Single-chip color CMOS image sensor with two or more line reading structure

The present invention is directed to a single-chip color CMOS image sensor with a novel two or more line reading structure which is compatible with MOS fabrication technology. The invention allows the simultaneous reading of line signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained without the use of an external delay line device. The sensor includes a pixel array having superimposed thereon a color filter pattern and a two or more line reading structure. The reading structure includes sets of storage capacitors on which the pixel signals are stored, and a means for reading the signals from the capacitors in such a way that signals from pixels in different rows may be combined. The reading structure is external to the pixel array but may still be fabricated on the same CMOS chip as the pixel array. By using a high-sensitivity interlace color structure that allows complementary sets of every other row to be read during alternating even and odd fields, the sensitivity of the device as a whole can be effectively doubled.