Nova Patents
EP0875855B1

Graphics processing system

Abstract

This record has no abstract on file.

EP0875855B1, drawing sheet 1
Sheet 1 of 69

Term

Term ended

Expired 29 April 2018, 8.4 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

22 claims: 9 independent, 13 dependent

  1. 1
    A method of rendering image data, the method comprising the steps of:generating a plurality of instruction streams (270,271);and executing instructions (Fig 9: 275) one at a time within a graphics co-processor (224) by performing sub-steps of: (a) determining (Fig 9: 276) one instruction stream from the plurality of instruction streams (270,271);(b) fetching (Fig 9: 277) an instruction not previously fetched from the determined instruction stream;(c) decoding (Fig 9: 278) the fetched instruction;(d) executing (Fig 9: 278) the decoded fetched instruction;and (e) repeating sub-steps (a) through (d);characterised in that : the graphics co-processor (224) comprises one or more reconfigurable units (240-243,246-249) for executing the instructions;the executing step (Fig 9: 275) further comprises the sub-step of reconfiguring (Fig 18: 330) at least one of the one or more reconfigurable units (240-243,246-249) in accordance with the decoded fetched instruction;and in the executing sub-step (Fig 9: 278), the decoded fetched instruction is executed using the at least one reconfigured reconfigurable unit.
  2. 9
    A method according to any of claims 6 to 8, wherein the one or more predefined priority rules include a rule that any one of the instruction streams that is designated as locked will be determined as being an instruction stream from which an instruction is to be fetched irrespective of an availability of instructions in another instruction stream.
  3. 10
    A method according to any of claims 6 to 9 when dependent on claim 3, wherein the one or more predefined priority rules include a rule that an instruction stream will be determined as being an instruction stream from which an instruction is to be fetched when its priority is a predetermined priority and a previous instruction last fetched was from the other instruction stream.
  4. 12
    Apparatus for rendering image data, the apparatus comprising a graphics co-processor (224) for accessing and executing instructions from a plurality of instruction streams (270,271), the graphics co-processor (224) comprising:means (235) for determining one instruction stream from the plurality of instruction streams (270,271);means (235) for fetching an instruction not previously fetched from the determined instruction stream;means (306) for decoding the fetched instruction;and means for executing the decoded fetched instruction;characterised in that : the means for executing the decoded fetched instruction comprises one or more reconfigurable units (240-243,246-249);and the graphics co-processor (226) further comprises means (321) for reconfiguring at least one of the one or more reconfigurable units (240-243,246-249) in accordance with the decoded fetched instruction to execute the instruction.
  5. 16
    Apparatus according to any of claims 12 to 14, further comprising a printer (225) arranged to receive and print a resulting image.
  6. 17
    Apparatus according to any of claims 12 to 16, wherein the determining means (235) is arranged to determine one instruction stream from the plurality of instruction streams (270,271) in accordance with a priority and one or more predefined priority rules.
  7. 20
    Apparatus according to any of claims 17 to 19, wherein the determining means is arranged to determine one instruction stream from the plurality of instruction streams according to the one or more predefined priority rules which include a rule that any one of the instruction streams that is designated as locked is to be determined as an instruction stream from which an instruction is to be fetched irrespective of an availability of instructions in another instruction stream.
  8. 21
    Apparatus according to any of claims 17 to 20 when dependent on claim 14, wherein the determining means is arranged to determine one instruction stream from the plurality of instruction streams according to the one or more predefined priority rules which include a rule that an instruction stream is to be determined as an instruction stream from which an instruction is to be fetched when its priority is a predetermined priority and a previous instruction last fetched was from the other instruction stream.
  9. 22
    Apparatus according to any of claims 12 to 21, wherein the graphics co-processor (225) is arranged to access and execute instructions from a plurality of instruction streams (270,271) which are generated in a host processor (202), and wherein the apparatus further comprises a buffer (203) for buffering the plurality of instruction streams generated by the host processor (202) for access by the graphics co-processor (224).
Independent claims9