Reconfigurable image processing pipeline

The present invention relates to an image processor (242) comprising a control register block (1470), a decoding block (1468), a data object processor (1462), and flow control logic. The control register block (1470) stores all the relevant information about the image processing operation. The decoding block (1468) decodes the information into configuration signals, which configure an input data object interface (1460). The input data object interface (1460) accepts and stores data objects from outside, and distributes these data objects to the data object processor (1462). For some image processing operations, the input data object interface (1460) may also generate addresses for data objects, so that the source of these data objects can provide the correct data objects. The data object processor (1462) performs arithmetic operations on the data objects received. The flow control logic controls the flow of data objects within the data object processing logic (1462). More particularly, the data object processor (1462) can comprise a number of identical data object sub-processors, each of which processes part of an incoming data object.