Nova Patents
EP0875853A2

Graphics processor architecture

Abstract

The present invention discloses an image processor (224) for executing a computer instruction set (280, 290) in the form of an opcode (281), at least one operand (283-285) which is, or indicates the location of data to be processed. The data to be processed consists of a variable length stream of data and each instruction includes a length field (297) containing data specifying the number of items of data to be processed or, if that number exceeds the size of the length field, a predetermined location of a previously allocated storage area at which that number is stored.

EP0875853A2, drawing sheet 1
Sheet 1 of 270

Term

Term ended

Projected expiry passed 29 April 2018, 8.4 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

27 claims: 11 independent, 16 dependent

  1. 1
    A graphics processor comprising:a plurality of interrelated functional modules;at least one register associated with each of the functional modules, each register being configured to control the function of its associated functional module;and an instruction controller for decoding instructions for use with the graphics processor, said instruction controller including register setting means to set the registers in accordance with a decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction.
  2. 4
    A graphics processor according to any one of the preceding claims, wherein each one of the functional modules provides a signal indicative of whether it is actively processing data.
  3. 5
    A graphics processor according to any one of the preceding claims, wherein the register setting means is one of a plurality of units able to set register values, the graphics processor further including arbitrator means to control which of the units is able to set the register values at a given time.
  4. 6
    A graphics processor according to any one of the preceding claims, wherein the values of the registers are set in a predetermined order.
  5. 8
    A graphics processor according to any one of the preceding claims, wherein each functional module includes an error, interrupt and exception signal output, which are asserted when an error, interrupt or exception, respectively, occurs in relation to the module in question.
  6. 9
    A graphics processor according to any one of the preceding claims, further including:a control bus interconnecting each of the registers;and control bus access means associated with each of the modules, thereby enabling the modules selectively to interact with the control bus.
  7. 10
    A graphics processor according to any one of the preceding claims, including a multi-used RAM for storing:(a) interval and fractional tables of data points, during colour conversion operations;(b) matrix coefficient data during image transformations and convolutions;and (c) double buffered minimal code units during JPEG operations.
  8. 12
    A graphics processor according to any one of the preceding claims, further including a JPEG unit capable of performing JPEG encoding and decoding, the coprocessor having a cache normally utilised for storing of recently used data and being adapted to store JPEG tables when the processor is performing JPEG operations.
  9. 21
    A method of processing graphics including the steps of:providing a plurality of interrelated functional modules;providing at least one register associated with each of the functional modules, each register being configured to control the function of its associated functional module;decoding an instruction for use with the graphics processor setting the registers in accordance with the decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction.
  10. 22
    An image processor for executing a computer instruction set comprising a plurality of instructions each of which has an instruction opcode and at least one operand, wherein said opcode corresponds to a type of calculation to be performed on the operand(s), each operand is data to be processed in said calculation or specifies the address of said data, the result of said calculation represents processed image data, and each instruction includes a length field containing data specifying the number of items of data to be processed or, if said number exceeds the size of said length field, a predetermined location of a previously allocated storage area at which said number is stored, whereby said processor for each instruction processes the corresponding said number of data items to thereby facilitate processing of variable length streams of data.
  11. 26
    An image processing method for executing a computer instruction set comprising a plurality of instructions each of which has an instruction opcode and at least one operand, wherein said opcode corresponds to a type of calculation to be performed on the operand(s), each operand is data to be processed in said calculation or specifies the address of said data, the result of said calculation represents processed image data, and each instruction includes a length field containing data specifying the number of items of data to be processed or, if said number exceeds the size of said length field, a predetermined location of a previously allocated storage area at which said number is stored, the method comprising the steps of:processing the corresponding said number of items of data for each instructions, wherein the processing of variable length streams of data is facilitated.
Independent claims11