OFDM system.

Technical Field

This invention relates generally to a telecommunication systems known as OFDM (Orthogonal Frequency Division Multiplexing), that is digital orthogonal frequency division multiplexing systems for data transmission, where data coming from a source are divided into a given number of data sequences and multiplexed according to a frequency division format.

In particular the invention finds its preferred application, while it is not limited to the same, in the field of digital television transmission systems.

Systems of this kind (or multicarrier) are employed to optimize the transmission of a large data flow, dividing the spectrum to be transmitted into a great number of sub-bands. This systems offers different advantages, such as for instance that to distribute the information avoiding troubles due to fading phenomena. The technical problem arising is therefore to manufacture a great number of high effective transreceivers, thus reducing in particular the number of complex operations to be made at each second.

Background Art

The status of the known technique and the present invention will described hereafter, mainly referring to the transmitting portion of the system since the receiving portion has an essentially dual structure and operation.

Referring to a transmitter for OFDM system in the general diagram (known) shown in Fig. 1, we start from a plurality of N data sequences (or channels), indicated with c_n(t), which is divided into 2N pairs, each pair of the sequence consisting of a real component R and of imaginary component IM. One sequence of the pair, for instance the real sequence, is delayed in a block DT, therefore both cross two separate interpolator filters G(f), then both the sequences of the pair are modulated (MD) with two carriers Pon(t) and Pin(t) having the same frequency, but 90° phase shifted, typically sine and cosine, and signals so modulated are summed up in an adder E which output consists of the V_R (to) signal.

Frequencies of the carriers Pon(t) and Pin(t) must be equidistant according to the relation:<maths id="math0001" num=""><img file="EP0668679A2_D0001.tif" /></maths>where F is the speed of data of each sequence.

In Figure 1, time spacing between two subsequent values of the sequences have been indicated with T and To.

A known embodiment, following this method for channel treatment, is outlined in Fig. 2, foreseeing to divide signal processing into four steps, through the processing indicated with DS(n), P&amp;O, SC and R respectively, and represented in summary through block arranged in cascade.

The operation made by the data staggering or shifting DS block (or Data Staggering) on data sequences c_n(t) involves a simple multiplication, by 1 or by -j, respectively, being j the imaginary unit produces sequences x_n(t) at output. The P&amp;O block for pre-modulation and ordering, involves operations such as the multiplication by j^k, the execution of connections and the possible extraction of a conjugate signal and its multiplication by j^k, producing at output the s_n(t) sequences.

Operations of DS, P&amp;O and R blocks are non critical, since the same are operations of neglectable calculation complexity, while critical processing, as for the speed and complexity aspects are those to be made in the SC block.

Referring to Fig. 3, according to a solution described by B. Hirosaki in "An Orthogonally Multiplexed QAM System Using Discrete Fourier Transform, IEEE Trans. on Communications, vol. COM-29, No. 7, July 1881, the processing indicated by SC is made in three steps, that is through a processor (or similar device) able to perform an N-DFT (discrete Fourier transform on N points), the passage through a polyphase network PN consisting of N filters operating at low rate, and then a parallel-series conversion in the P/S block.

More in detail, the solution shown in Fig. 3 foresees an N-DFT processor performing the discrete Fourier transform on N channels from 0 to N-1, a polyphase network PN having N inputs connected to the N-DFT processor, and N outputs connected to a parallel-series converter P/S. Components N-DFT and PN operate at (low) rate F of the N input channels, while the output is high rate Fo, namely N times bigger than F.

Finally, coming back to the general diagram of Fig. 2, the R block, simply extracts the real portion.

According to another known solution (see G. Cariolaro and others "A new architecture for orthogonally multiplexed QAM signals", GLOBECOM 1993), operations of the SC block can be made by the architecture shown in Fig. 4 foreseeing a parallel-series converter P/S supplied by the N channels 0 to N-1, which single output is connected to a sole polyphase filter PF, which is an all-pass filter with constant phase in each side band of the resulting OFDM signal. The filter output is connected to a multitone modulator MTM receiving a carrier y(F_ot) and producing N simultaneous shifts in frequency, that is it performs a multitone modulation of the input signal. The multitone modulator output is connected to an equalizer H_E(f).

According to the solution shown in Fig. 4, the serial operating mode is performed instead of the parallel one, that is all the components operate at a high rate Fo = N.F, where F is the rate of each one of the N input channels. The circuit simplification involves on the other hand the immediate passage to a high rate operation.

Objects of the Invention

The object of this invention is to improve the above mentioned transmission and reception systems, and particularly to reduce the circuit complexity of an OFDM system.

Disclosure of the invention

In accordance with the invention this object is reached through an orthogonal frequency division multiplexing system (OFDM) for the transmission of N data sequences or channels at a set rate F, consisting of a transmitter including: <ul id="ul0001" list-style="none"><li>- data staggering means receiving said sequences at input;</li><li>- pre-modulation and ordering means connected to the outputs of said data staggering means; and</li><li>- multiplexing means;</li><li>- parallel series conversion means connected to the outputs of said multiplexing means, characterized by the fact that said multiplexing means include:</li><li>- a first rate converter, having N inputs and I outputs, where N = M.I, with integer M and I, producing at output I channels at a rate F₁ higher than F;</li><li>- a first processor which inputs are connected to the outputs of said first converter, and performing the discrete Fourier transform on I channels;</li><li>- a first plurality of multitone modulators, each one connected to an output of said first processor, and receiving on the other input a carrier:<maths id="math0002" num=""><img file="EP0668679A2_D0002.tif" /></maths>where .8M(n) is the remainder of the integer division of n by M and<maths id="math0003" num=""><img file="EP0668679A2_D0003.tif" /></maths></li><li>- a first plurality of polyphase filters, each one connected to the output of a corresponding multitone modulator of said first plurality;</li><li>- a second plurality of multitone modulators, each one connected to the output of the corresponding polyphase filter of said first plurality Q(f) and receiving on the other input a carrier<maths id="math0004" num=""><img file="EP0668679A2_D0004.tif" /></maths></li></ul>

The invention foresees therefore the factorisation by M and by I of the N input channels and the use of said multitone modulators connected upstream and downstream versus said polyphase filters.

It is possible to demonstrate that the use of the above mentioned multitone modulators allows to drastically reduce the complexity, in terms of operations to be made, of said processor performing the discrete Fourier transform on input channels compared with the complexity of the corresponding processor foreseen in the solution proposed by B. Hirosaki, with ensuing considerable advantages as for complexity/cost of the whole transmission system.

The invention consists also in a system with orthogonal frequency division multiplexing (OFDM), characterized by the fact that the receiver includes: <ul id="ul0002" list-style="none"><li>- parallel series conversion means receiving at input the signal emitted by the transmitter;</li><li>- demultiplexing means including: <ul id="ul0003" list-style="none"><li>a) a third plurality of multitone modulators each one connected to one of the I outputs of said series- parallel conversion means, and receiving on the other input a carrier:<maths id="math0005" num=""><img file="EP0668679A2_D0005.tif" /></maths></li><li>b) a second plurality of polyphase filters, each one connected to the output of the corresponding modulator of said third plurality of multitone modulators;</li><li>c) a fourth plurality of modulators, each one connected to the output of a corresponding filter of said second plurality of polyphase filters, and receiving on the other input a carrier:<maths id="math0006" num=""><img file="EP0668679A2_D0006.tif" /></maths>where .8M(n) is the remainder of the integer division of n by M and W_N=exp^(j2π/N;</li><li>d) a second processor which inputs are connected to the outputs of multitone modulators of the fourth plurality, and performing the reverse discrete Fourier transform on I channels;</li><li>e) a second rate converter, having I inputs and N outputs, where N = M.I, with M and I integer, producing at output N channels at a rate F lower than F₁;</li></ul></li><li>- demodulation and ordering means connected to the outputs of said demultiplexing means;</li><li>- means for re-alignment of data receiving at input the outputs of demodulation and ordering means and emitting at output data sequences.</li></ul>

The invention consists also of an orthogonal frequency division multiplexing method (OFDM) for the transmission of N data sequences or channels having a set rate F, said method including the following steps: <ul id="ul0004" list-style="none"><li>a - to submit said sequences to data staggering;</li><li>b - to pre-modulate and order the sequences so treated;</li><li>c - to multiplex the pre-modulated and ordered sequences;</li><li>d - to convert said sequences into a serial stream; characterized by the fact to foresee also the following steps:</li><li>b1 - to convert said N pre-modulated and ordered sequences in I channels having a rate F1 higher than said set rate F, where N = M.I;</li><li>b2 - to perform the discrete Fourier transform on I channels;</li><li>b3 - to modulate each one of the I channels where the Fourier transform has been made with a carrier:<maths id="math0007" num=""><img file="EP0668679A2_D0007.tif" /></maths>where β_M(n) is the remainder of the integer division of n by M and W_N=exp^(j2π/N);</li><li>b4 - to filter said modulated I channels;</li><li>b5 - to modulate each one of the I channels filtered with a carrier:<maths id="math0008" num=""><img file="EP0668679A2_D0008.tif" /></maths></li></ul>

Finally the invention consists of a method for orthogonal frequency division demultiplexing method (OFDM) of a multiplexed signal, said method foreseeing the following steps: <ul id="ul0005" list-style="none"><li>- to convert the serial signal received into I parallel channels, having a transmission rate F1 higher than the set rate F;</li><li>- to demodulate each one of the I parallel channels with a carrier:<maths id="math0009" num=""><img file="EP0668679A2_D0009.tif" /></maths></li><li>- to filter the I channels so demodulated;</li><li>- to additionally demodulate the I channels filtered with a carrier:<maths id="math0010" num=""><img file="EP0668679A2_D0010.tif" /></maths>where β_M(n) is the remainder of the integer division of n by M and W_N=exp^(J2πN);</li><li>- to make the reverse discrete Fourier transform on the I demodulated channels;</li><li>- to convert the I channels submitted to Fourier transform into N channels having a rate F lower than the transmission rate F1 and equal to the set rate, where N = M.I;</li><li>- to demodulate and order the N channels at set rate F and re-align data so ordered to obtain the sequences of data transmitted in origin.</li></ul>

Brief Description of the Drawings

The features of the invention that are believed to be novel are set forth with particularity in the appended claims.

The invention together with further objects and advantages thereof may be understood with reference to the following description taken in conjunction with the accompanying drawings and in which: <ul id="ul0006" list-style="none"><li>Fig. 1, already described, outlines the treatment of one of the pair of sequences according to the conventional scheme;</li><li>Fig. 2, already described, shows the general processing diagram of an OFDM system in transmission;</li><li>Fig. 3, already described, shows a known diagram of the SC unit of Fig.2,</li><li>Fig. 4, already described, shows another known diagram of the SC unit of Fig.2,</li><li>Fig. 5 shows a realization diagram of the SC unit of Fig. 2 realized according to the invention;</li><li>Fig. 6 shows the general diagram for the processing of an OFDM system in reception; and</li><li>Fig. 7 shows a realization form of the CS unit of Fig.6 realized according to the invention.</li></ul>

Detailed Description of a Preferred Embodiment

According to the invention, the SC portion in transmission (and the CS portion in reception) contains the system computation complexity. The complete diagram of the transmitter is obtained adding the DS, P&amp;O and R indicated in Fig. 2, while the complete one of the receiver is obtained adding the parts D&amp;O and DDSK portions indicated in Fig. 6 to the CS portion shown in the detail of Fig. 7.

Making particular reference to Fig. 5, showing the SC unit of Fig. 2 realized according to the invention, the number N of sequences (or channels) at input So, S₁, S₂, .. S_N-₁ is divided into two factors M and I, integer and such that N = M.I.

For instance, in the case of N = 128, M and I values can be equal to 32 and to 4, respectively, or to 16 and 8, or 8 and 16.

It must be noticed that the transmitter diagram foresees the following rates: <ul id="ul0007" list-style="none"><li>- "low" rate F relevant to each data sequence;</li><li>- "high" rate Fo = N.F;</li><li>- "medium" rate F1 = M.F, where M = N/I.</li></ul>

Consequently the following time spacings of sequences are obtained: <ul id="ul0008" list-style="none"><li>- T=1/F;</li><li>- T1=1/F1;</li><li>- To=1/Fo.</li></ul>

The N origin channels So - S_N-₁ are brought to the input of a rate converter LMRC (low to medium) producing ar output a number I of channels ao, a₁, .. a_l-₁.

The outputs I of the LMRC converter form the inputs of an I-DFT processor (I points) performing the reverse discrete Fourier transform on the I input channels.

The outputs of the I-DFT processor are connected to the same number of multitone modulators of a first plurality Ao, A, , A₂, .. A_I-1 receiving on the other input the carriers:<maths id="math0011" num=""><img file="EP0668679A2_D0011.tif" /></maths>where β_M(n) is the remainder of the integer division of n by M and W_N=exp^(j2π/N).

The outputs A of multitone modulators are connected to a set of polyphase filters consisting of I different filters Q_;(f), each one having a response to the pulse given by:<maths id="math0012" num=""><img file="EP0668679A2_D0012.tif" /></maths>where h(To) is the S/P of the response to the pulse h(to) = g(to)e^J2πF/4TO, and<maths id="math0013" num=""><img file="EP0668679A2_D0013.tif" /></maths>

The outputs of polyphase filters Q_;(f) are connected to a second set of multitone modulators consisting of modulators B_o, B₁, B₂, .. B_I-₁, identical and supplied by carriers expressed by:<maths id="math0014" num=""><img file="EP0668679A2_D0014.tif" /></maths>

It must be noticed that I-DFT components, A, Q and B operate at an "intermediate" rate F₁ = M.F = F0/I

The outputs of B multitone modulators are connected to a parallel/series converter P/S, which output is connected to an equalizer H_E(f) producing the output signal v.

As for the receiving portion, which is dual of the transmission one, Fig. 6 shows the general processing diagram of the receiver including an equalizer H_E(f)_R, at which output a serial-parallel converter S/P is connected and which outputs are connected to the CS device performing the essential portion of demultiplexing, and to the D&amp;O demodulation and ordering means to the output of which the DDSK data re-alignment means are connected.

Fig. 7 shows more in detail the structure of the CS device of figure 6 including a first plurality of multitone demodulators MTM1, each one connected to an output of said serial-parallel (S/P) conversion means, and receiving on the other input a carrier

<maths id="math0015" num=""><img file="EP0668679A2_D0015.tif" /></maths>

The outputs of multitone demodulators are connected to a corresponding plurality of polyphase filters Q_;(f)_R, each one of which has an output connected to a respective demodulator of a second plurality of multitone demodulators MTM2 and receiving on the other input a carrier:<maths id="math0016" num=""><img file="EP0668679A2_D0016.tif" /></maths>where β_M is the remainder of the integer division of n by M;

The outputs of demodulators are connected to a DFT processor performing the discrete Fourier transform on channels and the outputs of the processor are connected to a medium to low rate converter (MLRC) having I inputs and N outputs, where N = M.I, with M and I integer, producing at output N channels so, S₁, S₂, .. N- at a rate F lower than F₁.

Factorisation by M and I of the N input channels and the use of multitone modulators transmission side (A,B) and reception side (MTM1, MTM2) allows to obtain considerable advantages.

In particular, from the studies conducted by the Applicant, we can demonstrate that the above mentioned innovative solutions allow to drastically reduce the complexity of said processors I-DFT and DFT performing the transform, namely the reverse Fourier transform on input channels, allowing to reduce the complexity/cost of the whole transmission system.

While a particular embodiment of the present invention has been shown and described, it should be understood that the present invention is not limited thereto since other embodiments may be made by those skilled in the art without departing from the true scope thereof. It is thus contemplated that the present invention encompasses any and all such embodiments covered by the following claims.