A semiconductor device and a process for manufacturing thereof.
Abstract
A semiconductor device comprising a plurality of semiconductor chips (3,4) and a lead frame (5) incorporated in a single package made of a molding resin (1), in which all or majority of the space between the principal plane (3a) of the first semiconductor chip and the principal plane 4a) of the second semiconductor chip is filled up with a deformation preventive resin (13) capable of withstanding the resin forming heat and resin filling pressure of the molding resin (1) for preventing damages due to deformation of semiconductor chips (3,4) and process for manufacturing the semiconductor device.

Term
Term ended
Projected expiry passed 29 June 2009, 17.2 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
11 claims: 2 independent, 9 dependent
- 1A semiconductor device comprising a plurality of semiconductor chips (3, 4) and a lead frame (5) incorporated in a single package made of a molding resin (1), in which all or majority of a space between a principal plane (3a) of the first semiconductor chip is filled up with a deformation preventive resin (13) for preventing damages due to deformation of semiconductor chips.
- 6A process for manufacturing semiconductor device comprising the steps of:forming on a principal plane (3a) of a first semiconductor chip (3), electrode terminals (3b) electrically connected with electrode terminals (4b) of a second semiconductor chip (4) and electrode terminals (3c) electrically connected with an electrode terminal (5a) of the lead frame (5);forming a protective film (6) on the other principal plane (3a) of the first semiconductor chip (3);forming on a principal plane (4a) of the second semiconductor chip (4), electrode terminals (4b) electrically connected with the electrode terminals (3b) of the first semiconductor chip (3);forming a protective film (7) on the other principal plane (4a) of the second semiconductor chip (4);connecting electrically a metallic film (9) of the electrode terminals (3b) of the first semiconductor chip (3) and a metallic film (10) of the electrode terminals (4b) of the second semiconductor chip (4) by way of the solder bumps (8);filling a space of tbe principal plane (3a) of the first semiconductor chip (3) and the principal plane (4a) of the second semiconductor chip (4) with a deformation preventive resin (13) other than a molding resin (1);packaging the semiconductor chips (3, 4) by the molding resin (1);and cutting and forming the lead frame (5) into a desired shape.
Independent claims2
47 paragraphs in 4 sections, as filed
BACKGROUND OF THE INVENTION
1. Field of the Invention
0001The present invention relates to a semiconductor device, more particularly to its packaging and a process for manufacturing thereof.
2. Description of the Prior Art
0002Recently as effective means for driving plural semiconductor chips as a system, various methods have been proposed for installing these semiconductor chips into a single ceramic package three-dimensionally, or so-called three-dimensional multi-chip packaging. These techniques are, however, high in the package cost because expensive ceramic packages are used, and this problem has been a bottleneck for obtaining a wide demand.
0003To solve this problem, for example, three-dimensional multi-chip packages using inexpensive resin molded packages have been already disclosed in the Japanese Laid-Open Patent Application Pub. Nos. 56-62350, 56-62351, and 58-130553 (hereinafter called the first prior art).
0004In the first prior art, however, the semiconductor chips are fixed to both sides of the chip mounting part of the lead frame, and the electrical connection between semiconductor chips is effected through the lead frame, and therefore multi-terminal connection between semiconductor chips is not realized.
0005Accordingly, to solve the above problem, a method of connecting two semiconductor chips opposingly, with the principal planes mutually spaced at a specific interval by way of a film carrier was proposed in the Japanese Laid-Open Patent Application Pub. No. 61-248541 (hereinafter called the second prior art).
0006In the second prior art, however, although multi-terminal connection between semiconductor chips is possible structurally, since the film carrier method is employed, take-out of electrodes is limited to the peripheral region free from elements on the secmiconductor chip. Furthermore, since the space between the principal planes of the confronting semiconductor chips is not filled with resin material or the like, the semiconductor chip may be deformed by the heat and resin filling pressure (usually 50 to 100 kg/cmz) at the time of resin molding, and the element characteristics may be spoiled.
0007Besides, other three-dimensional structures of semiconductor chips have been also proposed, for example, in the Japanese examined Patent Application Pub. No. 58-45822 (hereinafter called the third prior art) and the Japanese Laid-Open Patent Application Pub. No. 59-88863 (hereinafter called the fourth prior art), and in the third prior art the space between the semiconductor chips is vacant same as in the second prior art, and in the fourth prior art only the surrounding parts between the semiconductor chips are affixed with resin. Therefore, when these semiconductor chips are packaged by using a molding resin, the semiconductor chips are similarly deformed, and the element characteristics deteriorate.
SUMMARY OF THE INVENTION
0008It is hence a primary object of the invention to present a semiconductor device small in size and multiple in function, capable of connecting plural semiconductor chips with multiple terminals, and packaging by molding resin without deterioration of element characteristics due to deformation of semiconductor chips, and a process for manufacturing the semiconductor device.
0009In order to accomplish the above object, a semiconductor device according to the invention, comprises a plurality of semiconductor chips and a lead frame incorporated in a single package made of a molding resin, in which all or majority of a space between a pricnipal plane of the first semiconductor chip and a principal plane of the second semiconductor chip is filled up with a deformation preventive resin for preventing damages due to deformation of semiconductor chips.
0010In a preferred embodiment, the deformation preventive resin is capable of withstanding resin forming heat and resin filling pressure of a molding resin as the characteristic after curing.
0011In another preferred embodiment, the deformation preventive resin is capable of flowing smoothly into the space between the semiconductor chips as the characteristic before curing.
0012In still another embodiment, the deformation preventive resin is of solvent-free type and small in contraction.
0013In a further preferred embodiment, the deformation preventive resin comprises a filler and one or plural resin selected from the group of epoxy resin, urea resin, melamin resin and phenol resin.
0014A process for manufacturing semiconductor device in another aspect of the invention, comprises the steps of: forming on a principal plane of a first semiconductor chip, electrode terminals electrically connected with electrode terminals of a second semiconductor chip and electrode terminals electrically connected with an electrode terminal of the lead frame; forming a protective film on the other principal plane of the first semiconductor chip; forming on a principal plane of the second semiconductor chip, electrode terminals electrically connected with the electrode terminals of the first semiconductor chip; forming a protective film on the other principal plane of the second semiconductor chip; connecting electrically a metallic film of the electrode terminals of the first semiconductor chip and a metallic film of the electrode terminals of the second semiconductor chip by way of the solder bumps; filling a space of the principal plane of the first semiconductor chip and the principal plane of the second semiconductor chip with a deformation preventive resin other than a molding resin; packaging the semiconductor chips by the molding resin; and cutting and forming the lead frame into a desired shape.
0015In a preferred embodiment, the deformation prevent resin may contain a gap enough to withstand resin molding heat and resin filling pressure of the molding resin.
0016In another preferred embodiment, the deformation prevent resin has the coefficient of thermal expansion nearly equal to that of solder material of the solder bumps.
0017In still another preferred embodiment, a different semiconductor chip is connected on the first semiconductor chip.
0018In a further preferred embodiment, two or more other semiconductor chips are connected on the first semiconductor chip.
0019In a yet further preferred embodiment, a third or more semiconductor chip is connected on the second semiconductor chip.
0020In this means for solving the problems, by filling the space between the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 with the deformation preventive resin 13 capable of withstanding the resin molding heat and resin filling pressure of the molding resin 1, deterioration of the element characteristics due to deformation of semiconductor chips by heat or pressure at the time of filling with molding resin can be prevented. The plural semiconductor chips can be connected with multiple terminals, thereby realizing a resin molded packaging without causing deterioration of element characteristics due to deformation of semiconductor chips.
0021As clear from the description herein, according to the invention, deterioration of element characteristics derived from deformation of semiconductor chips due to heat or pressure of filling with molding resin can be prevented by filling the space between the principal plane of the first semiconductor chip and the principal plane of the second semiconductor chip with a deformation preventive resin capable of withstanding the resin molding heat and resin filling pressure of the molding resin, and therefore excellent effects are brought about, such as multi-terminal connection of plural semiconductor chips and resin molded packaging without deterioration of element characteristics due to deformation of semiconductor chips.
BRIEF DESCRIPTION OF THE DRAWINGS
0022These and other objects of the invention, as well as the features and advantages thereof, will be better understood and appreciated from the following detailed description taken in conjunction with the drawings, in which: <ul id="ul0001" list-style="none"><li>Fig. 1 is a sectional view of a semiconductor device in a first embodiment of the invention;</li><li>Fig. 2 is an enlarged sectional view of the essential parts of the same;</li><li>Fig. 3 is an enlarged sectional view of the essential parts of a second embodiment of the invention;</li><li>Fig. 4 is an enlarged sectional view of the essential parts of a third embodiment of the invention; and</li><li>Fig. 5 is an enlarged sectional view of the essential parts of a fourth embodiment of the invention.</li></ul>
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
0023Referring now to the drawings, some of the preferred embodiments of the invention are described in details below.
0024Fig. 1 is a sectional view of a semiconductor device in a first embodiment of the invention, and Fig. 2 is an enlarged sectional view of the essential parts of the same.
0025As shown in the drawings, the semiconductor device of the invention has a plurality of semiconductor chips 3, 4 and a frame 5 incorporated in a single package 2 made of a molding resin 1, in which the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of other at least one second semiconductor chip 4 are disposed opposite to each other.
0026On the principal plane 3a of the first semiconductor chip 3, as shown in Fig. 2, electrode terminals 3b to be electrically connected with electrode terminals 4b of the second semiconductor chip 4, and electrode terminals 3c to be electrically connected with an electrode terminal 5a of the lead frame 5 are formed, and a protective film 6 for example SiO₂, SiN and so on is formed on the other principal plane 3a.
0027On the other hand, on the principal plane 4a of the second semiconductor chip 4, the electrode terminals 4b to be electrically connected with the electrode terminals 3b of the first semiconductor chip 3 are formed, and a protective film 7 for example SiO₂, SiN and so on is formed on the other principal plane 4a.
0028On the surface of the electrode terminal 3b, in order to obtain a favorable electrical connection with solder bumps 8 formed on the electrode terminal 4b of the second semiconductor chip 4, a three-layered metal film 9 of, for example, titanium-tungsten alloy (800Å)/copper (2400Å)/solder (5 µm) is formed.
0029On the surface of the electrode terminals 4b, in order to form the solder bumps 8, a two-layered metal film 10 of, for example, titanium-tungsten alloy (800Å)/copper (2400Å) is formed, and the solder bumps 8 are formed thereon by vacuum deposition, plating or other method.
0030As the material for the solder bumps 8, it is necessary to select from those withstanding the temperature when filling with molding resin (170 to 190°C), and in this embodiment an alloy of tin (Sn)/lead (Pb) = 5/95 (melting point 300°C) is used.
0031The electrode terminals 3b of the first semiconductor chip 3 and the electrode terminals 4b of the second semiconductor chip 4 are connected together by the reflow method by overlaying the electrode terminals 4b on the electrode terminals 3b.
0032The lead frame 5 is composed of, as shown in Fig. 1, the electrode terminal 5a and a mounting part 5b on which the first semiconductor chip 3 is mounted, and the first semiconductor chip 3 is affixed to the mounting part 5b by means of a die-bonding agent 11.
0033The electrode terminal 5a and the electrode terminals 3c are electrically connected by means of bonding wire 12 such as aluminum wire and gold wire.
0034The space between the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 is preliminarily filled with a deformation preventive resin 13 (liquid thermoset resin) other than the molding resin by means of dispenser or the like, and is later cured in a heating over or the like.
0035The liquid thermoset resin 13 is required to flow smoothly into the space between the semiconductor chips as the characteristic before curing, and to be of solvent-free type and small in contraction by hardening owing to the necessity of filling the interface completely also after curing. Also as the characteristic after curing, owing to the necessity of minimizing the stress of the connections of solder bumps 8, it is desired that the coefficient of thermal expansion be nearly equal to that of solder material, and it is also necessary to select a material having mechanical properties capable of sufficiently withstanding the resin injection pressure of the molding resin 1 in the subsequent resin forming process. This is particularly important for preventing damages due to deformation of semiconductor chips caused by the stress of injection of molding resin.
0036As the resin satisfying such conditions, in this embodiment, an epoxy resin containing a filler (e.g. XNR5008-1, manufactured by Nagase Chiba K.K., 1-1-17 Shimmachi, Nishi-ku, Osaka) is used.
0037The semiconductor chips 3, 4 are packaged by the molding resin 1 using a die, and the lead frame is cut and formed into a desired shape.
0038Therefore, at the time of manufacture of the semiconductor device of the invention, first, the metallic film 9 of the electrode terminals 3b of the first semiconductor chip 3 and the metallic film 10 of the electrode terminals 4b of the second semiconductor chip 4 are electrically connected with each other by way of the solder bumps 8, and the solder bumps 8 are made of tin (Sn)/lead (Pb) = 5/95 alloy so as to withstand the temperature at the time of filling with molding resin 1.
0039Next, the space of the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 is preliminarily filled with the deformation preventive resin 13 other than the molding resin 1. As the characteristic of the deformation preventive resin 13 after curing, in order to minimize the stress at the connections of the solder bumps 8, the material should be selected from those having the coefficient of thermal expansion nearly equal to that of the solder material and mechanical properties capable of sufficiently withstanding the injection pressure of the molding resin 1 in the resin forming process.
0040In this way, by filling the space between the principal plane 3a of the first semiconductor chip 3 and the principal plane 4a of the second semiconductor chip 4 with the deformation preventive resin 13 capable of withstanding the resin molding heat and resin filling pressure of the molding resin 1, deterioration of the element characteristics derived from the deformation of semiconductor chips due to heat or pressure of filling with molding resin can be prevented, and therefore multi-terminal connection of plural semiconductor chips may be realized, so that the resin molded packaging may be achieved without deterioration of element characteristics due to deformation of the semiconductor chips.
0041In the foregoing embodiment, a different semiconductor chip was connected on a first semiconductor chip, but the invention is equally valid, needless to say, when two or more semiconductor chips 4, 14 are connected on the first semiconductor chip as shown in a second embodiment in Fig. 3, or when a third semiconductor chip 14 is connected on the second semiconductor chip as shown in a third embodiment in Fig. 4.
0042Incidentally, as shown in a fourth embodiment in Fig. 5, the curing state of the setting resin of the deformation preventive resin may not always be in the airtight state as in the first embodiment, but also contain a gap 15 enough to withstand the resin molding heat and resin filling pressure of the molding resin.
0043This invention, meanwhile, is not limited to the foregoing embodiments alone, but may be variously modified or changed within the scope of the invention.
0044For example, instead of the epoxy resin used as the deformation preventive resin (thermoset resin) in the mentioned embodiment, urea resin, melamin resin, or phenol resin may be used. These thermoset resins are generally excellent in heat resistance and solvent resistance, and are capable of realizing a tough forming by using a filler.
0045The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and the range of equivalency of the claims are therefore intended to be embraced therein.
Contents4
4 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| AU656595B2 | Cited by | Australia | Search report |
| EP0913866A1 | Cited by | European Patent Office (EPO) | Search report |
| EP0706219A1 | Cited by | European Patent Office (EPO) | Search report |
| WO9737374A3 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| EP0961319A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1427016A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1688993A3 | Cited by | European Patent Office (EPO) | Search report |
| US6515370B2 | Cited by | United States of America | Applicant |
| WO2004064139A2 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US7119445B2 | Cited by | United States of America | Applicant |
| EP0642157A1 | Cited by | European Patent Office (EPO) | Search report |
| US7932612B2 | Cited by | United States of America | Applicant |
| CN1041579C | Cited by | China | Search report |
| CN1110094C | Cited by | China | Search report |
| WO9202039A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| EP0740343A2 | Cited by | European Patent Office (EPO) | Search report |
| WO2004064139A3 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| WO9737374A2 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| EP0841700A2 | Cited by | European Patent Office (EPO) | Search report |
| US6989605B2 | Cited by | United States of America | Applicant |
| EP1688993A2 | Cited by | European Patent Office (EPO) | Search report |
| EP0841700A3 | Cited by | European Patent Office (EPO) | Search report |
| EP0642157A1 | Cited by | European Patent Office (EPO) | Search report |
| FR2709871A1 | Cited by | France | Search report |
| US5274913A | Cited by | United States of America | Search report |
| US6803663B2 | Cited by | United States of America | Applicant |
| EP0961319A2 | Cited by | European Patent Office (EPO) | Search report |
| EP0740343A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1427016A2 | Cited by | European Patent Office (EPO) | Search report |
| US8134237B2 | Cited by | United States of America | Applicant |
| EP1447849A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1447849A2 | Cited by | European Patent Office (EPO) | Search report |
| EP0913866A4 | Cited by | European Patent Office (EPO) | Search report |
| FR2709871A1 | Cited by | France | Search report |
| US7229851B2 | Cited by | United States of America | Applicant |
| US6037666A | Cited by | United States of America | Search report |
| WO9737374A3 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US7436071B2 | Cited by | United States of America | Applicant |
| US7598619B2 | Cited by | United States of America | Applicant |
| WO9202039A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| EP0031240A2 | Cites | European Patent Office (EPO) | Search report |
2 priority claims, no other members on record
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 16555188 | Japan | – | |
| 16555188 | Japan | A |
8 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Application deemed to be withdrawnWithdrawn18D | 18D | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWNSTAA | STAA | |
| First examination report despatched17Q | 17Q | |
| Designated contracting statesAK | AK | |
| Search report despatchedORIGINAL CODE: 0009013PUAL | PUAL | |
| Request for examination filed17P | 17P | |
| Designated contracting statesAK | AK | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 0348972
- Application
- 891118564
Titles3
- German
- Halbleiteranordnung und Verfahren zum Herstellen derselben
- English
- A semiconductor device and a process for manufacturing thereof
- French
- Dispositif semi-conducteur et procédé pour sa fabrication
Classification
- CPC, 19
- H10W90/00
- H10W74/012
- H10W74/15
- H10W74/121
- H10W90/732
- H10W90/736
- H10W90/722
- H10W72/0198
- H10W72/536
- H10W72/5363
- H10W72/856
- H10W90/756
- H10W72/884
- H10W90/754
- H10W90/724
- H10W90/291
- H10W74/00
- H10W72/5522
- H10W72/5524
- IPC, 6
- H01L23 29
- H01L23 31
- H01L25 065
- H01L25 07
- H01L25 18
- H10W74 01
Designated states1
- Contracting states, 1
- France