Digital signal processing device and audio signal reproduction device

Specification A digital-signal-processing device and sound signal reproducer Technical field

It is related with the present invention and a sound signal reproducer. In particular, it has a Delta sigma modulation circuit. It is related with Audio signal reproduction device. It is related with the present invention and a digital-signal-processing device.

Background art

Audio signal reproduction device which plays the audio signal stored in recording media, such as CD and MD As Place, it is Multi bit. A P CM (Pulse Code Modulation) Method sound signal reproduction A device and a 1-bit method sound signal reproducer are mentioned. A 1-bit method is Multi. It is a method which can reproduce a sound source faithfully rather than a Tut P CM method.

Sound which is the conventional 1-bit method sound signal reproducer and a multibit digital signal A voice signal is coded to a 1-bit digital signal, the 1-bit digital signal -- Digital amplification is carried out -- the 1-bit digital signal by which digital amplification was carried out -- low pass filter (for example, Provisional-Publication-No. 1 0 -- refer to 3 222 1 No. 5 gazette) changed into the reproduction signal which is therefore an analog signal.

the example of 1 composition of the PDM (Pulse Densi ty Modulation) signal generation circuit with which the conventional 1-bit method sound signal reproducer is provided here -- a figure -- it is shown in 5.

the P DM signal generation circuit of Drawing 5 -- input terminal I N, output terminal OUT, and multiplier 1 0 1 *: L 11 and adding machine 1 1 2*1 1 9 and quantization machine 1 20 and And delay device 1 2 1*1 It is constituted by 28. Multiplier 10 1 and 10 2, ..., 1 1 The multiplication coefficient of 1 is That. It is Each m 1, m2, ..., ml 1.

As opposed to the audio signal whose P DM signal generation circuit of Drawing 5 is a multibit digital signal 7th The delta sigma abnormal conditions are performed, and the P DM signal which is a 1-bit digital signal is generated. It carries out. P DM signal is the pulse same as amplitude and time width. Density of a pulse, That is A level of a signal is expressed by changing Occurrence frequency. In order to reproduce faithfully the P DM signal generation circuit of Drawing 5, and a sound source, even output terminal OUT is very quick Samp of 2. 8MH z or 5. 6 MH z from input terminal I N. Data is processed on ring frequency.

It is a quantization error the case where delta sigma abnormal conditions generate a 1-bit digital signal. An ingredient serves as distribution shifted to the high region. this, as a "noise shaving" -- Knowledge -- Being done . Therefore, it is used for the quantization noise reduction of a frequency band (for example, audible zone) made into the PDM signal generation circuit of Drawing 5, and the object, and is I I R. It plays the role of a filter (Infinite-d uration Impulse Response). Thereby, they are the object and To. SZN of the area within Frequency band can be secured and broadband-ization can be attained.

With a deer, a sampling frequency is very quantity in the P DM signal generation circuit of Drawing 5. Since the influence of To (for example, 2. 8MH z, 5. 6MH z, etc.) and unnecessary radiation is great, it is a steel plate. When [ be / sufficient measures against a noise' shield, such as a double shield by a And copper plate, / indispensable ] To. for this reason -- in a sound signal reproducer -- a shield steel plate etc. . -- remarkable space it will occupy -- since the weight of a sound signal reproducer also increases -- a sound signal reproducer -- small -- Model-ized and a weight saving were not able to be attained.

Since many multipliers and adding machines are used, the P DM signal generation circuit of figure .5 is a time. Intermediary There was with a large way scale. And since the circuit scale is large, power consumption is also size Hear. Ivy. furthermore -- the PDM signal generation circuit of Drawing 5 is generally analog circuitry -- One piece Since only processing of only Nellnell corresponds, it is use with stereo (L c h, Rc h). the case where it carries out -- a figure -- two P DM signal generation circuits shown in 5 had to be provided. P DM signal generation circuit is carrying out circuit composition complicated in this way with an immense circuit scale. It was difficult to carry in L S I conventionally from things. For this reason, Audio signal reproduction device Miniaturization and the weight saving of Place were not able to be attained.

P DM signal generation circuit of Drawing 5, Since it has the above-mentioned problem Low-power-consumption-izing, Small a weight saving and a portable type sound signal reproducer with an indispensable cost cut -- especially -- un--- It is direction., It was not adopted as a portable type sound signal reproducer. The indication of an invention

an example is taken by the present invention and the above-mentioned problem -- 1 bit which can attain miniaturization and a weight saving It aims at providing a method sound signal reproducer. the present invention and the above-mentioned question an example is taken by Subject -- the digital-signal-processing device which can make a circuit scale small -- To provide It aims at To.

To achieve the above objects, in the digital-signal-processing device concerning the present invention, An adding means and the multiplication means of The 1 which multiplies a predetermined multiplication value to a signal, the above-mentioned adding means a multiplication value predetermined to the output signal of the delay means which delays an output signal, and the above-mentioned delay means -- Power it has a multiplication means of The 2 which carries out Calculation -- the above-mentioned adding means, Output signal of the multiplication means of above-mentioned The 1 An item and output signal of the above-mentioned delay means, it is addition about the reversal output signal of the multiplication means of above-mentioned The 2 it carries out -- the output of the above-mentioned adding means -- the multiplication means And above-mentioned delay means of above-mentioned The 1 Composition which processes a signal by repeating processing in which it inputs, two or more times, and performing it It carries out. The memory measure which memorizes the output signal of the above-mentioned adding means and the total adding means, it has a quantization means -- addition processing is performed by the above-mentioned adding means -- until -- one step It is. In the 1st step, it is a place at the multiplication means of above-mentioned The 1 about the input signal from the outside. After multiplying the multiplication value of a law, it inputs into the above-mentioned adding means, Before setting after The 2 step The output signal of an account memory measure is inputted into the multiplication means and the above-mentioned delay means of above-mentioned The 1, and it is the above-mentioned Addition. Calculation means is an output signal of the multiplication means of above-mentioned The 1, It is two or more step deed about processing in which the output signal of the above-mentioned delay means and the reversal output signal from the 2nd above-mentioned multiplication means are added, The above-mentioned adding means for every step memorized by the above-mentioned memory measure in the last step After total-adding an output signal in the above-mentioned total adding means, It is the above-mentioned total addition hand at the above-mentioned quantization means. While quantizing the output signal of the stage and outputting the output signal of the above-mentioned quantization means outside It has composition returned to the 2nd above-mentioned multiplication means in The 1 above-mentioned step.

According to such composition, the conventional multiplier with a large circuit scale like before is used. To, using small Shifter and adding machine of a circuit scale which were shared -- multiplication processing -- Here -- it obtains and things become possible -- above, while leading to reduction of large power consumption It becomes possible to carry the signal processor which performs repetition processing in L S I.

it sets to the digital-signal-processing device concerning the present invention -- the multiplication means of above-mentioned The 1 -- ON or not [ carrying out a power signal ], whether the above-mentioned delay means outputs a signal and multiplication hand of above-mentioned The 2 It comes out to control whether the stage outputs a signal by a respectively separate control signal. It is desirable to have composition to cut. According to such composition, it is One to the means which is not required. Since it can avoid making it work if it is, consumption of electric power is reduced sharply. Things are made.

it sets to the digital-signal-processing device of the above-mentioned composition -- the above-mentioned adding means -- subtraction processing It is an addition-and-subtraction means which can be performed. The multiplication means of above-mentioned The 1 is Multiply about a multiplication value predetermined to a signal. About Processing, the multiplication means of above-mentioned The 1 is Power of the reciprocal of a predetermined multiple or a predetermined multiple to a signal. A Calculation value is multiplied and it outputs to the above-mentioned addition-and-subtraction means, the above-mentioned addition-and-subtraction means -- multiplication means of above-mentioned The 1 an output and the output of the above-mentioned delay means are added or subtracted -- the above-mentioned delay means -- the above-mentioned degree Repeat operation processing in which the output of Calculation means is inputted and perform it, It is a pair to a signal. It replaces by processing of The 1 which carries out and multiplies a predetermined multiplication coefficient, Multiplication means of above-mentioned The 2 About the processing which multiplies a predetermined multiplication value to a signal, the multiplication means of above-mentioned The 2 is a place to a signal. The multiplication value of the reciprocal of a constant multiple or a predetermined multiple is multiplied, and it outputs to the above-mentioned addition-and-subtraction means, above-mentioned Addition a subtraction means -- the output of the multiplication means of above-mentioned The 2, and the output of the above-mentioned delay means -- addition or decrease Calculation is carried out -- the above-mentioned delay means winds operation processing in which the output of the above-mentioned addition-and-subtraction means is inputted -- Return Carry out by carrying out, It may be made to perform at least one of the replacing by processing of The 2 which multiplies a predetermined multiplication coefficient to a signal.

The above-mentioned addition-and-subtraction means are an output of the multiplication means of above-mentioned The 1 or The 2, and an output of the above-mentioned delay means. Since it adds or subtracts, it is the output and the above-mentioned delay hand of a multiplication means of above-mentioned The 1 or The 2. Compared with the case of only adding with the output of the stage, the number of times of a repetition of processing can be reduced. There is a To case. for example, a predetermined multiplication coefficient -- 0.9 3 7 it is 5 -- predetermined multiple or place the multiplication value of the reciprocal of a constant multiple -- 1Z1 the case where it is 6 -- addition -- 1 5 times of repetition places Although Reason is required the multiplication value of the reciprocal of the predetermined multiple in first-time processing or a predetermined multiple is set to 1 -- the multiplication value of the reciprocal of the predetermined multiple in the 2nd processing, or a predetermined multiple -- 1 1 If it subtracts by being referred to as 6, it will end by two repetition processings. Thereby, the accuracy of a multiplication coefficient Even if it goes up and the digit number of processed data increases, the increase in operation The mouth A frequency is lessened. Since things are made, even if it raises the accuracy of a multiplication coefficient value, power consumption is stopped low. It can do.

It is a multiplication value of the reciprocal of the above-mentioned predetermined multiple or a predetermined multiple for every repetition of the above-mentioned operation processing. It is desirable to use a different value.

Thereby, the number of times of repetition processing can be reduced. for example, predetermined multiplication a coefficient -- 0.93 7 it is 5 -- the multiplication value of the reciprocal of a predetermined multiple or a predetermined multiple -- 1Z1 the case where it is 6 -- addition -- 1 Although five repetition processings are required A predetermined multiple or place They are 1Z2, 1/4, 1/8, and 1 A 1 about the multiplication value of the reciprocal of a constant multiple. Every 6 and repetition processing If it changes, it will be a predetermined multiplication coefficient by repetition processing of only four addition 0.93 7 It can be made 5. A predetermined multiplication coefficient is 0.906. When it is 25, the multiplication value of the reciprocal of the predetermined multiple in first-time processing or a predetermined multiple is set to 1, The 2nd time or subsequent ones The multiplication value of the reciprocal of the predetermined multiple in processing or a predetermined multiple is made into 1/32, and it is a line about subtraction. In use, Predetermined multiplication coefficient 0.9062 Although four repetition processings are required in order to realize multiplication processing of 5 (= 1 - 1/3 2- 1/3 2- 1/3 2), a predetermined multiple -- or -- the multiplication value of the reciprocal of a predetermined multiple -- 1 and 1 1 6 and 1 3 Change to 2 for every repetition processing. Multiplication processing of Leave and predetermined multiplication coefficient 0.90625 (= 1 - 1/1 6 - 1/3 2) In order to realize, it ends by three repetition processings.

the above-mentioned predetermined multiplication coefficient -- 2 Bit of "0" and "1" the case where it expresses by A -- " -- This from which the above-mentioned addition-and-subtraction means subtracts the time of the beam which is 1" continuing over triple or more figures It is desirable.

Thereby, the above-mentioned addition-and-subtraction means adds because the above-mentioned addition-and-subtraction means performs subtraction processing. Only when the number of times of repetition processing can be reduced rather than carrying out, it is the above-mentioned addition and subtraction. A means can perform subtraction processing.

In the sound signal reproducer applied to the present invention to achieve the above objects an audio signal inputs the P CM signal by which pulse code abnormal conditions were carried out -- the above-mentioned P CM signal -- De Delta sigma modulation means which carries out Ruta- sigma abnormal conditions, the above-mentioned delta sigma modulation means , -- PWM hand which carries out Pulse Density Modulation of the output To be sick signal, and generates a 1-bit digital signal Have a stage and a demodulation means which restores to the above-mentioned 1-bit digital signal to an analog signal. It is considered as Configuration.

According to such composition, he is announcer after carrying out digital amplification of the 1-bit digital signal. Since it can get over to a log signal, it is sound from the conventional multibit P CM method. A source is faithfully reproducible.

It is a P DM modulation method (2. 8 MH z or 5. 6 MH z) about a 1-bit signal. Low PWM modulation method of a sampling frequency (for example, 3 52. 8 kH z) Since it generates, the switching loss of switching amplifier is suppressed -- reduction of power consumption it can do -- unnecessary radiation can be suppressed. thereby, required for a P D M modulation method measures against a noise' shield, such as a double shield by an indispensable steel plate And copper plate, -- needlessness composition of goods can be performed in a Ri plastic cabinet etc. -- miniaturization , weight saving , and low Kos A-ization can be attained.

What is done for the Pulse Density Modulation of the signal which carried out the delta sigma abnormal conditions of the P C M signal Since the intermediary 1 bit digital signal is generated, As compared with the conventional 1-bit method which generates a 1-bit digital signal, the sampling frequency of and a delta sigma modulation circuit can be made extremely small from a P C M signal only with a delta sigma modulation circuit. To. That is, that each work between each clock carries out with ease very much It can do. therefore -- it comes out to further divide the work performed with one clock, and to perform it It cuts. That is, if it works by decomposing into n steps, they will be n times as many Crout. It may carry out by The. And as mentioned above, it is Samp of a delta sigma modulation circuit. Since ring frequency is made extremely small, even if n is 6 and 7, it is a top in any way. The effect of an account is not lost. The n above-mentioned steps are on basic targets, such as integration work. Since it is only the same thing and a thing from which the constant value dealt with for every But only step differs, it is a constant value. If it enables it to do the work to change and basic work in routine, predetermined delta - sigma abnormal conditions can be carried out. hard [ in soft ] by this ---like -- Composition is simplified very much. that is, -- generating of a noise can be barred further -- un--- It becomes a measure against radiation required.

it sets in the above-mentioned composition -- the above-mentioned delta sigma modulation means -- the above-mentioned digital signal place It is good to use Device. thereby, reduction of large power consumption can be aimed at it sets in the above-mentioned composition again -- the above-mentioned delta sigma modulation means -- the left Chia of an audio signal It may be made to process the signal for Nellnell, the signal for right channels, and by turns. this the above-mentioned multiplication means, the above-mentioned adding means, and the above-mentioned quantization means -- the left channel and the right Chi since it can be used in common by Yannell, it becomes the further circuit reduction -- reduction of power consumption It is connected.

It is portable type Audio signal reproduction device about the sound signal reproducer of the composition of one of the above. It may be made Place. thereby, low-power-consumption-izing, a small weight saving, and a cost cut are required it sets to an indispensable portable type sound signal reproducer -- low-power-consumption-izing, a small weight saving, and cost reduction can be attained. Brief explanation of the drawings

Drawing 1 is a figure showing the example of 1 composition of MD playback equipment concerning the present invention,

Drawing 2 -- a figure -- example of 1 composition of the 7th Delta sigma modulation circuit with which MD playback equipment of 1 is provided Shown figure,

Drawing 3 -- a figure -- the figure and Drawing 4 showing the example of 1 composition of the PWM circuit with which MD playback equipment of 1 is provided -- a figure -- the The mouth A signal of 96 Advance counter in the PWM circuit of 3, and 96 Strength Figure showing the count value of Dunta, and a relation with a PWM signal,

1 of the PDM signal generation circuit with which the 1-bit method sound signal reproducer of the former [ Drawing / 5 ] is provided Figure showing the example of composition,

Drawing 6 -- a figure -- other examples of composition of the 7th Delta sigma modulation circuit with which MD playback equipment of 1 is provided It is a shown figure.

The best form for inventing

One embodiment of the present invention is described with reference to drawings below. Sound concerning the present invention It explains by mentioning MD playback equipment as an example as a voice signal regeneration device here. Drawing 1 is the Plock figure showing the example of 1 composition of MD playback equipment concerning the present invention.

Optical pickup device 2 takes a signal from MD 1, and sends it out to extension circuit 3. Signal into which extension circuit 3 was inputted (compression music data) It elongates. This develops. It is set to P CM signal S 1 of the signal outputted from circuit 3, and sampling frequency 44. 1 kH z. -

P CM signal S 1 outputted from oversampling circuit 4 and extension circuit 3 (multibit) It changes into 24 bit P CM signal S 2 of sampling frequency 8 f s. It carries out. However, it is f s = 44. 1 kH z.

being outputted from 7th delta 1 sigma modulation circuit 5 and oversampling circuit 4 the Delta sigma abnormal conditions of To PCM signal S 2 are carried out -- 6-bit PCM Trust for left channels item S -- 3 and 6 bit P CM signal S 4 for right channels are generated. 6 Bit The sampling frequency of A P CM signal S 3 and S 4 is 8 f s.

the left channel outputted from PWM circuit 6 and 7th Delta sigma modulation circuit 5 the for 6-bit P CM signal S -- carrying out Pulse Density Modulation of 3, and generating 1 bit PWM Trust S 5 for left channels Pulse Density Modulation of the 6 bit P CM signal S 4 for right channels outputted from 7th delta 1 sigma modulation circuit 5 is carried out, and 1 bit PWM signal S 6 for right channels are generated.

1 bit PWM signal S 5 for left channels outputted from PWM circuit 6 are Switzerland. After being changed into the analog signal by Ting amplifier 7 and being amplified with it, low Passy a high-frequency component is removed by Ruta (LP F) 8 -- speaker 9 for left channels It becomes an intermediary sound. 1 bit P WM signal S 6 for right channels outputted from PWM circuit 6 -- switching amplifier 1 being changed into an analog signal by 0 -- amplification -- After Was done, low pass filter (LPF) 1 a high-frequency component is removed by 1 -- the right Chi Speaker 1 for Yannell It becomes a sound by 2.

At this embodiment, they are extension circuit 3 and exaggerated Sampler. 4 or 7th Tongue circuit Dell Tha-- sigma modulation circuit 5 and PWM circuit 6 are carried in one system L S I. Although it is, it may be provided separately.

Then, it explains in more detail about 7th Delta sigma modulation circuit 5 and PWM circuit 6 which are the characterizing portions of the present invention. first, 7th delta 1 sigma modulation circuit 5 -- just -- Explanation is carried out. the example of 1 composition of 7th Delta sigma modulation circuit 5 -- a figure -- it is shown in 2.

the 7th delta 1 sigma modulation circuit of Drawing 2 -- input terminal I N and output terminal OUT, Shifter 1 -- 14*1 6 and adding machine 1 7 and quantization machine 1 8, Register d s 1 -- r e g~d s 71re g, o u t1r e g, ACC and r e g, and selector 1 It is a digital-signal-processing device constituted by 9~23.

input terminal I N -- selector 2 it is connected to "0 1" of 1 input terminal -- selector 2 1 An output terminal is connected to the input side of Shifter 14. adding machine 1 7 and Shifter 14 And 1 the reversed input of the output of 5 is carried out -- Shifter 1 The reversal input of the output of 6 is carried out. Adding machine 1 The output side of 7 is connected to the input side of register ACC. And appearance of register ACC The power side is selector 2. "1 0" of 1 An input terminal and register d s l r e g*d s 7 -- r e g and o u t -- It is connected to the input side of each r e g.

Register d s 1 -- The output side of r e g is selector 1. 9 And 2 "0 0 0" of 0 Input edge It is connected to a child, Register d s 2 -- The output side of r e g is selector 1. 9 And 2 "0 0 1" of 0 It is connected to an input terminal, Register d s 3 -- The output side of r e g is selector 1. 9 And 2 "0 1 0" of 0 It is connected to an input terminal, Register d s 4 -- The output side of r e g is S. Recta 1 9 And 2 "0 1 1" of 0 It is connected to an input terminal, Register d s 5 -- The output side of r e g is selector 1. 9 And 2 It is connected to "1 0 0" of 0 input terminal, Regis Tha d s 6 -- the output side of r e g -- selector 1 9 And 2 the "1 0 1" input terminal of 0 -- Connection is carried out -- the output side of register d s 7 1 The e g -- selector 1 9 and 2 It is connected to the "1 1 0" input terminal of 0. Register o u t -- the output side of r e g -- quantization machine 1 it is connected to the input side of 8 -- quantization machine 1 the output side of 8 -- selector 2 It is connected to the "11 1" input terminal [ of 0 ], and input side of register r e g. And the output side of register r e is connected to output terminal OUT.

selector 1 the output terminal of 9 -- selector 2 "1" of 2 input terminal -- connection -- Re and selector 2 the output terminal of 2 -- Shifter 1 It is connected to the input side of 5. selector 2 the output terminal of 0 -- selector 2 it is connected to "1" of 3 input terminal -- selector 2 Appearance of 3 a power terminal -- Shifter 1 -- 1 It is connected to the input side of 6.

Shifter 1 4*1 6 is by Shifter control signal c t i l* c t l 3, respectively. It is controlled. Selector 1 9 is controlled by selection signal r e g s e 1_1, Sele Cuthah 2 0 -- selection signal r e g s e -- being controlled by 1--2 selector 2 1 -- Selection being controlled by item a s e 1 -- selector 2 2 -- selection signal b s e 1 -- control -- Re and selector 2 3 is controlled by selection signal c s e1. selector 1 9*2 3 chooses the input terminal which is in agreement with the contents of each selection signal -- the selected input terminal -- ON The signal by which power was carried out is outputted to an output terminal. register AC C -- Enable signal e n a b l e -- it is controlled by a c c -- Register d s 1 -- r e g* (!) s 7 -- r e g -- respectively -- Enable signal e n a b 1 e_l~e n a b 1 e -- 7 -- control it is carried out -- Register o u t -- r e g -- Ine Nole signal e n a b 1 e -- o -- control It is carried out. And selector 2 "0 0" of 1 input terminal, and selector 2 "0" of 2 input A terminal and selector 2 The data in which all the bit sequence is 0 at "0" input terminals of 3 is inputted.

Such composition, Multiplication processing It is selector 2 when carrying out. Control signal a of 1 s e 1 and selector 2 Control signal b s e 1 of 2, and selector 2 Control signal .c s e 1 of 3 It changes to the signal for multiplication processing, and is Shifter 1. 4 and 1 5 and 1 6 and adding machine 1 7 A multiplication result can be obtained with combination.

For example, 3 inputted from input terminal I N in the P DM signal generation circuit of Drawing 5 5 Two of 8. 8 k H z It is multiplier 1 about a 4-bit P CM signal. 0 1 should carry out multiplication processing. Connection obtained the same result as Result -- a figure -- in order to obtain in the 7th Delta sigma conversion circuit of 2 Multiplication factor m l = in the case of 0.5, set in the 7th delta sigma conversion circuit of Drawing 2. Selector 2 setting selection signal a s e of 1 1 to "0 1" -- Shifter 1 Selector 2 taken into 4 output data d a t a a of 1 -- Shifter 1 -- 1 Make it shift to the 1-bit right by 4. multiplication staff several meters -- l = 0.2 the case of 5 -- a figure -- set in the 7th Delta sigma conversion circuit of 2 selector 2 making selection signal a s e of 1 1 into "0 1" -- Shifter 1 -- 1 Selector 2 taken into 4 output data d a t a a of 1 -- Shifter 1 -- 1 4 -- the 2-bit right -- CIF Carry out A. By making selection signal b s e 1 And c s e l into "0", it is Shifter 1. The output value of 4 is stored in register AC C.

the time of raising the accuracy of multiplication coefficient m 1, in order to improve sound quality -- a shift amount -- different -- A Shifter value can be added if needed. For example, it is multiplication coefficient m 1 0.9 3 7 The case where 5 is used is explained below. in this case, 7th Delta sigma modulation circuit 5 -- a figure -- not circuit composition but the figure which are shown in 2 -- it has circuit composition shown in 6. in addition -- in Drawing 6 -- a figure -- numerals are identically given to the same portion as 2, and detailed explanation is omitted. The 7th Delta sigma modulation circuit shown in Drawing 6, and 7th delta sigma modulation circuit shown in figure 2 Selector 2 It is selector 2 about 2. It is the composition replaced by 2'. And the output side of register AC C is selector 2. "1 0" of 2' It is connected to an input terminal, Selector 1 The output terminal of 9 is selector 2. It is connected to "0 0" input terminal of 2', and is selector 2. The output terminal of 2, is Shifter 1. It is connected to the input side of 5. Selector 2 "0 1" of 2' input The data in which all the bit sequence is 0 at a terminal is inputted. selector 2 2' is controlled by selection signal b s e 1 -- the input terminal which is in agreement with the contents of the selection signal is chosen -- the signal inputted into the selected input terminal is outputted to an output terminal. Adding machine 1 7, external signal (not shown) Shifter 1 Into which does not carry out the reversed input of the output of 4 A reversal input can be carried out.

First, in the 7th Delta sigma conversion circuit of Drawing 6, it is selector 2. Selection of the output of 1 Selection signal as e l is made into "0 1", Shifter 1 Selector 2 taken into 4 Appearance of 1 power data d at a a -- Shifter 1 -- 1 Make it shift to the 1-bit right by 4. It is Shifter 1 by setting selection signal b s e 1 to "0 1", and setting selection signal c s e 1 to "0". The output value of 4 is stored in register AC C.

and selector 2 making selection signal a s e of 1 1 into "0 1" -- Shifter 1 -- 1 Take to 4. Crowded selector 2 output data d a t a a of 1 -- Shifter 1 -- 1 4 -- the 2-bit right -- Si Carry out Bud. selection signal b s e 1 is made into "1 0" -- selection signal c s e 1 -- " -- 0" and To do -- Shifter 1 the output of 4, and Shifter 1 -- 1 an aggregate value with the output of 5 -- Regis It stores in Tha AC C. At this time, multiplication coefficient m 1 is 0.7. It is equivalent to 5 (= 1 / 2+1 / 4).

selector 2 making selection signal a s e l of 1 into "0 1" -- Shifter 1 Take to 4. Crowded selector 2 output data d a t a a of 1 -- Shifter 1 -- 1 4 -- the 3-bit right -- Si Carry out Bud. selection signal b s e 1 is made into "1 0" -- selection signal c s e 1 -- " -- 0 "and To do -- Shifter 1 the output of 4, and Shifter 1 -- 1 an aggregate value with the output of 5 -- Regis It stores in Tha AC C. At this time, multiplication coefficient m l is 0.8. 7 It is equivalent to 5 (= 1 / 2+1 / 4+1 / 8).

selector 2 setting selection signal a s e l of 1 to "0 1" -- Shifter 1 -- 1 Take to 4. Crowded selector 2 output data d a t a a of 1 -- Shifter 1 -- 1 4 -- the 4-bit right -- Si Carry out Bud. 0 selection signal b s e 1 is made into "1 0" -- selection signal c s e 1 -- " -- consider it as " things -- Shifter 1 the output of 4, and Shifter 1 -- 1 An aggregate value with the output of 5 is stored in register AC C. At this time, multiplication coefficient m 1 is 0.9. 3 7 It is equivalent to 5 (= 1 / 2+1 / 4+1 / 8+1 / 1 6).

above -- Shifter 1 -- 1 shifting a signal two or more times by 4 -- Power The accuracy of Coefficient of calculation can be raised. In the above-mentioned operation (henceforth the 1st operation) It is multiplication coefficient m l 0.9 3 7 Although addition is required 4 times in order to use 5, It is Show to Drawing 6. 7th To delta 1 sigma modulation circuit 5 can raise the accuracy of a multiplication coefficient by the following operations (henceforth the 2nd operation).

that it is the same as that of the above, and multiplication coefficient m l -- 0.9 3 7 the case where 5 is used -- a figure -- 7th Del Tarsi of 6 In a pellet conversion circuit first -- selector 2 making selection signal a s e of 1 1 into "0 1" -- Si lid 1 -- 1 Selector 2 taken into 4 output data d a t a a of 1 -- Shifter 1 -- 1 Without it makes it shift by 4 it is considered as selection signal b s e 1"0 1" -- setting selection signal c s e 1 to "0" -- Shifter 1 The output value of 4 is stored in register AC C. and adding machine 1 7 -- Shifter 1 -- 1 Input [ reversed/ un-/-] not but input [ reversal ] the output of 4. selector 2 making selection signal a s e of 1 1 into "0 1" -- Shifter 1 S taken into 4 Recta 2 output data d a t a a of 1 -- Shifter 1 -- 1 Make it shift to the 4-bit right by 4. it is considered as selection signal b s e 1" 1 0" -- selection signal c s e 1 -- " -- considering it as 0" The and Shifter 1 What carried out the reversal output in order to subtract the output of 4, and Shifter 1 An aggregate value with the output of 5 is stored in register AC C. At this time, multiplication coefficient m l is already 0.9. 3 7 It is equivalent to 5 (= 1 - 1/1 6). By this operation, addition and subtraction are 10 at 2 times. It is a part and processings are reduced compared with the operation only by addition. Thereby, he is the multiplication staff. Even if the accuracy of a number goes up and the digit number of processed data increases, it is the increase in an operation clock frequency. Since it can lessen, even if it raises the accuracy of a multiplication coefficient value, it is low about power consumption. It can stop.

It is a line about which of operation of The 1 and operation of The 2 of 7th delta 1 sigma modulation circuit 5 of Drawing 6. If Emergence is determined as operation of The 2 is adopted, when the fixed coefficient which carried out binary number expression is developed to addition and the beam where "1" stands continues over triple or more figures It is effective. It is the above-mentioned multiplication coefficient m l 0.9 3 7 In the example set to 5 If a binary representation is carried out, m 1 = 0.1 1 1 1 = (1/2) With the method [ what / is ++(1/4) (1/8)+ (1 / 1 6) ] using subtraction, it is m 1 = 0. 1. 1 1 1 = (1) It processed with 1 (1 / 1 6). It becomes.

and the value which multiplied the input signal stored in register AC C by multiplication coefficient ml -- a figure -- each following delay device 1 of 5 2 1*1 2 Register d s l equivalent to 8 -- r e g*d s 7 -- it is stored in r e g And o u t__r eg. Register d s l -- r e g*d s 7 -- r e g and o u t -- r e g is 24-bit width, respectively.

Selector 2 When it is selection signal a s e 1 power S" 1 0" of 1, it is an output of register A C C. (register d s l -- the same as that of the register value of r e g) Selector 2 It becomes an output of 1, The selector 2 The output of 1 is Shifter 1. It is CIF at the value which hits multiplication coefficient m 2 by 4. A multiplication is carried out and it is adding machine 1. It becomes one reversed input of 7. moreover Selector 2 Two selections Signal b s e 1 power S" 1" and selector 1 Nine selection signals r e g s e l -- When 1 is "0 0 1", it is register d s 2. -- The last register value of r e g is selector 2. Two outputs It becomes, The selector 2 The output of 2 is Shifter 1. It is Addition, without shift multiplication being carried out by 5. Calculator 1 It becomes a reversed input of another side of 7. Selector 2 Selection signal c s e 1 of 3 is "1" and selector 2. Selection signal r e g s e 1 of 0 -- It is Les when it is 2 power S" 0 1 0". The last register value of District d s 3_r e g is selector 2. It becomes an output of 3, The S Recta 2 The output of 3 is Shifter 1. It is shift multiplication at the value which hits multiplication coefficient m8 by 6. It is carried out and is adding machine 1. It becomes a reversal input of 7. in this case, adding machine 1 7 -- a figure -- adding machine 1 formed in the P DM signal generation circuit of 5 1 Processing equivalent to 3 is carried out.

selector 1 9*2 selection signal Api Shifter 1 of 3 -- 1 4*1 This which changes the control signal of 6 Adding machine 1 7 -- a figure -- adding machine 1 formed in the P DM signal generation circuit of 5 1 4*1 1 8 -- it can be alike, respectively and can perform corresponding processing.

thus -- each -- 1 time of a clock can perform processing which obtains the following data n-th noise shaver (Delta sigma modulation circuit) Then. -- clock of the n minimum The data of all the degrees can be obtained.

Drawing 2 or figure The 7th delta 1 sigma modulation circuit of 6 is a PDM signal generation circuit of Drawing 5. It is multiplier 1 like. 0 1*1 1 1 is not provided, and since it may not be, circuit scales are reduced. Things are made. Since the degree of Delta sigma abnormal conditions can be raised easily, it is Noi. The A characteristic can be made very good. Sampling cycle of an input signal A number can also be suppressed very low.

moreover -- computing the frequency of a main clock from the total number of times of processing -- a figure -- 2 -- or -- ROM (not shown) provided in the 7th Delta sigma modulation circuit of Drawing 6 Required Adre It is good to create A counter.

8 It is Must about 24 steps the object for left channels, and for right channels to the period of f s, respectively. When considering it as an important point, the clock of 8 f s X (24 step X 2 c h) = 3 S 4 f s (1 6. 8 6 8 8 MH z) is needed. this clock or this clock , -- a phase -- the shifted signal serves as a clock of each register. Drawing 2 or figure 7th 6 Dell It is 24 Advance counter to a Tha 1 sigma modulation circuit. (not shown) It provides, The 24 Advance counter It becomes Address of ROM which the counter value mentioned above, ROM -- rice 1 of a register pull ft e n a D 1 e- 1~e n a b -- one e1 -- 7, e n a b 1 e- o, and And e n a b 1 -- e1q, Selection signal a s e l of a selector, b s e. l, c s e l, r e g s e 1 -- 1, And r e g s e 1 -- 2, control signal c t 1 which controls the shift amount of Shifter 1* c t 1 3 is stored -- the contents of those signals outputted for every The mouth A It changes. and Shifter 1 4*1 6 and adding machine 1 7 and quantization machine 1 8 -- the left -- business -- Channel -- the right -- business -- a channel -- alternation , such as a channel, for example, the signal of 8 f s -- " -- the time of being 1 "-- the left -- game business -- flannel and the time of "0" -- the right -- business -- It uses. Thereby, it is Circuit cutting sharply. A decrease is realizable. Register [ What is used for Yannell is provided separately respectively. ] d s l -- r e g*d s 7 -- r e g, o u t -- What uses r e g, And r e g, and output terminal O U T for the channel for the lefts, and Chi for the rights

Drawing 2 or figure In the 7th Delta sigma modulation circuit of 6, it is a register value of register d s l_r e g, Register d s 2 -- The register value of r e g, and register d s 3 -- Register value of r e g, Register d s 4 -- The register value of r e g, and register d s 5 -- Les of r e g District value, The register value of register d s 6_r e g, and register d s 7 -- Register of r e g Star value, Register o ut -- Register value of r e g (L c h) R c h -- respectively -- 24 Bi the data stored in Tut width -- respectively -- a figure -- d s 1 in the PDM signal generation circuit of 5, d s 2, and d s -- it is equivalent to 3, d s 4, d s 5, ds 6, d s 7, and o u t. Register d s l -- r e g~d s 7 -- r e g, o u t -- In r e g, it is rice 1, respectively. It is Summer to the composition which a bull exists, becomes effective only once in the period of 8 i s, and stores data. ing sake, 3 8 The register is working to every 4 f s (= 1 6. 8 6 8 8MH z). Since it is not To mention, power consumption is not influenced at all.

it mentioned above -- as -- multiplication processing -- Shifter 1 -- 1 4*1 6 And adding machine 1 Combination of 7 It is realizable. And the multiplication coefficient embraces the characteristic finally made profitably like, and is Establishment. It carries out constant. 24-bit data finally stored in register o u t_r e g, Quantization machine 1 It is 4 at 8. which is divided into seven and replaced by 6-bit data (in the case of this embodiment "0 0 0 0 0 0" * total 4 7 value of "1 0 1 11 0"). namely, input terminal I N the delta sigma abnormal conditions of the inputted P CM signal are carried out -- low Bit It is conversion to the P CM signal of A. It means carrying out. The P CM signal of a low bit is outputted from output terminal OUT via register r e g.

Next, PWM circuit 6 is explained. the example of 1 composition of PWM circuit 6 -- a figure -- shown in 3. Figure It is constituted by PWM circuit 6, input terminal 24 And 27, comparison machine 25 And 28, output terminals 26 and 29, and 96 Advance counter 30 of 3.

input terminal 24 -- a figure -- 2 or a figure -- it is outputted from the 7th Delta sigma conversion circuit of 6 -- the left -- 6 bit P CM signal S 3 for channels are inputted. Comparison machine 25 is to input terminal 24. Inputted power U of 6 bit P CM signal S 3 for left channels, and 96 Advance ability 30 A The value is compared, PWM signal S 5 for left channels are generated, and it is Sending to output terminal 26. It comes out and carries out. on the other hand -- input terminal 27 -- a figure -- from 2 or the 7th Delta sigma conversion circuit of Drawing 6 6 bit P CM signal S 4 for right channels outputted are inputted. Comparison machine 28 is ON. 6 bit PCM signal S 4 for right channels inputted into power terminal 27, and 96 Advance Kaun The counter value of Tha 30 is compared, PWM signal S 6 for right channels are generated, and it sends out to output terminal 29. 96 Advance counter 30 is power U about 96 values at the period of 8 f s. Tent is carried out. .

Comparison machine 2 5 and 1 corresponding to 6 bit PCM signal S 3 for left channels When the number of 0 Advance and the count value of 96 Advance counter 30 become equivalent, it is a toggle to a "H i g h" level. It carries out, 1 corresponding to 6 bit P CM signal S 3 for left channels The number of 0 Advance, and 96 Progress The left Chia which will carry out a toggle to a "L ow" level if the sum with the counter value of Tha 30 is set to 95 PWM signal S 5 for Nellnell are generated. It corresponds to comparison machine 28 and 6 bit P CM signal S 4 for right channels. A decimal number and the count value of 96 Advance counter 30 If it becomes equivalent, a toggle will be carried out to the "H i g h" level, 6-bit P CM Trust for right channels It corresponds to item S 4. if the sum of a decimal number and the counter value of 96 Advance counter 30 is set to 95 -- the "L o w" level -- toggle 10 -- PWM signal S 6 for Right channels are generated. Comparison machines 25 and 28 operate in this way, It is for certainly carrying out a toggle twice, without fixing PWM signal S 6 for the PWM signal S 5 Right hand channels for left channels to a "H i g h" level or the "L o w" level in the period of 8 f s, and is Ah. To. clock signal CK of 96 Advance counter 30 in this case, the count value of 96 Advance counter 30, and a relation with a PWM signal -- a figure -- it is shown in 4.

the left -- PWM signal S 6 for the PWM signal S 5 Right hand channels for channels come out with 'amplitude it is a pulse signal with the constant present frequency -- change of the time width of a pulse -- signal level It is expressing. Therefore, about the amplitude direction, although PWM signal S 6 for the PWM signal S 5 Right hand channels for left channels are 1 bit, they are related in the direction of a time-axis, and they are many values. It is. As shown in Drawing 4, it is the time of 1 cycle pattern 8 f s (= 3 52. 8 kH z). The data conversion of 47 receiving values is 768 f s symmetrically. It hits that to which the width of the (= 3 3. 8 688MH z) width [ every ] H i g h level section was changed.

At this embodiment, it is a 7th Delta sigma abnormal-conditions time to a Delta sigma modulation circuit. Although the way was used, the Delta sigma modulation circuit of other degrees may be used. Industrial applicability

The digital-signal-processing device and speech-signal-processing playback equipment of the present invention, and audio equipment It can begin and can use for various devices which process a digital signal.