Digital signal processing device and audio signal reproduction device

The present invention relates to an audio signal reproduction device. In particular, the present invention relates to an audio signal reproduction device having a delta-sigma modulation circuit. The present invention also relates to a digital signal processing device.

Examples of the audio signal reproduction device for reproducing the audio signal stored in a recording medium such as a CD or MD include a multi-bit PCM (Pulse Code Modulation) type audio signal reproduction device and a 1-bit type audio signal reproduction device. The 1-bit method is a method that can reproduce the sound source more faithfully than the multi-bit PCM method. A conventional 1-bit audio signal reproduction device encodes an audio signal, which is a multi-bit digital signal, into a 1-bit digital signal, digitally amplifies the 1-bit digital signal, and digitally amplifies the digitally amplified 1-bit digital signal with a low-pass filter. Is converted into a reproduced signal which is an analog signal (see, for example, Japanese Patent Application Laid-Open No. 10-322215). Here, FIG. 5 shows an example of a configuration of a PDM (Pulse Density Modulation) signal generation circuit included in a conventional 1-bit audio signal reproduction device. The PDM signal generation circuit of FIG. 5 is composed of an input terminal IN, an output terminal OUT, multipliers 101 to 111, adders 112 to 119, a quantizer 120, and delayers 121 to 128. The multiplication coefficients of the multipliers 101, 102, ..., 111 are m1, m2, ..., and m11, respectively. The PDM signal generation circuit of FIG. 5 performs 7th-order delta-sigma modulation on an audio signal which is a multi-bit digital signal to generate a PDM signal which is a 1-bit digital signal. A PDM signal is a pulse having the same amplitude and time width, and expresses the signal level by changing the pulse density, that is, the frequency of appearance. Further, the PDM signal generation circuit of FIG. 5 processes data at a very fast sampling frequency of 2.8 MHz or 5.6 MHz from the input terminal IN to the output terminal OUT in order to faithfully reproduce the sound source. When a 1-bit digital signal is generated by delta-sigma modulation, the quantization error component has a distribution shifted to a high frequency range. This is known as "noise shaping". Therefore, the PDM signal generation circuit of FIG. 5 is used to reduce the quantization noise of the target frequency band (for example, the audible band) and acts as an IIR (Infinite-duration Impulse Response) filter. As a result, the S / N within the target frequency band can be secured and the bandwidth can be widened. However, in the PDM signal generation circuit shown in Fig. 5, the sampling frequency is very high (for example, 2.8MHz, 5.6MHz, etc.) and the influence of unnecessary radiation is large. Is indispensable. For this reason, the shield steel plate or the like occupies a considerable space in the audio signal reproduction device, and the weight of the audio signal reproduction device also increases. Therefore, it is not possible to reduce the size and weight of the audio signal reproduction device. In addition, the PDM signal generation circuit in Fig. 5 uses many multipliers and adders, so the circuit scale is large. And because the circuit scale is large, the power consumption is also large. Furthermore, since the PDM signal generation circuit shown in FIG. 5 is generally an analog circuit and supports processing of only one channel, the PDM signal generation circuit shown in FIG. 5 should be used when used in stereo (Lch, Rch). I had to set up two. Since the PDM signal generation circuit has such a complicated circuit configuration and a huge circuit scale, it has been difficult to mount it on a conventional LSI. Therefore, it has not been possible to reduce the size and weight of the audio signal reproduction device. Since the PDM signal generation circuit of FIG. 5 has the above problems, it is particularly unsuitable for a portable audio signal reproduction device in which low power consumption, small size and light weight, and cost reduction are indispensable. Was not adopted in.

In view of the above problems, an object of the present invention is to provide a 1-bit audio signal reproduction device that can be miniaturized and lightweight. Another object of the present invention is to provide a digital signal processing device capable of reducing the circuit scale in view of the above problems. In order to achieve the above object, in the digital signal processing apparatus according to the present invention, the addition means, the first multiplication means for multiplying the signal by a predetermined multiplication value, and the delay means for delaying the output signal of the addition means. And a second multiplication means for multiplying the output signal of the delay means by a predetermined multiplication value, the addition means includes the output signal of the first multiplication means, the output signal of the delay means, and the said. It adds the inverted output signal of the second multiplication means, and processes the signal by repeating the process of inputting the output of the addition means to the first multiplication means and the delay means a plurality of times. It is configured. Further, it is provided with a storage means for storing the output signal of the addition means, a total addition means, and a quantization means, and it is one step until the addition process is performed by the addition means. The input signal is multiplied by a predetermined multiplication value by the first multiplication means and then input to the addition means, and the output signal of the storage means is sent to the first multiplication means and the delay means in the second and subsequent steps. The addition means performs a plurality of steps of adding the output signal of the first multiplication means, the output signal of the delay means, and the inverted output signal from the second multiplication means in a plurality of steps, and the final step. After the output signal of the addition means for each step stored in the storage means is totally added by the total addition means, the output signal of the total addition means is quantized by the quantization means, and the quantization is performed. The output signal of the means is output to the outside and returned to the second multiplication means in the first step. With such a configuration, it becomes possible to perform multiplication processing using a shared shifter and adder with a small circuit scale instead of using a conventional multiplier with a large circuit scale as in the past, which consumes a large amount of power. In addition to reducing power consumption, it is possible to mount a signal processing device that performs the above-mentioned repetitive processing on the LSI. Further, in the digital signal processing device according to the present invention, whether or not the first multiplying means outputs an input signal, whether or not the delay means outputs a signal, and whether or not the second multiplying means outputs a signal. It is desirable to have a configuration in which whether or not each of them can be controlled by a separate control signal. With such a configuration, it is possible to prevent unnecessary means from operating, so that power consumption can be significantly reduced. Further, in the digital signal processing device having the above configuration, the addition means is an addition / subtraction means that can also perform a subtraction process, and the process of multiplying the signal by a predetermined multiplication value by the first multiplication means is performed by the first multiplication means. Multiplies the signal by a multiplication value of a predetermined multiple or an inverse of a predetermined multiple and outputs the signal to the addition / subtraction means, and the addition / subtraction means adds or subtracts the output of the first multiplication means and the output of the delay means. By repeating the arithmetic process of the delay means inputting the output of the addition / subtraction means, the signal is replaced with the first process of multiplying the signal by a predetermined multiplication coefficient, and the second multiplication means is the signal. Is multiplied by a predetermined multiplication value, the second multiplication means multiplies the signal by a multiplication value of a predetermined multiple or an inverse number of the predetermined multiple and outputs the process to the addition / subtraction means, and the addition / subtraction means performs the second multiplication / subtraction means. The output of the multiplication means and the output of the delay means are added or subtracted, and the delay means repeatedly inputs the output of the addition / subtraction means to multiply the signal by a predetermined multiplication coefficient. At least one of the replacements with the second process may be done. Since the addition / subtraction means adds or subtracts the output of the first or second multiplication means and the output of the delay means, it only adds the output of the first or second multiplication means and the output of the delay means. In some cases, the number of times the process is repeated can be reduced as compared with the case of. For example, a given multiplication factor is 0. If it is 9375 and the multiplication value of the predetermined multiple or the reciprocal of the predetermined multiple is 1/16, the multiplication of the predetermined multiple or the reciprocal of the predetermined multiple in the initial processing is required, although the addition alone requires 15 iterations. Is set to 1, and the multiplication value of the predetermined multiple or the reciprocal of the predetermined multiple in the second process is set to 1/16, and the subtraction is performed twice. As a result, even if the accuracy of the multiplication coefficient increases and the number of digits of the processed data increases, the increase in the calculation clock frequency can be reduced. Therefore, even if the accuracy of the multiplication coefficient value is improved, the power consumption can be kept low. it can. Further, it is desirable that the multiplication value of the predetermined multiple or the reciprocal of the predetermined multiple is set to a different value each time the arithmetic processing is repeated. As a result, the number of iterative processes can be reduced. For example, if the predetermined multiplication coefficient is 0.9375 and the multiplication value of the predetermined multiple or the reciprocal of the predetermined multiple is 1/16, the addition alone requires 15 iterations, but the predetermined multiple or the reciprocal of the predetermined multiple. If the multiplication value of is switched to 1/2, 1/4, 1/8, 1/16 for each iterative process, the predetermined multiplication coefficient can be set to 0.9375 by four iterative processes with only addition. When the predetermined multiplication coefficient is 0.90625, the multiplication value of the predetermined multiple or the inverse of the predetermined multiple in the first processing is set to 1, and the multiplication value of the predetermined multiple or the inverse of the predetermined multiple in the second and subsequent processing is 1 /. When subtraction is performed as 32, four iterations are required to realize the multiplication process with the predetermined multiplication coefficient 0.90625 (= 1-1 / 32-1 / 32-1 / 32), but it is a predetermined multiple or If the multiplication value of the inverse of the predetermined multiple is switched to 1, 1/16, 1/32 for each iterative process, the predetermined multiplication coefficient is 0. It only needs to be repeated 3 times to realize the multiplication process of 90625 (= 1-1 / 16-1 / 32). Further, when the predetermined multiplication coefficient is expressed by two bits of "0" and "1" and the digits of "1" are continuous for three or more digits, it is desirable that the addition / subtraction means perform subtraction. .. As a result, the addition / subtraction means can perform the subtraction process only when the number of repetitions can be reduced as compared with the case where the addition / subtraction means performs only the addition. Further, in order to achieve the above object, in the audio signal reproduction device according to the present invention, a delta-sigma modulation means for inputting a pulse code-modulated PCM signal and delta-sigma-modulating the PCM signal. The configuration includes a PWM means that pulse-width-modulates a signal output from the delta-sigma modulation means to generate a 1-bit digital signal, and a demodulation means that demodulates the 1-bit digital signal into an analog signal. According to such a configuration, since the 1-bit digital signal can be digitally amplified and then demodulated into an analog signal, the sound source can be reproduced more faithfully than the conventional multi-bit PCM method. Also, a PWM modulation method (for example, 352.) that has a lower sampling frequency than the PDM modulation method (2.8MHz or 5.6MHz) for a 1-bit signal. Since it is generated by 8kHz), switching loss of the switching amplifier can be suppressed, power consumption can be reduced, and unnecessary radiation can be suppressed. As a result, noise shielding measures such as double shielding with steel plates and copper plates, which are indispensable for the PDM modulation method, are not required, and products can be configured with plastic cabinets, etc., and miniaturization, weight reduction, and cost reduction can be achieved. it can. Moreover, since a 1-bit digital signal is generated by pulse-width-modulating a signal obtained by delta-sigma-modulated a PCM signal, a conventional 1-bit digital signal is generated from a PCM signal only by a delta-sigma modulation circuit. Compared with the method, the sampling frequency of the delta-sigma modulation circuit can be made extremely small. In other words, each work between each clock can be done with a great margin. Therefore, the work performed by one clock can be further divided. That is, if the work is to be decomposed into n steps, it may be performed with n times the clock. Since the sampling frequency of the delta-sigma modulation circuit is extremely reduced as described above, even if n is 6 or 7, the above effect is not lost. Furthermore, the above n steps are basically the same, such as integration work, and only the constant values handled by each step are different. Therefore, if the work of switching the constant values and the basic work can be performed routinely. A given delta-sigma modulation can be performed. This greatly simplifies the configuration in terms of software and hardware. That is, it is possible to further prevent the generation of noise, which is a countermeasure against unnecessary radiation. Further, in the above configuration, the digital signal processing device may be used as the delta-sigma modulation means. As a result, it is possible to significantly reduce power consumption. Further, in the above configuration, the delta-sigma modulation means may alternately process the left channel signal and the right channel signal of the audio signal. As a result, the multiplication means, the addition means, and the quantization means can be used in common for the left channel and the right channel, which further reduces the circuit and leads to the reduction of power consumption. Further, the audio signal reproduction device having any of the above configurations may be a portable audio signal reproduction device. As a result, it is possible to reduce the power consumption, the size and the weight, and the cost of the portable audio signal reproduction device, which is indispensable for the reduction of the power consumption, the size and the weight, and the cost.

FIG. 1 is a diagram showing a configuration example of an MD reproduction device according to the present invention, FIG. 2 is a diagram showing a configuration example of a 7th-order delta-sigma modulation circuit included in the MD reproduction device of FIG. 1, and FIG. 3 is a diagram of FIG. A diagram showing an example of a configuration of a PWM circuit included in an MD playback device, FIG. 4 is a diagram showing the relationship between the clock signal of the 96-ary counter in the PWM circuit of FIG. 3, the count value of the 96-ary counter, and the PWM signal. 5 shows an example of a configuration of a PDM signal generation circuit included in a conventional 1-bit audio signal reproduction device, and FIG. 6 shows another configuration example of a 7th-order delta-sigma modulation circuit included in the MD reproduction device of FIG. It is a figure.

An embodiment of the present invention will be described below with reference to the drawings. As the audio signal reproduction device according to the present invention, an MD reproduction device will be described here as an example. FIG. 1 is a block diagram showing a configuration example of an MD reproduction device according to the present invention. The optical pickup device 2 extracts a signal from MD1 and sends it to the extension circuit 3. The decompression circuit 3 decompresses the input signal (compressed music data). As a result, the signal output from the extension circuit 3 becomes the PCM signal S1 having a sampling frequency of 44.1 kHz. The oversampling circuit 4 converts the PCM signal S1 output from the extension circuit 3 into a 24-bit (multi-bit) PCM signal S2 having a sampling frequency of 8 fs. However, fs = 44.1kHz. The 7th-order delta-sigma modulation circuit 5 delta-sigma-modulates the PCM signal S2 output from the oversampling circuit 4 to generate a 6-bit PCM signal S3 for the left channel and a 6-bit PCM signal S4 for the right channel. The sampling frequency of the 6-bit PCM signals S3 and S4 is 8fs. The PWM circuit 6 pulse width modulates the left channel 6-bit PCM signal S3 output from the 7th-order delta-sigma modulation circuit 5 to generate a left-channel 1-bit PWM signal S5, and generates a 7th-order delta-sigma modulation circuit. The 6-bit PCM signal S4 for the right channel output from 5 is pulse-width modulated to generate the 1-bit PWM signal S6 for the right channel. The left channel 1-bit PWM signal S5 output from the PWM circuit 6 is converted to an analog signal by the switching amplifier 7, amplified, and then the high frequency component is removed by the low-pass filter (LPF) 8 and then by the left channel speaker 9. Become a voice. In addition, the 1-bit PWM signal S6 for the right channel output from the PWM circuit 6 is converted to an analog signal by the switching amplifier 10 and amplified, and then the high frequency component is removed by the low-pass filter (LPF) 11 and the speaker for the right channel is used. It becomes a voice by 12. In the present embodiment, the extension circuit 3, the oversampling circuit 4, the 7th-order delta-sigma modulation circuit 5, and the PWM circuit 6 are mounted on one system LSI, but they may be provided separately. Subsequently, the 7th-order delta-sigma modulation circuit 5 and the PWM circuit 6, which are the feature portions of the present invention, will be described in more detail. First, the 7th-order delta-sigma modulation circuit 5 will be described. A configuration example of the 7th-order delta-sigma modulation circuit 5 is shown in FIG. The 7th-order delta-sigma modulation circuit in Fig. 2 includes input terminal IN, output terminal OUT, shifters 14 to 16, adder 17, quantizer 18, and registers ds1_reg to ds7_reg, out_reg, ACC, and reg. It is a digital signal processing device composed of selectors 19 to 23. The input terminal IN is connected to the 01 input terminal of the selector 21, and the output terminal of the selector 21 is connected to the input side of the shifter 14. The adder 17 inputs the outputs of the shifters 14 and 15 in reverse, and inputs the outputs of the shifters 16 in reverse. The output side of the adder 17 is connected to the input side of the register ACC. Then, the output side of the register ACC is connected to the 10 input terminal of the selector 21 and the input side of each of the registers ds1_reg to ds7_reg and out_reg. The output side of registers ds1_reg is connected to the 000 input terminals of selectors 19 and 20, the output side of registers ds2_reg is connected to the 001 input terminals of selectors 19 and 20, and the output side of registers ds3_reg is connected to 010 of selectors 19 and 20. "Connected to the input terminal, the output side of the register ds4_reg is connected to the" 011 "input terminal of selectors 19 and 20, the output side of the register ds5_reg is connected to the" 100 "input terminal of the selectors 19 and 20, and the output side of the register ds6_reg is. It is connected to the "101" input terminal of selectors 19 and 20, and the output side of the register ds7_reg is connected to the "110" input terminal of selectors 19 and 20. Further, the output side of the register out_reg is connected to the input side of the quantizer 18, and the output side of the quantizer 18 is connected to the 111 input terminal of the selector 20 and the input side of the register reg. Then, the output side of the register reg is connected to the output terminal OUT. Further, the output terminal of the selector 19 is connected to the 1 input terminal of the selector 22, and the output terminal of the selector 22 is connected to the input side of the shifter 15. The output terminal of the selector 20 is connected to the 1 input terminal of the selector 23, and the output terminal of the selector 23 is connected to the input side of the shifter 16. Shifters 14 to 16 are controlled by shifter control signals ctl1 to ctl3, respectively. Selector 19 is controlled by the selection signal regsel_1, selector 20 is controlled by the selection signal regsel_2, selector 21 is controlled by the selection signal asel, selector 22 is controlled by the selection signal bsel, and selector 23 is controlled by the selection signal csel. .. Selectors 19 to 23 select an input terminal that matches the content of each selected signal, and output the signal input to the selected input terminal to the output terminal. The register ACC is controlled by the enable signal enable_acc, the registers ds1_reg to ds7_reg are controlled by the enable signals enable_1 to enable_7, and the register out_reg is controlled by the enable signal enable_o. Then, data in which all bit strings are 0 is input to the 00 input terminal of the selector 21, the 0 input terminal of the selector 22, and the 0 input terminal of the selector 23. With such a configuration, when performing multiplication processing, the control signal asel of selector 21, the control signal bsel of selector 22, and the control signal csel of selector 23 are switched to signals for multiplication processing, and shifters 14, 15, and 16 are used. The multiplication result can be obtained by combining with the adder 17. For example, in the PDM signal generation circuit of FIG. 5, the same result obtained by multiplying the 358.8 kHz 24-bit PCM signal input from the input terminal IN by the multiplier 101 is obtained by the 7th-order delta-sigma conversion of FIG. In order to obtain it in the circuit, when the multiplication coefficient m1 = 0.5, the selection signal asel of the selector 21 is set to 01 in the 7th-order delta-sigma conversion circuit in Fig. 2, and the output data dataa of the selector 21 taken into the shifter 14 is the shifter. Shift to the right by 1 bit at 14, and when the multiplication factor m1 = 0.25, set the selection signal asel of selector 21 to 01 in the 7th-order delta-sigma conversion circuit in Fig. 2 and set the output data dataa of selector 21 to be taken into shifter 14. Is shifted to the right by 2 bits with the shifter 14, and the output value of the shifter 14 is stored in the register ACC by setting the selection signals bsel and csel to 0. When improving the accuracy of the multiplication coefficient m1 in order to improve the sound quality, shifter values having different shift amounts can be added as needed. For example, the case where the multiplication coefficient m1 is set to 0.9375 will be described below. In this case, the 7th-order delta-sigma modulation circuit 5 has the circuit configuration shown in FIG. 6 instead of the circuit configuration shown in FIG. In FIG. 6, the same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The 7th-order delta-sigma modulation circuit shown in FIG. 6 has a configuration in which the selector 22 of the 7th-order delta-sigma modulation circuit shown in FIG. 2 is replaced with a selector 22'. Then, the output side of the register ACC is connected to the "10" input terminal of the selector 22', the output terminal of the selector 19 is connected to the "00" input terminal of the selector 22', and the output terminal of the selector 22'is the input of the shifter 15. Connected to the side. Data in which all bit strings are 0 is input to the "01" input terminal of the selector 22'. The selector 22'is controlled by the selection signal bsel, selects an input terminal that matches the content of the selection signal, and outputs the signal input to the selected input terminal to the output terminal. The adder 17 can reverse-input the output of the shifter 14 by an external signal (not shown) without non-inverting input. First, in the 7th-order delta-sigma conversion circuit of FIG. 6, the selection signal asel of the output of the selector 21 is set to 01, and the output data dataa of the selector 21 taken into the shifter 14 is shifted 1 bit to the right by the shifter 14 and selected. By setting the signal bsel to 01 and the selection signal csel to 0, the output value of the shifter 14 is stored in the register ACC. Then, the selection signal asel of the selector 21 is set to 01, the output data dataa of the selector 21 taken into the shifter 14 is shifted to the right by 2 bits by the shifter 14, the selection signal bsel is set to 10, and the selection signal csel is set to 0. By setting, the added value of the output of the shifter 14 and the output of the shifter 15 is stored in the register ACC. At this point, the multiplication factor m1 is 0. It corresponds to 75 (= 1/2 + 1/4). Further, the selection signal asel of the selector 21 is set to 01, the output data dataa of the selector 21 taken into the shifter 14 is shifted to the right by 3 bits by the shifter 14, the selection signal bsel is set to 10, and the selection signal csel is set to 0. By setting, the added value of the output of the shifter 14 and the output of the shifter 15 is stored in the register ACC. At this point, the multiplication factor m1 corresponds to 0.875 (= 1/2 + 1/4 + 1/8). Further, the selection signal asel of the selector 21 is set to 01, the output data dataa of the selector 21 taken into the shifter 14 is shifted to the right by 4 bits by the shifter 14, the selection signal bsel is set to 10, and the selection signal csel is set to 0. By setting, the added value of the output of the shifter 14 and the output of the shifter 15 is stored in the register ACC. At this point, the multiplication factor m1 corresponds to 0.9375 (= 1/2 + 1/4 + 1/8 + 1/16). By shifting the signal a plurality of times by the shifter 14 as described above, the accuracy of the multiplication coefficient can be improved. In the above operation (hereinafter, also referred to as the first operation), addition is required four times in order to set the multiplication coefficient m1 to 0.9375, but the 7th-order delta-sigma modulation circuit 5 shown in FIG. 6 has the following operation (hereinafter, also referred to as the first operation). The accuracy of the multiplication coefficient can also be improved by the second operation). Similar to the above, the multiplication coefficient m1 is set to 0. In the case of 9375, in the 7th-order delta-sigma conversion circuit of FIG. 6, first, the selection signal asel of the selector 21 is set to 01, and the output data dataa of the selector 21 taken into the shifter 14 is not shifted by the shifter 14, but the selection signal. By setting bsel 01 and setting the selection signal csel to 0, the output value of the shifter 14 is stored in the register ACC. Then, the adder 17 reverse-inputs the output of the shifter 14 instead of the non-inverting input, sets the selection signal asel of the selector 21 to 01, and sets the output data dataa of the selector 21 taken into the shifter 14 to the right by 4 bits with the shifter 14. By shifting and setting the selection signal bsel 10 and the selection signal csel 0, the added value of the inverted output to subtract the output of the shifter 14 and the output of the shifter 15 is stored in the register ACC. Store. At this point, the multiplication factor m1 already corresponds to 0.9375 (= 1-1 / 16). In this operation, two additions and subtractions are sufficient, and the processing is reduced compared to the calculation by only addition. As a result, even if the accuracy of the multiplication coefficient increases and the number of digits of the processed data increases, the increase in the calculation clock frequency can be reduced. Therefore, even if the accuracy of the multiplication coefficient value is improved, the power consumption can be kept low. it can. Whether the 7th-order delta-sigma modulation circuit 5 in Fig. 6 performs the first operation or the second operation is determined by the digit in which "1" stands when the fixed coefficient expressed in binary is expanded into addition. It is effective to decide to adopt the second operation when it is continuous for 3 digits or more. In the above example where the multiplication coefficient m1 is set to 0.9375, when expressed in binary, subtraction is used for m1 = 0.1111 = (1/2) + (1/4) + (1/8) + (1/16). The method used was m1 = 0. It means that it was processed as 1111 = (1)-(1/16). Then, the value obtained by multiplying the input signal stored in the register ACC by the multiplication coefficient m1 is stored in the registers ds1_reg to ds7_reg and out_reg corresponding to the first-order delayers 121 to 128 in FIG. The registers ds1_reg to ds7_reg and out_reg are each 24 bits wide. When the selection signal asel of selector 21 is 10, the output of register ACC (same as the register value of register ds1_reg) becomes the output of selector 21, and the output of that selector 21 is shifted by the shifter 14 by the value corresponding to the multiplication factor m2. It is multiplied to become one non-inverting input of the adder 17. When the selection signal bsel of the selector 22 is 1 and the selection signal regsel_1 of the selector 19 is 001, the previous register value of the register ds2_reg becomes the output of the selector 22, and the output of the selector 22 is the output of the shifter 15. It becomes the other non-inverting input of the adder 17 without shift multiplication. When the selection signal csel of the selector 23 is 1 and the selection signal regsel_2 of the selector 20 is 010, the previous register value of the register ds3_reg becomes the output of the selector 23, and the output of the selector 23 is the output of the shifter 16. It is shift-multiplied by the value corresponding to the multiplication coefficient m8 and becomes the inverted input of the adder 17. In this case, the adder 17 performs a process corresponding to the adder 113 provided in the PDM signal generation circuit of FIG. By changing the selection signals of the selectors 19 to 23 and the control signals of the shifters 14 to 16, the adder 17 can perform processing corresponding to each of the adders 114 to 118 provided in the PDM signal generation circuit of FIG. In this way, the process of obtaining each next-order data can be performed with a single clock, so the n-th order noise shaver (delta-sigma modulation circuit) obtains all order data with a minimum of n times of clock. Can be done. Since the 7th-order delta-sigma modulation circuit of FIG. 2 or 6 does not need to be provided with multipliers 101 to 111 as in the PDM signal generation circuit of FIG. 5, the circuit scale can be reduced. Moreover, since the order of delta-sigma modulation can be easily increased, the noise characteristics can be made very good. Furthermore, the sampling frequency of the input signal can be kept very low. Further, it is preferable to calculate the frequency of the main clock from the total number of processes and create an address counter required for the ROM (not shown) provided in the 7th-order delta-sigma modulation circuit of FIG. 2 or FIG. If you need 24 steps for the left channel and 24 steps for the right channel in the period of 8fs, 8fs x (24 steps x 2ch) = 384fs (16. 8688MHz) clock is required. This clock or a signal whose phase is shifted from this clock becomes the clock of each register. A 24-ary counter (not shown) is provided in the 7th-order delta-sigma modulation circuit of FIG. 2 or 6, and the counter value of the 24-ary counter becomes the address of the ROM described above, and the register enable signals enable_1 to enable_7 are stored in the ROM. , Enable_o, and enable_q, selector selection signals asel, bsel, csel, regsel_1, and regsel_2, and control signals ctl1 to ctl3 that control the shift amount of the shifter are stored, and these signals are output for each clock. Change the contents of. Then, the shifters 14 to 16, the adder 17, and the quantizer 18 alternate between the left channel and the right channel (for example, when the 8fs signal is "1", the left channel, when "0", the right channel, etc.). Use for. As a result, the circuit can be significantly reduced. The registers ds1_reg to ds7_reg, out_reg, and reg and the output terminal OUT are separated from those used for the left channel and those used for the right channel. In the 7th-order delta-sigma modulation circuit of Fig. 2 or Fig. 6, the register value of register ds1_reg, the register value of register ds2_reg, the register value of register ds3_reg, the register value of register ds4_reg, the register value of register ds5_reg, the register value of register ds6_reg, The data stored in the register value of register ds7_reg and the register value of register out_reg (24-bit width for each of Lch and Rch) are ds1, ds2, ds3, ds4, ds5, ds6, ds7, out in the PDM signal generation circuit shown in FIG. Corresponds to. Registers ds1_reg ~ ds7_reg and out_reg each have an enable, and are configured to store redata that is valid only once in the period of 8fs, so 384fs (= 16. Since the register is not operating every 8688MHz), it does not affect the power consumption at all. As described above, the multiplication process can be realized by the combination of the shifters 14 to 16 and the adder 17. Then, the multiplication coefficient is set according to the characteristics to be finally obtained. Finally, the 24-bit data stored in the register out_reg is divided into 47 by the quantizer 18 and replaced with 6-bit data (in the case of this embodiment, a total of 47 values of 000000 to 101110). ). That is, the PCM signal input to the input terminal IN is delta-sigma modulated and converted into a low-bit PCM signal. The low-bit PCM signal is output from the output terminal OUT via the register reg. Next, the PWM circuit 6 will be described. A configuration example of the PWM circuit 6 is shown in FIG. The PWM circuit 6 of FIG. 3 is composed of input terminals 24 and 27, comparators 25 and 28, output terminals 26 and 29, and a 96-ary counter 30. The input terminal 24 inputs the 6-bit PCM signal S3 for the left channel output from the 7th-order delta-sigma conversion circuit of FIG. 2 or FIG. The comparator 25 compares the 6-bit PCM signal S3 for the left channel input to the input terminal 24 with the counter value of the 96-ary counter 30, generates a PWM signal S5 for the left channel, and sends it to the output terminal 26. On the other hand, the input terminal 27 inputs the 6-bit PCM signal S4 for the right channel output from the 7th-order delta-sigma conversion circuit of FIG. 2 or FIG. The comparator 28 compares the 6-bit PCM signal S4 for the right channel input to the input terminal 27 with the counter value of the 96-ary counter 30, generates a PWM signal S6 for the right channel, and sends it to the output terminal 29. The 96-ary counter 30 counts 96 values in a period of 8 fs. The comparator 25 toggles to the High level when the decimal number corresponding to the 6-bit PCM signal S3 for the left channel and the count value of the 96-ary counter 30 are equal, and corresponds to the 6-bit PCM signal S3 for the left channel. When the sum of the decimal number and the counter value of the 96-ary counter 30 reaches 95, a PWM signal S5 for the left channel that toggles to the Low level is generated. In addition, the comparator 28 toggles to the High level when the decimal number corresponding to the 6-bit PCM signal S4 for the right channel and the count value of the 96-ary counter 30 are the same, and becomes the 6-bit PCM signal S4 for the right channel. When the sum of the corresponding decimal number and the counter value of the 96-ary counter 30 reaches 95, a PWM signal S6 for the right channel that toggles to the Low level is generated. The comparators 25 and 28 operate in this way only twice without the left channel PWM signal S5 and the right channel PWM signal S6 being fixed at the "High" or "Low" level for a period of 8 fs. Is to toggle. FIG. 4 shows the relationship between the clock signal CK of the 96-ary counter 30 and the count value of the 96-ary counter 30 and the PWM signal in this case. The left channel PWM signal S5 and the right channel PWM signal S6 are pulse signals having a constant amplitude and appearance frequency, and the signal level is expressed by a change in the pulse time width. Therefore, the left channel PWM signal S5 and the right channel PWM signal S6 are 1 bit in the amplitude direction, but have multiple values in the time axis direction. As shown in Fig. 4, the 47-value data conversion for the time of 1 cycle pattern 8fs (= 352.8kHz) corresponds to the one in which the width of the High level section is changed symmetrically by 768fs (= 33.8688MHz) width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used. 8688MHz) It corresponds to the one in which the width of the High level section is changed by the width. In the present embodiment, the 7th-order delta-sigma modulation circuit is used for the delta-sigma modulation circuit, but a delta-sigma modulation circuit of another order may be used.

The digital signal processing device and audio signal processing / reproducing device of the present invention can be used in various devices for processing digital signals, including audio devices.