Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit

0001Specification A phase comparison profit detector circuit, an incorrect synchronous detector circuit, and P L L circuit Technical field

0002The present invention relates to a phase comparison profit detector circuit, an incorrect synchronous detector circuit, and a P L L circuit, especially -- Case where a standard The mouth A signal is extracted from receiving data in the optical transmitter-receiver for optical communications etc. -- it is related with the P L L circuit which may be applied, the phase comparison profit detector circuit which may be applied there, and an incorrect synchronous detector circuit. PRIOR ART

0003Drawing 1 The general composition of A and the P L L circuit for clock extraction is shown. It is phase comparator 1 about the phase contrast between clock signal C L which is an output of VCO (voltage control oscillating circuit) 40 in circumferential composition, and input data D A. It detects by 0, responding to the detection output concerned -- Charge pump 2 0 is charged -- as a result, the current proportional to the phase comparator output concerned -- roux Puffy Ruta 3 0 is supplied. and loop filter 30 -- the above-mentioned supply current -- smoothing -- Re and its result -- VC04 It is fed back to 0. Again 1 B is the above-mentioned roux Puffy. Ruta 3 It is a circuit diagram showing an example of the composition of zero. as [ show / in the figure ] -- the case of this example -- roux Pfilter 3 0 consists of a series circuit of resistance R and capacitor C -- smooth in an input It has a function which it turns and changes into output voltage. By above-mentioned operation, it is in the P L L circuit concerned. It becomes possible to acquire clock signal C L in sync with input data signal D A. here -- phase comparator 1 the phase comparison profit in 0 -- K p and charge pump 2 0 -- the current amplitude to kick -- I c and loop filter 3 the transfer function of 0 -- F (s) Profit of .VCO the case where it is referred to as K V -- the ? concerned L The loop gain of L circuit is denoted by the following well-known formulas. Open loop gain = [kapparho, I c, F (s), and Kv] /s

0004Closed loop gain = i eta/ o u t

0005= [K, I c, F (s), and Kv] / [s+p, I c, F (s), and K v] It is as a loop filter again, When the thing of 2nd [ completeness ] order type is used, Open loop gain = [Kp and I c - R and KvZs] - [1 + 1/s CR] Closed loop gain = [kapparho, I c, R, and kappa nu -] (1+s CR) / Each loop gain of [s^2, CR+Kp, I c, R, and K v -] (1+s CR) is obtained.

0006Cycle to which, as for the power Turn off frequency of closed loop gain, Open loop gain is set to 0 d B from an upper type It is a number and they are phase comparator 10 and Chia. It is a ratio to each profit of Di pump 20 and VC040. (refer to figure 2 A) which example 10 To understands. Here, it is this cutlet when the profit of each part is large. Toff frequency becomes high and is in the tendency which appearance A casita increases as a result. another side -- this , -- when a profit is small, (refer to figure 2B) and cutoff frequency become low -- the -- a result -- a phase margin -- decreasing -- peaking -- increasing -- a tendency -- it is . that case -- a phase -- incorrect -- It is in the tendency for a difference response to worsen.

0007here -- the closed loop characteristic as a jitter characteristic of P L L -- what is called Jitter transfer it corresponds -- output to input Gitta in the state where PLL was locked It is expressed with Gitta's amplification rate. This value is so good that the speed of response of PL L is slow. on the other hand, P LL can bear Gitta of which grade, where mouth A is carried out -- what is called A bit that is that index when it thinks from the standpoint of a Tatare lance, so that the speed of response of PL L is conversely quick -- power-proof -- a large -- Like -- . Therefore, both have a relation of a trade-off mutually.

0008Pro who shows an example of the discernment timing signal extraction circuit where Drawing 3 applied the PL L method It is a A figure. The data of input data signal D A is extracted like the above by clock signal C L extracted by a P L L circuit function in discernment circuit 100. Frequency Synthesiology general in the P L L circuit in such an optical transceiver circuit etc. It is used by THE. Data random as an input data signal unlike a PLL circuit It is inputted. therefore, cycle which should be extracted the case where change of the frequency of an input signal is large the level of several ingredient value falls relatively -- the above-mentioned PL L loop gain falls as a result The operation becomes unstable.

0009Drawing 4 -- as the above-mentioned phase comparison circuit 10 -- well-known half rate clock B a n g -- The example of a circuit at the time of applying a B a ng circuit is shown. the inside of the figure, and input data signal D A -- an opposite -- it carries out -- Two D -- a F F (D -- flip-flop) circuit -- respectively -- Cros for data discernment A signal Mushi and this Clock signal C L for Edge detection delayed by pi/2 phase performs data discernment operation. And a deed and signal D c are acquired for an exclusive OR operation in exclusive OR circuit EX O R to each signal D a acquired as a result and D b.

0010As a result, the phase of data signal D A is overdue to the phase of discernment The mouth A signal C L. In the Had been case as [ show / in Drawing 6 / probable ] -- signal with intermittent exclusive Junichiro output D c it becomes -- the phase of another side and data signal D A receives the phase of discernment clock signal C L -- Advance the case where it is by Hmm -- a figure -- as [ show / in 7 ] -- exclusive Junichiro output D c serves as a continuous signal -- good Potential is high.

0011As a result, it is charge pump 2 to such a phase comparison result. 0 and roux Puffy Level of the signal acquired through the low pass filter by Ruta 30, Drawing 6 it is low when a phase comparison output is an intermittent signal obtaining -- being continuous like [ in the case of being another side figure 7 ] the case of a phase comparison output with a high possibility -- the output level of the above-mentioned low pass filter -- high -- To -- . And it responds to the output level of this low pass filter, and is V C O 4. Zero oscillation circumferences A wave number is controlled.

0012namely, -- when the phase of the data signal is behind, a V O C input level falls -- That a result -- V C O oscillating frequency -- falling -- a data signal -- it acts so that the phase of clock signal C L may be delayed according to a phase. conversely, when the phase of the data signal is progressing, V C O oscillating frequency rises -- you make it follow the phase of a clock signal to a data signal It obtains and acts.

0013here -- a figure -- in the case of 6 -- the numerals of the data of A system of the input data signals are change If it carries out, in a phase comparison output, H signal of 1 Z 4 cycle of a clock signal will be outputted. H signal is not outputted the case where the numerals of the data of an another side A system continue in the meantime. It becomes. this situation -- Drawing 8 thru/or a figure -- 1 It is shown in 0.

0014[ the case of Drawing 7 ], i.e., when the phase of the data signal is progressing, it is shown in Drawing 7 -- as -- said -- since the exclusive OR between Tooth data does not occur -- statistical -- phase comparison output As -- H signal and L signal will occur by halves. however, A system L signal is outputted when a same sign continues in B system -- another side opposite sign H signal will be outputted when a repetition continues. this situation -- a figure -- 1 1 thru/or a figure -- 1 It is shown in 3.

0015Thus, a phase comparison output is not necessarily a phase between a data signal and a clock signal. The contents of not only a difference but a data signal themselves (in this case, what is called a rate of edge and the duty first class) It will be affected. As a result, the above-mentioned phase comparator 1 Zero profits Profitable K p will be changed, with the loop gain of the above-mentioned whole P L L circuit will be changed. Drawing 1 4 alpha- and figure 1 Phase comparator 1 with which 4 beta has composition as shown in Drawing 4 Zero outputs A wave-like example is shown. a figure -- 1 D in ON A casita and a phase comparison circuit -- as [ show / in 4A ] -- as opposed to the ideal output characteristic shown with a dashed line -- setup hold operating characteristic of a F F circuit By Influence etc., as shown by the solid line in fact, a provincial accent arises in a waveform. Drawing 1 A provincial accent arises in a waveform also with the rate of edge of like and the above-mentioned input data shown in 4 beta. as a result, the loop gain of a P L L circuit is changed -- having -- like Above -- circuit operation -- unstable It becomes a factor. The indication of an invention

0016the present invention takes an example by the above-mentioned problem -- it is not based on change of the rate of edge of input data, duty, etc., the influence by the circuit characteristic, etc. -- P L L time which can provide the stable P L L circuit operation It aims at providing a way.

0017Phase conditions make it differ concerning discernment of an input data signal at the present invention, and they are a plurality of phases. It is Inspection about a phase comparison profit by comparing a deed and each phase comparison result for comparison operation. It comes out and carries out. Therefore, set of the rate of edge of an input data signal, duty, and also a discrimination circuit On time phase which considered the change factor of phase comparison profits, such as the rise' hold characteristic A comparison profit is detectable. As a result, it is based on the phase comparison detection result concerned, and is a P L L circuit. Exact loop gain Compensation control on time by controlling loop gain It is realizable. Brief explanation of the drawings

0018Drawing 1 A and 1 B are the figures showing the composition of the conventional P L L circuit. Drawing 2 A and 2 B are the explanatory views about the loop gain of a P L L circuit.

0019Drawing 3 is an explanatory view of the conventional P L L circuit of operation.

0020Drawing 4, Example of a circuit of the conventional half rate clock B a n g - B a n g phase comparator It is a shown figure.

0021Drawing 5 is a figure for explaining a data discernment phase.

0022Drawing 6 -- a figure -- it is time chart of each signal in the circuit of 4 (the 1).

0023Drawing 7 -- a figure -- it is time chart of each signal in the circuit of 4 (the 2).

0024Drawing 8 -- a figure -- it is time chart of each signal in the circuit of 4 (the 3).

0025Drawing 9 -- a figure -- it is time chart of each signal in the circuit of 4 (the 4).

0026Drawing 1 0 -- a figure -- it is time chart of each signal in the circuit of 4 (the 5). Figure 1 1 is time chart of each signal in the circuit of Drawing 4 (the 6). Drawing 1 2 -- a figure -- it is time chart of each signal in the circuit of 4 (the 7). Drawing 1 3 -- a figure -- it is time chart of each signal in the circuit of 4 (the 8). Drawing 1 o which is figure for explaining degradation state of A, 4 B, and the phase comparison characteristic (the 1)

0027Drawing 1 It is a circuit Plock figure of an example of 5 and a P L L circuit with a phase comparison profit compensation function, and is Ah. To.

0028Drawing 1 It is a circuit diagram showing an example of 6 and a phase comparison profit detector circuit.

0029Drawing 1 It is a figure for explaining the degradation state of 7 and the phase comparison characteristic (the 2). Drawing 1 8 is the Plock figure of one example of the present invention.

0030Drawing 1 9 -- Drawing 1 Figure for explaining the phase comparison profit detection principle by the composition shown in 8 it is -- omicron

0031Drawing 2 It is a circuit diagram of 0 and one example of the present invention.

0032Drawing 2 1 is Drawing 2. It is Thailand Muchiya 1 A of each signal in the circuit shown in 0.

0033Drawing 2 2 -- Drawing 2 Figure for explaining the phase comparison profit detection principle by the composition shown in 0 it is -- o

0034Drawing 2 3 is Drawing 2. One fruit of the present invention using the phase comparison detector circuit which has the composition shown in 0 P depended on the example of Application

0035Drawing 2 4 -- Drawing 2 5 -- Drawing 2 Figure for explaining the phase comparison profit detection principle by the composition shown in 4 it is .

0036Drawing 2 It is a circuit diagram of 6 and the incorrect synchronous detector circuit by the example of further others of the present invention. Drawing 2 7 is Drawing 2. It is a figure for explaining the incorrect synchronous detection principle by the composition shown in 6. Explanation of a desirable example

0037The composition of the example of the present invention is explained with a drawing below.

0038It is a P L L circuit like Above. (for example, a figure 1 circuit shown in 5) It is profit change V C 0 4 As what detects and compensates the profit of 0, phase comparator 1 the profit of 0 -- data D A the rate of edge detects -- being based on the detection result -- charge pump 2 Output power of 0 a style is adjusted -- or filter 3 Direction of adjusting and compensating the capacity value or resistance of 0 A method can be considered. a figure -- 1 the case of 5 -- phase comparison profit circuit 2 1 0 -- account 1 of phase comparison the profit of 0 is detected -- being based on the detection result -- control circuit 2 2 0 -- Special of a charge pump A sex is controlled.

0039in this case, account 1 of phase comparison 0 -- for example, a figure -- 1 H o g g e phase of common knowledge as shown in 6 a comparison machine -- like -- the Sawtooth wave phase comparison characteristic (figure 1 7 reference) the case of the phase comparator which it has -- phase it is the value it was decided that a cycle would be -- a profit is decided by that output amplitude. and a figure -- 1 Like shown in 5 it sets in the phase comparison profit compensation circuit of To -- change of the amplitude by the rate change of edge of data It detects. namely, this case -- E X O R circuit 2 1 the output of 3, and data -- edge -- an owner -- a To case, at i.e., the time of change of data, -- " -- it becomes "L" when there is nothing, H" and. The rate of edge of data is detectable by equalizing this by L P F (circuit by R and C). And control circuit 2 2 It is charge pump 2 about a changed part of the output amplitude of a phase detector by 0. It is the method of compensating with adjusting the current of 0.

0040On the other hand, about a discrimination circuit and a counting-down circuit, since it can constitute as some phase comparators, it is composition. When the well-known B n a g - B a n g phase comparator with which there are few parts and they end is applied, this -- the phase comparison characteristic is expressed in a phase comparator by step function (B a n g--B a n g phase Comparison Special nature) -- stochastic variation of (for example, characteristic of the dashed line of figure 1 4 A), and a phase comparator output It has the characteristic that respond and a phase comparison profit value is decided. change important point of the phase comparison profit in this case as Cause, it adds to change of the rate of edge of data -- Gitta of (1) input data, and (2) input De Setup' hold of the duty of - Tha, and the discrimination circuit (FF) in (3) phase comparator Variation And change of the characteristic etc., etc. are mentioned. therefore, a phase comparison profit is received in this case Design -- a figure -- comparing with the case of 16 and 17 -- the inside of being complicated and an applicable system -- phase It is adjustment about the loop gain of whole P L L which contained the phase comparison profit after incorporating a comparison circuit. It is necessary to carry out.

0041Then, in the P L L circuit provided with the above-mentioned B a n g-B a n g phase comparator etc. in Origin, Gitta of these input data, the duty of input data, and phase comparison It is based on the variation of the setup' hold characteristic of discrimination circuit [ of a vessel ] (FF), change, etc. The circuit which detects change of a phase comparison profit correctly is provided.

0042Drawing 18, It is a principle figure of one example of the present invention. The phase comparison profit detector using the figure and the above-mentioned B a n g-B a n g phase comparator is shown. It is this phase ratio as shown in the figure. Comparative output 300, Phase ratio which considers clock signal CL which identifies data DA as an input Delay Calibrator 311 and clock signal CL for data discernment for a predetermined period, and make them into clock signal CL. Delay device 313 to output and this delay clock signal CL are considered as an input. LPF314 which smooths phase comparator 312 and an output, 315, and difference voltage detection time It comprises way 316.

0043While data signal D A and clock signal CL synchronize in the circuit of the figure, Immediately It is with phase comparator output D 1 of a deed and each, and D2 about data discernment operation by two clock signals CL of a different phase, and C L, respectively the time of the clock synchronizer for Input data discernment, The time lag between both clock signal CL and CL', i.e., the above-mentioned predetermined time delay, to request A phase comparison profit is detected. Thereby, it is at the setup' hold time of a phase comparator. Edge rate and Gitta, duty Change Palacky, etc. of between and input data are Ah. It is also Then by a Ivy case, these -- It was which can detect a factored in phase comparison profit Because -- controlling based on the detection output concerned -- loop gain of the whole PLL circuit It can compensate so that it may become fixed. therefore, the stable response characteristic is acquired -- desired A bit The P L L circuit with which it is satisfied of the Transfer characteristic can be provided.

0044Drawing 19 shows Gentlemen phase comparison machine 311 for explaining the principle of one example of the above-mentioned present invention, and the output level of 312 -- the phase comparison characteristic of the figure -- figure 14 A and 14 B -- also being shown -- It is equivalent to that. as [ show / in the figure ] -- a phase comparison output -- phase contrast as a phase comparison result it responds and changes -- the rate of change (delta t/T), i.e., AVZ, Equivalent to phase comparison profit Kp It carries out. it sets at an upper ceremony -- AV, Smooth Y of the phase comparison output by different phase conditions was carried out. value D -- it is the difference voltage between 1 andD2. Late which delta t provides with a difference among the phase conditions concerned. Extender it is a delaying amount by 313 -- T shows a signal cycle of a clock signal.

0045Drawing 20 -- a figure -- phase comparison detection by one example of the present invention which further materialized the composition of 18 The composition of a circuit is shown. B a n g for which the circuit used the half rate clock -- It is a phase comparison profit detector circuit to which a B a n g phase comparator is applied. it is shown in a figure -- as -- as circuit and discrimination circuit (FF) -- discrimination circuit 411 for data discernment, 412, and data edge detection the for discrimination circuit 413 -- providing discrimination circuit 414 for phase comparison profit detection further Exclusive As alternation gate (EX OR), Data discernment FF output DO a and data edge detection business -- logic with FF output DOc Circuit 433 which similarly takes the logic of circuit 431 to take, circuit 432 which takes the logic of data discernment FF output DO b and FF output DO c for data edge detection, data discernment F F output DOb, and FF output DO d for phase comparison profit detection It is provided. And these outputs are at LPF 441, 442, and 443, respectively. It is smoothed and is outputted as phase comparison output Ph 1, Ph 2, and Ph 3.

0046this figure -- as [ show /, in the circuit of 20 / the wave form chart of Drawing 21 ] -- data signal D A and Crout The state where the synchronization with The signal CL can be taken, the data of A system is obtained as output DO a of discrimination circuit 411 -- the data of B system obtains as output DOb of discrimination circuit 412 , -- To be . On the other hand, as output DOc of discrimination circuit 413 for edge detection, it is a clock signal. Since standup timing coincides with the changing point of data signal DA, it is the above-mentioned Timing. The probability that the data of A system will be obtained by Tongue, and probability that the data of B system will be obtained It becomes equal. On the other hand, as the output of discrimination circuit 414 for phase comparison profit detection, The clock which is behind the changing point of data signal D A in the standup timing of a The signal a little Because -- the probability that the data of A system will be obtained by the above-mentioned timing -- day of B system The direction of the establishment which Tha can obtain becomes large.

0047as a result -- as the result of the exclusive OR between the data of these -- EXOR circuit 4 the appearance probability of H level [ in / in the appearance probability of H level in output Ph 1 of 41 / output P h 2 of EX OR 442 ], and abbreviation -- it becomes equal. On the other hand, at output P h 3 of EXOR circuit 443, it becomes higher [ the appearance probability of H level ] than former each. Namely, EXOR circuit The probability that DO a which is an input of 443, and DO d are in agreement, EXOR circuit 441 It is Ah by the input of the probability whose DO a which is input and DO c correspond, or EXOR circuit 442. It is because it is lower than the probability whose To DO b and DO c correspond. The appearance probability of A system De [ in / from the appearance probability of A system data in / like / this and the above / signal DO c / signal DO d ] - Tha is smaller, Appearance of B system data [ in / similarly / signal DO c ] The appearance probability of A system data in signal DO d is smaller than probability. To.

0048Thus, at this example, it is predetermined time intentionally. Clock signal C Lb which carried out delta t delay is generated, and A t delay of the data discernment is carried out with the data of a deed and its discriminated result. Exclusive OR with the data of the discriminated result identified with clock C L which is not is taken. Discriminated result data which performed data discernment by clock signal C L a for edge detection The same Discriminated result data identified with clock CL which does not carry out delta t delay Exclusive OR is taken. And it is L P F about the result of these two kinds of exclusive OR. It smooths and is the above-mentioned delaying amount about the level difference. This which breaks delta t by the phase normalized cycle T Phase comparison profit K p is obtained.

0049namely, -- here -- after synchronous establishment -- intentional -- delaying amount generating delta t -- false ---like -- data clock signal [ (figure the example of 20 and 21 signal C Lb) ] with which signal DA and a synchronization shifted -- raw -- Accomplish. the "false synchronous gap" clock signal -- discernment of the same data signal D A It carries out. And the exclusive OR output between the identification data obtained there and the data identified by clock signal C L a delayed pi/2 is smoothed, and "false synchronous Sure" phase comparison detection value is acquired. And identification data identified by clock signal CL of a synchronous state to this false synchronous gap phase comparison detection value, It is the same. You make it delayed pi A 2. The exclusive OR output between the data identified by It was clock signal C L a is smoothed. The Was obtained value "it is a phase comparison detection value at the time of a synchronization", i.e., , is compared. difference of this comparison result The phase contrast between clock signals CL over data signal D A is received, so that Different is large. it can be said that phase comparison detection sensitivity is as high as To -- it has and is synonymous with a phase comparison profit being high. thus, the rate of edge of the data in this time in the example concerned and duty -- each -- setup , the hold characteristic, etc. of discrimination circuit (FF) -- all -- factored in phase comparison In order to ask for a profit, It is an on time effectual phase comparison profit very correctly. Asking is possible.

0050Drawing 23, PL L circuit provided with the phase comparison profit compensation function by one example of the present invention An example is shown, The difference voltage between phase comparison output Ph 1 of phase comparator detector circuit 400 and P h 3 which have the composition of Drawing 20 is changed into a digital signal. A/D conversion machine 510, the digital difference voltage concerned is compared with a predetermined standard value -- the output current of Chia - Di pump is adjusted based on the comparison result -- it has and compensates the loop gain of the PL L circuit concerned It has composition.

0051Data output D Oa of phase comparison detector circuit 400 shown in Drawing 20 in the composition of Drawing 23 and DOb are usable as reproduction data of input data as it is. namely, these data output DO a and DOb -- a figure -- equivalent to the output of discernment circuit 100 in 3 It carries out.

0052Namely, Drawing 23 In order to control the loop gain of a P L L circuit based on the phase comparison output difference voltage between "false said term gap" discernment signal and "synchronization" discernment signal which were acquired in the PLL circuit in phase comparison detector circuit 400, The characteristic of the input signal in this time, and phase comparison The P L L circuit which has the exact loop gain compensation function which considered the circuit characteristic can be provided. It is.

0053not only the circuit composition of Drawing 23 but control circuit 520 -- output current of a charge pump Transfer Seki of filter 30 which is a determinant of the loop gain of P LL circuits other than amplitude I c SeveralF (s) , Profit Kv of VC040, etc. are controlled and the loop gain of a P LL circuit is compensated. It is not good as composition to carry out also until it says.

0054It is [ in / at an above-mentioned example / phase comparison detector circuit 400 ] a half rate clock. Although the used Ba n g -beta a n g phase comparator is applied, except [ this ] -- Full rate clock was used -- the phase comparison characteristic -- a saw -- wavelike (refer to Drawing 25) Becoming phase comparator It is also possible to receive and to apply the present invention. Drawing 24 is a phase comparison detection time in that case. The example of circuit composition of a way is shown. In the circuit of the figure, it is clock signal C To about data signal D A. Discrimination circuit 611 and data signal D A which are identified to timing, It is Late about clock signal CL. It is To identify at the timing of delay clock signal C L' delayed by Extender 622 in the specified quantity. Identification 612 is provided. And it is based on these discrimination circuits 611 and 612. EXO which takes the exclusive OR of each of discernment output DO 1 and DO 2, and data signal D A R 631 and 632 are provided, smooth Y of the output of these EXOR631 and 632 is carried out -- low -- Region passage filter 641 and 642 are provided.

0055according to the phase comparison detector circuit of Drawing 24 -- the case of Drawing 20 -- being the same -- the difference between discriminated result signal DO 1 by the phase contrast of discernment The mouth A signal C L and CL, and DO 2, these discernment a result -- signal DO -- performing the exclusion logical sum operation of 1, DO 2, and original data signal DA -- it , -- it detects by smoothing an EXOR operation result, respectively and acquiring a difference. Drawing 25 -- the -- It is a figure for explaining the difference voltage obtained at a case. LPF 64 detected here Difference voltage deltanu between 1, and output Ph l of 642 and Ph 2, To delay device 622 It is Delay amount. It breaks by delta t/T showing the amount of delay phases which normalized delta t cycle T. (refer to lower type) from which Kp which is a phase comparison profit is obtained.

0056Kp = AV/(delta t/T) carrying out based on the phase comparison detection value acquired by doing in this way -- a figure -- control circuit 52 shown in 23 0 -- loop gain determinant parameters, such as current amplitude value I c of charge pump 20 The loop gain of a P L L circuit is compensated with carrying out adjustment control.

0057it compares with the example of Drawing 16 in this case -- factors other than the rate of edge of input data Compensation is possible for profit change to depend in a phase comparison profit also to a Oh case.

0058it is good also considering a phase comparator as other composition -- it has the function to make it delay the phase of Tha [ The phase of clock signal C L, or input De - ] signal DA in the specified quantity or progress -- a phase comparator -- said -- him -- it may incorporate with the phase detector circuit which has circuit composition, and may constitute a P L L circuit. As explained above, according to the present invention, it is change' Wide of the phase comparator of a P L L circuit. In order to compensate a phase comparison profit according to Gitta of and input data, etc., P it is possible to keep constant a A [ Le of L L - ] profit with sufficient accuracy, and stable in the Gitta frequency characteristic it can change -- it has and improvement in the performance of a P LL circuit is possible.

0059In order that Drawing 26 and Drawing 27 may illustrate the incorrect synchronous detecting device by other examples of the present invention It is a figure. Drawing 26 -- a figure -- 1 That it is the same as that of the circuit composition of 8 substantially, and correspondence component part The same numerals are attached and duplication explanation is omitted.

0060in this case -- as the phase comparator of a P L L circuit -- a figure -- Sawtooth wave as shown with the dashed line of 27 What has a sex is assumed. namely, the detection voltage outputted according to detection phase contrast -- Inspection responding to appearance phase contrast -- a saw -- it has the characteristic of changing wavelike. In such a P L L circuit, it is credit in the intermediate part of the rise lamp section of this Sawtooth wave, i.e., P point in a figure, about a phase lock. It kicks, (The central portion, i.e., eye butter, between the points of input data signal D A changing [ signal ] -- It is a phase of clock signal C L so that data can be identified in the timing of the central part of A. (refer to Drawing 5) which can be locked.)

0061However, it is Sawtooth wave by change of the duty of input data signal D A, etc. in fact. It is Drawing 2 to the characteristic. A wave-like distortion as shown as the solid line of 7 may arise. In that case, in a P L L circuit, it is Drawing 2. A phase lock may be accidentally hung at Q point in seven. In this case, it becomes an incorrect synchronization and a clock signal is a crosspoint of The iron permanent wave of data - A. A possibility that identification data will become performing data discernment to timing with an error It is high.

0062incorrect synchronous detecting device according to other examples of the present invention in order to prevent such an incorrect synchronization Then. -- a figure -- 2 0 thru/or a figure -- 2 as [ stated / with 5 ] -- phase comparison detection of a phase comparator An output and delay device 3 1 3 and 6 2 It changes with the delaying amount △ t given by 2. However, absolute [ between the amount of change, data signal D A, and clock signal C L ] It has the characteristic depending on a phase. Namely, between data signal D A and clock signals C L Phase contrast is the zero neighborhood, Namely, timing (refer to Drawing 5) of the central part of the eye patterns of data signal D A In the state of identifying data, Since data is correctly discriminable, it is in the exclusive OR result of the discernment signal and data signal D A, Data discernment timing Delay device 3 1 Even if you make it delayed by 3, it is the delaying amount. deltat is smaller than cycle T to some extent. Only the difference in the grade which is [ abbreviated-] proportional to a limitation and its delaying amount arises.

0063Conversely, the timing of the crosspoint of eye patterns, i.e., the value of data signal D A A possibility that the right data can be identified when carrying out data discernment in the unfixed state is 5. By 0 % grade It is. on the other hand, the above-mentioned specified quantity from the timing delta t delay is carried out -- the delaying amount A t -- the upper -- exceeding account unfixed state (insensible belt) -- abbreviated -- exact -- discernment timing in which data discernment is possible the case where it is large to a To grade -- the possibility of the right data discernment -- 1 0 It becomes near the 0 %. the Connection Case [ he has Result, a discriminated result by such discernment timing, and no delay ] (in the case [ Namely, unfixed-like voice ] of about discernment rate 5 0 %) it will differ from a discriminated result greatly -- the difference As compared with the case of discernment near the center of the eye patterns of different Is the same as, it becomes quite large. this point -- a figure -- 2 it explains again with 7 -- data Identification near the center of eye patterns the phase comparison outputs of the delay existence of the case, i.e., the case of P point of the figure, of being another are D 1 and D 2, respectively -- that difference is A V. On the other hand, near the crosspoint of eye patterns In the phase comparison output of the delay existence of a case, i.e., the case of Q point, With and its difference become delta nu' by D 1 and D 2', respectively. Like illustration, it is clearly.

0064It is delta V < delta V. therefore -- A V exceeds a predetermined standard value -- large -- Noodle -- detecting things Therefore, an incorrect synchronization is detectable.

0065the present invention is not limited to the above-mentioned example -- the basic thought of the present invention -- Follow"-- ? It was -- various modifications until it says that it is feasible and that the modification of them is also included in the range of the present invention ---less -- it is -- .

0066The present invention and the following composition are included.

0067(Composition 1)

0068as opposed to an input data signal -- discernment timing signal for identifying the data It can set in the P L L circuit for making phase relation into predetermined phase relation. Input data signal Phase ratio which detects the phase comparison profit at the time of comparing the phase between discernment timing signals It is a Comparative gain detector circuit,

0069Phase of The 1 which detects the phase relation between an input data signal and a discernment timing signal Comparison means,

0070The phase relation between an input data signal and a discernment timing signal is shifted in the specified quantity. Phase relation shifting means,

0071The input data signal and discernment timing Trust which were shifted by the phase relation shifting means Phase comparison means of The 2 which detects the phase relation between items,

0072The difference and the above-mentioned phase relation shifting means of each output of the 1st and the phase comparison means of The 2 Phase comparison profit which detects a phase comparison profit based on the specified quantity to which phase relation is shifted Phase comparison profit detector circuit which consists of a detection means. (Composition 2)

0073In the phase comparison profit detector circuit of the above-mentioned composition 1,

0074As for the 1st phase comparison means, an input data signal and a discernment timing signal are the shape of approximately Synchronized. The phase relation between both of voice is detected,

0075As for the 2nd phase comparison means, an input data signal and a discernment timing signal are the shape of approximately Synchronized. Phase ratio of composition of detecting the phase relation between both in the state where it shifted from voice in the specified quantity Comparative gain detector circuit.

0076(Composition 3)

0077as opposed to the input data signal with which data changes a predetermined cycle -- the data -- To identify It can set in the P L L circuit for making phase relation of the discernment timing signal of a To sake into predetermined phase relation. When comparing the phase between an input data signal and a discernment timing signal It is a phase comparison profit detector circuit which detects a phase comparison profit,

0078The data discernment output of the data identification part which identifies the data of an input data signal, Data Therefore, it is the OFF of the data of an input data signal to shift discernment timing in the specified quantity [ of The 1 ]. The data correlation between the data discernment outputs of a change primary detecting element which carry out Replacement detection is detected. Phase comparison means of The 1 which compares both phase by things,

0079The data discernment output of the above-mentioned data identification part, and data Identification in the above-mentioned change primary detecting element Data phase between the data discernment outputs at the time of the ability to shift another timing in the specified quantity [ of The 2 ] further Phase comparison means of The 2 which compares both phase by detecting Seki, He is To et al. about the difference and the above-mentioned discernment timing of each output of a phase comparison means of 1st And 2. Phase comparison gain detecting means which detects a phase comparison profit based on the specified quantity of To 2 Phase comparison profit detector circuit.

0080(Composition 4)

0081as opposed to an input data signal -- discernment timing signal for identifying the data It can set in the P L L circuit for making phase relation into predetermined phase relation. Input data signal Phase ratio which detects the phase comparison profit at the time of comparing the phase between discernment timing signals It is a Comparative gain detector circuit,

0082It is [ the data of an input data signal, and ] the above-mentioned discernment timing signal about an input data signal. It is To detect about the data correlation between the data of the obtained discernment output by carrying out Identification. Phase comparison means of The 1 which compares a phase by To,

0083It is [ the data of an input data signal, and ] discernment of the above-mentioned discernment timing signal about an input data signal. It was obtained by discriminating from timing to the timing which was able to shift the specified quantity. About that of The 2 which compares a phase by detecting the data correlation between the data of a discernment output Phase comparison means,

0084The 1st and the Difference above-mentioned discernment timing signal of each output of the phase comparison means of The 2 Phase comparison profit which detects a phase comparison profit based on the specified quantity which shifts discernment timing Phase comparison profit detector circuit which consists of a detection means.

0085Composition (W)

0086The data correlation detection between the data in the 1st and the phase comparison means of The 2, and exclusive theory The above-mentioned composition 3 or 4 phase comparison profits which have the composition realized by a Riwa operation Detector circuit.

0087(Composition 6)

0088Composition which an exclusion logical sum output is smoothed and is inputted into a phase comparison gain detecting means Phase comparison profit detector circuit of Above composition 5.

0089(Composition 7)

0090Each data discernment should be considered as the composition performed by the flip-flop circuit. Phase comparison profit detector circuit of either of the Above composition 3 thru/or 6.

0091(Composition 8)

0092as opposed to an input data signal -- the discernment timing signal for identifying the data -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronous detector circuit for detecting a term.

0093Phase of The 1 which detects the phase relation between an input data signal and a discernment timing signal Comparison means,

0094The phase relation between an input data signal and a discernment timing signal is shifted in the specified quantity. Phase relation shifting means,

0095The input data signal and discernment timing Trust which were shifted by the phase relation shifting means Phase comparison means of The 2 which detects the phase relation between items,

0096It is based on the difference of each output of the 1st and the phase comparison means of The 2, and is To detect about an incorrect synchronous state. Incorrect synchronous detector circuit of Configuration.

0097(Composition 9)

0098as opposed to an input data signal -- the discernment timing signal for identifying the data -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronous detector circuit for detecting a term.

0099The data discernment output of the data identification part which identifies the data of an input data signal, Data Therefore, it is the OFF of the data of an input data signal to shift discernment timing in the specified quantity [ of The 1 ]. The data correlation between the data discernment outputs of a change primary detecting element which carry out Replacement detection is detected. Phase comparison means of The 1 which compares both phase by things,

0100The data discernment output of the above-mentioned data identification part, and data Identification in the above-mentioned change primary detecting element Data phase between the data discernment outputs at the time of the ability to shift another timing in the specified quantity [ of The 2 ] further Phase comparison means of The 2 which compares both phase by detecting Seki, It is based on the difference of each output of the 1st and the phase comparison means of The 2, and is To detect about an incorrect synchronous state. which consists of a False synchronous detection means.

0101Incorrect synchronous detector circuit.

0102(Composition 1 0)

0103as opposed to an input data signal -- the discernment timing signal for identifying the data -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronous detector circuit for detecting a term.

0104It is [ the data of an input data signal, and ] the above-mentioned discernment timing signal about an input data signal. Correlation between the data of the discernment output obtained by carrying out Identification is detected. 1st phase comparison means that compares a phase,

0105It is [ the data of an input data signal, and ] discernment of the above-mentioned discernment timing signal about an input data signal. It was obtained by discriminating from timing to the timing which was able to shift the specified quantity. Phase comparison of The 2 which compares a phase by detecting correlation between the data of a discernment output Means,

0106It is based on the difference of each output of the 1st and the phase comparison means of The 2, and is To detect about an incorrect synchronous state. Incorrect synchronous detector circuit which consists of a False synchronous detection means.

0107(Composition 1 1) The phase comparison profit detector circuit and the above-mentioned composition 8 A of either of the above-mentioned composition 1 thru/or 7 From 1 It has a circuit of at least 1 side of the incorrect synchronous detector circuits of either of 1. It is a It was P L L circuit,

0108It is based on the phase comparison detection profit of the phase comparison profit detector circuit, and is loop Interest of a P L L circuit. It is based on the incorrect synchronous detection result of the control circuit which controls profit, and the above-mentioned incorrect synchronous detector circuit, and is grade. It further has a control circuit of at least 1 side of the control circuits which control phase mouth A operation. To P L L circuit.

0109(Composition 1 2)

0110Current amplitude of the charge pump which constitutes the above-mentioned control circuit and the P L L circuit concerned, roux either [ at least ] the transfer function of Pfilter or the control profits of V C O -- change -- To -- things; The above-mentioned composition 1 which consists of composition which controls the loop gain of a P L L circuit P L L circuit of 1.

0111(Composition 1 3)

0112as opposed to an input data signal -- discernment timing signal for identifying the data It can set in the P L L circuit for making phase relation into predetermined phase relation. Input data signal Phase ratio which detects the phase comparison profit at the time of comparing the phase between discernment timing signals It is a Comparative gain detecting method,

0113Phase of The 1 which detects the phase relation between an input data signal and a discernment timing signal Comparison stage,

0114The phase relation between an input data signal and a discernment timing signal is shifted in the specified quantity. Phase relation shift step story,

0115The input data signal and discernment timing Trust which were shifted by the phase relation shifting means Phase comparison stage of The 2 which detects the phase relation between items,

0116The difference and above-mentioned phase relation Si of an output value who are obtained by each of the 1st and the phase comparison phase of The 2 Based on the specified quantity to which phase relation is shifted, a phase comparison profit is detected in a Bud stage. Phase comparison profit detecting method which consists of a phase comparison profit detection stage.

0117(Composition 1 4)

0118The above-mentioned composition 1 In the phase comparison detecting method of 3,

0119In the 1st phase comparison method, the input data signal and the discernment timing signal abbreviated-synchronized. The phase relation between both of a state is detected,

0120In the 2nd phase comparison phase, the input data signal and the discernment timing signal abbreviated-synchronized. Phase of composition of detecting the phase relation between both in the state where it shifted from the state in the specified quantity Comparison detecting method.

0121(Composition 1 5)

0122as opposed to the input data signal with which data changes a predetermined cycle -- the data -- To identify It can set in the P L L circuit for making phase relation of the discernment timing signal of a To sake into predetermined phase relation. When comparing the phase between an input data signal and a discernment timing signal It is a phase comparison profit detecting method which detects a phase comparison profit,

0123The data discernment output of the data identification part which identifies the data of an input data signal, Data Therefore, it is the OFF of the data of an input data signal to shift discernment timing in the specified quantity [ of The 1 ]. The data correlation of Listen with the data discernment output of a change primary detecting element which carries out Replacement detection is detected. Phase comparison stage of The 1 which compares both phase by things,

0124The data discernment output of the above-mentioned data identification part, and data Identification in the above-mentioned change primary detecting element Data phase between the data discernment outputs at the time of the ability to shift another timing in the specified quantity [ of The 2 ] further Phase comparison stage of The 2 which compares both phase by detecting Seki, The 1st and the Difference above-mentioned discernment tie of the comparison output value in each of the phase comparison stage of The 2 Phase comparison Gain check which detects a phase comparison profit based on the specified quantity of The 2 which shifts ming Phase comparison profit detecting method which consists of an appearance stage.

0125(Composition 1 6).

0126as opposed to an input data signal -- discernment timing signal for identifying the data It can set in the P L L circuit for making phase relation into predetermined phase relation. Input data signal Phase ratio which detects the phase comparison profit at the time of comparing the phase between discernment timing signals It is a Comparative gain detecting method,

0127It is [ the data of an input data signal, and ] the above-mentioned discernment timing signal about an input data signal. It is To detect about the data correlation between the data of the obtained discernment output by carrying out Identification. Phase comparison stage of The 1 which compares a phase by To,

0128It is [ the data of an input data signal, and ] discernment of the above-mentioned discernment timing signal about an input data signal. It was obtained by discriminating from timing to the timing which was able to shift the specified quantity. About that of The 2 which compares a phase by About which detects the data correlation between the data of a discernment output Phase comparison stage,

0129The difference and the above-mentioned discernment Timing of a comparison output in each of the 1st and the phase comparison phase of The 2 To the extent that a phase comparison profit is detected based on the specified quantity which shifts the discernment timing of a Tongue signal Phase comparison profit detecting method which consists of a phase comparison profit detection stage.

0130(Composition 1 7)

0131as opposed to an input data signal -- the discernment timing signal for identifying the data -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronization detection method for detecting a term.

0132Phase of The 1 which detects the phase relation between an input data signal and a discernment timing signal Comparison stage,

0133The phase relation between an input data signal and a discernment timing signal is shifted in the specified quantity. Phase relation shift step story,

0134The input data signal and discernment timing Trust which were shifted by the phase relation shifting means Phase comparison stage of The 2 which detects the phase relation between items,

0135It is based on the difference of each output in the 1st and the phase comparison phase of The 2, and is an incorrect synchronous state. Incorrect synchronization detection method of composition of detecting.

0136(Composition 1 8)

0137as opposed to an input data signal -- the discernment timing signal for identifying the data -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronization detection method for detecting a term.

0138data discernment appearance of the data identification part which identifies the data of an input data signal When Data Therefore, it is the OFF of the data of an input data signal to shift discernment timing in the specified quantity [ of The 1 ]. The data correlation between the data discernment outputs of a change primary detecting element which carry out Replacement detection is detected. Phase comparison stage of The 1 which compares both phase by things,

0139The data discernment output of the above-mentioned data identification part, and data Identification in the above-mentioned change primary detecting element Data phase between the data discernment outputs at the time of the ability to shift another timing in the specified quantity [ of The 2 ] further Phase comparison stage of The 2 which compares both phase by detecting Seki, It is based on the difference of the output in each of the 1st and the phase comparison phase of The 2, and is an incorrect synchronous state. P T/JP2002/011319

014020

0141An incorrect synchronization detection method which consists of an incorrect synchronous detection stage to detect.

0142(Composition 1 9)

0143as opposed to an input data signal -- the data is identified Because -- a discernment timing signal -- said -- in the P L L circuit made to expect -- between an input data signal and discernment timing signals -- incorrect -- said -- It is an incorrect synchronous detector circuit for detecting a term.

0144It is [ the data of an input data signal, and ] the above-mentioned discernment timing signal about an input data signal. Correlation between the data of the discernment output obtained by carrying out Identification is detected. 1st phase comparison phase that compares a phase,

0145It is [ the data of an input data signal, and ] discernment of the above-mentioned discernment timing signal about an input data signal. It was obtained by discriminating from timing to the timing which was able to shift the specified quantity. Phase comparison of The 2 which compares a phase by detecting correlation between the data of a discernment output Stage,

0146It is based on the difference of the output in each of the 1st and the phase comparison phase of The 2, and is an incorrect synchronous state. Incorrect synchronization detection method which consists of an incorrect synchronous detection stage to detect.