Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit

The present invention relates to a phase comparison gain detection circuit, a false synchronization detection circuit, and a PLL circuit, and is particularly applicable to a PLL circuit that can be applied when a reference clock signal is extracted from received data in an optical transmitter / receiver for optical communication, and an application thereof. It relates to a phase-locked gain detection circuit which can be performed, and a false synchronization detection circuit.

FIG. 1A shows a general configuration of a clock extraction PLL circuit. In the same configuration, the phase difference between the clock signal CL, which is the output of the VCO (voltage controlled oscillator circuit) 40, and the input data DA is detected by the phase comparator 10, and the charge pump 20 is charged according to the detected output. As a result, a current proportional to the output of the phase comparator is supplied to the loop filter 30. Then, the supply current is smoothed by the loop filter 30, and the result is fed back to the VCO 40. FIG. 1B is a circuit diagram showing an example of the configuration of the loop filter 30. As shown in the figure, in the case of this example, the loop filter 30 is composed of a series circuit of the resistor R and the capacitor C, and has a function of smoothing the input current and converting it into an output voltage. By the above-mentioned operation, the PLL circuit can obtain the clock signal CL synchronized with the input data signal DA. Here, when the phase comparison gain in the phase comparator 10 is Kp, the current amplitude in the charge pump 20 is Ic, the transfer function of the loop filter 30 is F (s), and the VCO gain is Kv, the loop gain of the PLL circuit is It is expressed by the well-known formula below. Open loop gain = [Kp Ic F (s) Kv] / s Closed loop gain = φin / φout = [Kp Ic F (s) Kv] / [s + Kp Ic F (s) Kv]

Also, when a complete next-order loop filter is used, open-loop gain = [Kp Ic R Kv / s] [1 + 1 / sCR]

Closed loop gain = [Kp Ic R Kv (1 + sCR)] / [s ^ 2 CR + Kp Ic R Kv (1 + sCR)]

Each loop gain of is obtained. From the above equation, it can be seen that the cutoff frequency of the closed loop gain is the frequency at which the open loop gain becomes 0 dB, and is proportional to the gains of the phase comparator 10, the charge pump 20, and the VCO 40 (see Fig. 2A). Here, when the gain of each part is large, this cutoff frequency tends to be high, and as a result, the output jitter tends to increase. On the other hand, when these gains are small (see FIG. 2B), the cutoff frequency tends to be low, resulting in a decrease in phase margin and an increase in peaking. In that case, the phase error response tends to be poor. Here, the closed-loop characteristic as the jitter characteristic of the PLL corresponds to the so-called jitter transfer, and is represented by the amplification factor of the output jitter with respect to the input jitter in the locked state of the PLL. This value is better as the response speed of the PLL is slower. On the other hand, from the viewpoint of so-called jitter tolerance, which is an index of how much jitter can be tolerated when the PLL is locked, on the contrary, the faster the response speed of the PLL, the greater the yield strength. Therefore, the two are in a trade-off relationship with each other. FIG. 3 is a block diagram showing an example of an identification timing signal extraction circuit to which the PLL method is applied. The data of the input data signal DA is extracted by the identification circuit 100 by the clock signal CL extracted by the PLL circuit function as described above. In the PLL circuit in such an optical transmission / reception circuit or the like, unlike the PLL circuit used in a general frequency synthesizer, random data is input as an input data signal. Therefore, when the frequency fluctuation of the input signal is large, the level of the frequency component value to be extracted is relatively lowered, and as a result, the PLL loop gain is lowered and the operation becomes unstable. FIG. 4 shows a circuit example when a well-known half-rate clock Bang-Bang circuit is applied as the phase comparison circuit 10. In the figure, for the input data signal DA, the data identification clock signal CL and the edge detection clock signal CL delayed by π / 2 phase are used in two D-FF (D-flip-flop) circuits. Data identification operation is performed by'and. Then, the exclusive OR circuit ExOR performs an exclusive OR operation on each of the resulting signals Da and Db to obtain the signal Dc. As a result, when the phase of the data signal DA is delayed with respect to the phase of the identification clock signal CL, the exclusive theory sum output Dc becomes an intermittent signal probabilistically, as shown in FIG. 6, while the data If the phase of the signal DA is advanced with respect to the phase of the identification clock signal CL, the exclusive theory sum output Dc is likely to be a continuous signal, as shown in FIG. As a result, the level of the signal obtained through the low-pass filter by the charge pump 20 and the loop filter 30 with respect to such a phase comparison result is low when the phase comparison output is an intermittent signal as shown in FIG. On the other hand, in the case of a phase comparison output that is likely to be continuous as in the case of FIG. 7, the output level of the low-pass filter is high. The oscillation frequency of the VCO40 is controlled according to the output level of this low-pass filter. That is, when the phase of the data signal is delayed, the VOC input level is lowered, and as a result, the VCO oscillation frequency is lowered, which acts to delay the phase of the clock signal CL according to the phase of the data signal. On the contrary, when the phase of the data signal is advanced, the VCO oscillation frequency rises, and it acts to advance the phase of the clock signal with respect to the data signal. Here, in the case of FIG. 6, when the sign of the data of system A in the input data signal changes, the H signal having 1/4 period of the clock signal is output in the phase comparison output. On the other hand, if the codes of the A system data are continuous, the H signal will not be output during that time. This situation is shown in FIGS. 8 to 10. Further, in the case of FIG. 7, that is, when the phase of the data signal is advanced, the exclusive OR between the same data does not occur as shown in FIG. 7, so that the H signal is statistically used as the phase comparison output. The L signal will be generated in half. However, in both the A system and the B system, the L signal is output when the same code is continuous, and the H signal is output when the repetition of different codes continues. This situation is shown in FIGS. 11 to 13. In this way, the phase comparison output is not necessarily affected by the phase difference between the data signal and the clock signal, but also by the content of the data signal itself (in this case, the so-called edge ratio, duty, etc.). As a result, the gain Kp of the phase comparator 10 fluctuates, and thus the loop gain of the entire PLL circuit also fluctuates. 14A and 14B show an example of the output waveform of the phase comparator 10 having the configuration as shown in FIG. As shown in Fig. 14A, the ideal output characteristics shown by the broken line are actually curved as shown by the solid line due to the influence of input jitter and the setup hold operation characteristics of the D-FF circuit in the phase comparison circuit. Occurs. Further, as shown in FIG. 14B, the waveform becomes blunt due to the edge ratio of the input data. As a result, the loop gain of the PLL circuit fluctuates, which causes the circuit operation instability as described above.

In view of the above problems, it is an object of the present invention to provide a PLL circuit capable of providing stable PLL circuit operation regardless of fluctuations in the edge ratio of input data, fluctuations in duty, etc., and the influence of circuit characteristics. In the present invention, a plurality of phase comparison operations are performed with different phase conditions for the identification of the input data signal, and the phase comparison gain is detected by comparing the phase comparison results of each. Therefore, it is possible to detect the on-time phase comparison gain in consideration of the fluctuation factors of the phase comparison gain such as the edge ratio and duty of the input data signal and the setup / hold characteristics of the classifier. As a result, on-time and accurate loop gain compensation control can be realized by controlling the loop gain of the PLL circuit based on the phase comparison detection result.

FIGS. 1A and 1B are diagrams showing the configuration of a conventional PLL circuit. 2A and 2B are explanatory views of the loop gain of the PLL circuit. FIG. 3 is an operation explanatory diagram of a conventional PLL circuit. FIG. 4 is a diagram showing a circuit example of a conventional half-rate clock Bang-Bang phase comparator. FIG. 5 is a diagram for explaining the data identification phase. FIG. 6 is a time chart (No. 1) of each signal in the circuit of FIG. FIG. 7 is a time chart (No. 2) of each signal in the circuit of FIG. FIG. 8 is a time chart (No. 3) of each signal in the circuit of FIG. FIG. 9 is a time chart (No. 4) of each signal in the circuit of FIG. FIG. 10 is a time chart (No. 5) of each signal in the circuit of FIG. FIG. 11 is a time chart (No. 6) of each signal in the circuit of FIG. FIG. 12 is a time chart (No. 7) of each signal in the circuit of FIG. FIG. 13 is a time chart (No. 8) of each signal in the circuit of FIG. 14A and 14B are diagrams (No. 1) for explaining the deterioration state of the phase comparison characteristics. FIG. 15 is a circuit block diagram of an example of a PLL circuit with a phase comparison gain compensation function. FIG. 16 is a circuit diagram showing an example of a phase comparison gain detection circuit. FIG. 17 is a diagram (No. 2) for explaining the deterioration state of the phase comparison characteristic. FIG. 18 is a block diagram of an embodiment of the present invention. FIG. 19 is a diagram for explaining the phase comparison gain detection principle according to the configuration shown in FIG. FIG. 20 is a circuit diagram of an embodiment of the present invention. FIG. 21 is a time chart of each signal in the circuit shown in FIG. FIG. 22 is a diagram for explaining the phase comparison gain detection principle according to the configuration shown in FIG. FIG. 23 is a block diagram of a PLL circuit according to an embodiment of the present invention using the phase comparison detection circuit having the configuration shown in FIG. FIG. 24 is a circuit diagram of a phase comparison gain detection circuit according to another embodiment of the present invention. FIG. 25 is a diagram for explaining the phase comparison gain detection principle according to the configuration shown in FIG. 24. FIG. 26 is a circuit diagram of an erroneous synchronization detection circuit according to still another embodiment of the present invention. FIG. 27 is a diagram for explaining the erroneous synchronization detection principle according to the configuration shown in FIG. 26.<u style="single">Description of preferred examples</u> The configuration of the examples of the present invention will be described below together with the drawings. Assuming that the gain change of the PLL circuit (for example, the circuit shown in FIG. 15) as described above is compensated by detecting the gain of VCO40, the gain of the phase comparator 10 is detected by the edge ratio of the data DA, and the detection result is obtained. It is conceivable to adjust the output current of the charge pump 20 based on the above, or adjust the capacitance value or the resistance value of the filter 30 to compensate. In the case of FIG. 15, the phase comparison gain circuit 210 detects the gain of the phase comparison notation 10, and the control circuit 220 controls the characteristics of the charge pump based on the detection result. In this case, in the case of a phase comparator having saw-wave phase comparison characteristics (see FIG. 17) such as the well-known Hogge phase comparator as shown in FIG. 16, the phase period is a fixed value. , The output amplitude determines the gain. Then, in the phase comparison gain compensation circuit as shown in FIG. 15, the fluctuation of the amplitude due to the fluctuation of the edge ratio of the data is detected. That is, in this case, the output of the EXOR circuit 213 is "H" when the data has an edge, that is, when the data changes, and "L" when there is no data. The edge ratio of data can be detected by averaging this with LPF (circuit by R, C). Then, the control circuit 220 compensates for the fluctuation of the output amplitude of the phase detector by adjusting the current of the charge pump 20. On the other hand, when applying the well-known Bnag-Bang phase comparator, which requires a small number of components because the classifier and frequency divider can be configured as a part of the phase comparator, the phase comparison characteristic is stepped in this phase comparator. It is represented by a function (Bang-Bang phase comparison characteristic) (for example, the characteristic of the broken line in FIG. 14A), and has a characteristic that the phase comparison gain value is determined according to the stochastic fluctuation of the phase comparator output. In this case, as the fluctuation factors of the phase comparison gain, in addition to the fluctuation of the edge ratio of the data, 1 input data jitter, 2 input data duty, and 3 classifier (FF) in the phase comparator. There are variations and fluctuations in the setup / hold characteristics of the above. Therefore, in this case, the design for the phase comparison gain is more complicated than in the cases shown in FIGS. 16 and 17, and it is necessary to adjust the loop gain of the entire PLL including the phase comparison gain after incorporating the phase comparison circuit in the corresponding system. There is. Therefore, in the present invention, in the PLL circuit provided with the above-mentioned Bang-Bang phase comparator and the like, the jitter of these input data, the duty of the input data, the variation of the setup / hold characteristics of the phase comparator classifier (FF), and the variation Provided is a circuit that accurately detects fluctuations in phase comparison gain due to fluctuations and the like. FIG. 18 is a principle diagram of an embodiment of the present invention. The figure shows a phase comparison gain detector using the above Bang-Bang phase comparator. As shown in the figure, the phase comparison detector 300 outputs the phase comparator 311, which inputs the clock signal CL for identifying the data DA, and the data identification clock signal CL with a delay of a predetermined time as the clock signal CL'. It is composed of a delay device 313, a phase comparator 312 that takes this delay clock signal CL'as an input, LPF 314, 315 that smoothes the output, and a difference voltage detection circuit 316. In the circuit shown in the figure, while the data signal DA and the clock signal CL are synchronized, that is, when the input data identification clock is synchronized, the data identification operation is performed by two clock signals CL and CL'of different phases, respectively. The desired phase comparison gain is detected from the time difference between the phase comparator outputs D1 and D2 of the above and the clock signals CL and CL', that is, the predetermined delay time. As a result, even if there are setup / hold times of the phase comparator, edge ratio and jitter of the input data, duty fluctuations, variations, etc., the phase comparison gain in which these are incorporated can be detected. By controlling based on the detection output, the loop gain of the entire PLL circuit can be compensated to be constant. Therefore, it is possible to provide a PLL circuit in which stable response characteristics can be obtained and the desired jitter transfer characteristics are satisfied. FIG. 19 shows the output levels of the phase comparators 311, 312 for explaining the principle of the embodiment of the present invention, and the phase comparison characteristics in the figure correspond to those shown in FIGS. 14A and 14B. As shown in the figure, the phase comparison output changes according to the phase difference as the phase comparison result, and the rate of change, that is, ΔV / (Δt / T) corresponds to the phase comparison gain Kp. In the above equation, ΔV is the difference voltage between the smoothed values D1 and D2 of the phase comparison outputs under different phase conditions, and Δt is the amount of delay by the delay device 313 that provides the difference in the phase conditions. , T indicate the signal period of the clock signal. FIG. 20 shows a configuration of a phase comparison detection circuit according to an embodiment of the present invention, which further embodies the configuration of FIG. This circuit is a phase comparison gain detection circuit that applies a Bang-Bang phase comparator that uses a half-rate clock. As shown in the figure, the circuit is provided with data identification classifiers 411 and 412, data edge detection classifier 413, and phase comparison gain detection classifier 414 as classifiers (FF), and is further exclusive. As a logic sum circuit (EXOR), a circuit 431 that takes the logic of the data identification FF output DOa and the data edge detection FF output DOc, and a circuit 432 that takes the logic of the data identification FF output DOb and the data edge detection FF output DOc. , A circuit 433 that takes the logic of the data identification FF output DOb and the phase comparison gain detection FF output DOd is provided. Then, these outputs are smoothed by LPF441,442,443 and output as phase comparison outputs Ph1, Ph2, Ph3, respectively. In the circuit of FIG. 20, as shown in the waveform diagram of FIG. 21, in a state where the data signal DA and the clock signal CL are synchronized, the data of system A is obtained as the output DOa of the classifier 411 and is identified. The data of system B can be obtained as the output DOb of the device 412. On the other hand, as the output DOc of the edge detection classifier 413, since the rising timing of the clock signal coincides with the change point of the data signal DA, the probability that the data of the A system can be obtained and the data of the B system can be obtained by the above timing. Equal to the probability. On the other hand, as for the output of the phase comparison gain detection classifier 414, since the rising timing of the clock signal is slightly delayed from the change point of the data signal DA, the probability that the data of system A can be obtained by the above timing is higher than the probability that the data of system A is obtained. The probability of getting data is greater. As a result, as a result of the exclusive OR between these data, the probability of H level appearing at output Ph1 of EXOR circuit 441 is approximately equal to the probability of H level appearing at output Ph2 of EXOR442. On the other hand, at the output Ph3 of the EXOR circuit 443, the probability of appearance of the H level is higher than that of each of the former. That is, the probability that the inputs DOa and DOd of the EXOR circuit 443 match is the probability that the inputs DOa and DOc of the EXOR circuit 441 match, or the probability that the inputs of the EXOR circuit 442 DOb and DOc match. Because it is lower. This is because, as described above, the appearance probability of the A system data in the signal DOd is smaller than the appearance probability of the A system data in the signal DOc, and similarly, the A system data in the signal DOd is smaller than the appearance probability of the B system data in the signal DOc. This is because the probability of appearance of is smaller. As described above, in this embodiment, the clock signal CLb intentionally delayed by Δt for a predetermined time is generated to perform data identification, and the identification result data and the identification identified by the clock CL not delayed by Δt t. Exclusively with the resulting data. Further, an exclusive OR is taken between the identification result data in which the data is identified by the edge detection clock signal CLa and the identification result data identified by the clock CL which is not delayed by Δt. Then, the result of these two types of exclusive OR is smoothed by LPF, and the level difference is divided by the phase standardized by the period T to obtain the phase comparison gain Kp. That is, here, after the synchronization is established, a delay amount Δt is intentionally generated to generate a clock signal (signal CLb in the examples of FIGS. 20 and 21) that is pseudo-synchronized with the data signal DA, and the pseudo-synchronization deviation is generated. The same data signal DA is identified by the clock signal. Then, the exclusive OR output between the identification data obtained there and the data identified by the π / 2 delayed clock signal CLa is smoothed to obtain a "pseudo-synchronous shift" phase comparison detection value. Then, with respect to this pseudo-synchronous phase shift detection value, the exclusive OR between the identification data identified by the clock signal CL in the synchronized state and the data identified by the clock signal CLa also delayed by π / 2 The value obtained by smoothing the output, that is, the "synchronous phase comparison detection value" is compared. It can be said that the larger the difference in the comparison results, the higher the phase comparison detection sensitivity with respect to the phase difference between the data signal DA and the clock signal CL, which is synonymous with the higher phase comparison gain. In this way, in this embodiment, the phase comparison gain in which the edge ratio, duty, setup / hold characteristics of each detector (FF), etc. at the present time are all incorporated is obtained, so that the phase comparison gain is turned on very accurately. It is possible to obtain an effective phase comparison gain of time. FIG. 23 shows an example of a PLL circuit having a phase comparison gain compensation function according to an embodiment of the present invention, and shows a difference voltage between the phase comparison outputs Ph1 and Ph3 of the phase comparator detection circuit 400 having the configuration of FIG. Is compared with the A / D converter 510 that converts the digital signal into a digital signal, the digital difference voltage is compared with a predetermined reference value, and the output current of the charge pump is adjusted based on the comparison result, so that the loop gain of the PLL circuit is obtained. Has a configuration to compensate for. Further, in the configuration of FIG. 23, the data outputs DOa and DOb of the phase comparison detection circuit 400 shown in FIG. 20 can be used as they are as the reproduced data of the input data. That is, these data outputs DOa and DOb correspond to the outputs of the identification circuit 100 in FIG. That is, in the PLL circuit of FIG. 23, the loop gain of the PLL circuit is controlled based on the phase comparison output difference voltage between the "pseudo-synchronous deviation" identification signal and the "synchronous" identification signal obtained by the phase comparison detection circuit 400. Therefore, it is possible to provide a PLL circuit having an accurate loop gain compensation function in consideration of the characteristics of the input signal and the characteristics of the phase comparison circuit at the present time. Not limited to the circuit configuration shown in FIG. 23, the control circuit 520 determines the transfer function F (s) of the filter 30 and the gain Kv of the VCO 40, which are the determinants of the loop gain of the PLL circuit other than the output current amplitude 1c of the charge pump. Needless to say, the configuration may be controlled to compensate for the loop gain of the PLL circuit. In the above-described embodiment, the Bang-Bang phase comparator using a half-rate clock is applied in the phase comparison detection circuit 400, but in addition to this, the phase comparison characteristic using a full-rate clock is serrated (FIG. 25). It is also possible to apply the present invention to the phase comparator (see). FIG. 24 shows a circuit configuration example of the phase comparison detection circuit in that case. In the circuit of the figure, the discriminator 611 that identifies the data signal DA at the timing of the clock signal CL and the data signal DA are identified at the timing of the delayed clock signal CL'in which the clock signal CL is delayed by a predetermined amount by the delay device 622. A classifier 612 is provided. Then, EXOR631,632 for exclusive-ORing the identification outputs DO1 and DO2 by these classifiers 611 and 612 with the data signal DA is provided, and a low-pass filter 641,642 for smoothing the outputs of these EXOR631,632 is provided. .. According to the phase comparison detection circuit of FIG. 24, as in the case of FIG. 20, the difference between the identification result signals DO1 and DO2 due to the phase difference of the identification clock signals CL and CL'is determined between the identification result signals DO1 and DO2 and the original data. It is detected by performing an exclusive OR operation with the signal DA and smoothing the EXOR operation results to obtain the difference. FIG. 25 is a diagram for explaining the difference voltage obtained in that case. The difference voltage ΔV between the outputs Ph1'and Ph2'of the LPF641,642 detected here is divided by Δt / T, which represents the delay phase amount whose delay amount Δt by the delay device 622 is standardized by the period T. As a result, Kp, which is the phase comparison gain, is obtained (see the equation below). Kp = ΔV / (Δt / T) Based on the phase comparison detection value obtained in this way, the control circuit 520 shown in FIG. 23 adjusts and controls the loop gain determinant parameters such as the current amplitude value Ic of the charge pump 20. This compensates for the loop gain of the PLL circuit. In this case, as compared with the example of FIG. 16, the phase comparison gain can be compensated even when there is a gain fluctuation due to a factor other than the edge ratio of the input data. Further, the phase comparator may have another configuration, and a phase detection circuit having a circuit configuration similar to that of the phase comparator, which has a function of delaying or advancing the phase of the clock signal CL or the phase of the input data signal DA by a predetermined amount. It may be incorporated to form a PLL circuit. As described above, according to the present invention, in order to compensate the phase comparison gain according to the fluctuation / variation of the phase comparator of the PLL circuit, the jitter of the input data, etc., it is possible to keep the loop gain of the PLL accurately and constant. It is possible and the jitter frequency characteristics can be stabilized, so that the performance of the PLL circuit can be improved. 26 and 27 are diagrams for explaining the erroneous synchronization detection device according to another embodiment of the present invention. FIG. 26 is substantially the same as the circuit configuration of FIG. 18, and the corresponding components are designated by the same reference numerals and duplicate explanations are omitted. In this case, it is assumed that the phase comparator of the PLL circuit has sawtooth characteristics as shown by the broken line in FIG. 27. That is, it has a characteristic that the detected voltage output according to the detected phase difference changes in a sawtooth shape according to the detected phase difference. In such a PLL circuit, by applying a phase lock at the middle part of the rising lamp part of the sawtooth wave, that is, the point P in the figure, the central part between the signal change points of the input data signal DA, that is, the center of the eye pattern The phase of the clock signal CL can be locked so that the data can be identified at the timing of the part (see Fig. 5). However, in reality, the sawtooth characteristics may be distorted as shown by the solid line in FIG. 27 due to fluctuations in the duty of the input data signal DA. In that case, in the PLL circuit, the phase lock may be erroneously applied at the Q point in FIG. 27. In this case, erroneous synchronization occurs, and the clock signal performs data identification at the timing of the cross point of the data eye pattern, and there is a high possibility that the identification data becomes erroneous. In order to prevent such erroneous synchronization, in the erroneous synchronization detection device according to another embodiment of the present invention, as described with reference to FIGS. 20 to 25, for example, the phase comparison detection output of the phase comparator is generated by the delay device 313,622. It changes depending on the amount of delay Δt given. However, the amount of change has a characteristic that depends on the absolute phase between the data signal DA and the clock signal CL. That is, when the phase difference between the data signal DA and the clock signal CL is near zero, that is, when the data is identified at the timing of the center of the eye pattern of the data signal DA (see FIG. 5), the data can be correctly identified. , The exclusive logical sum result of the identification signal and the data signal DA is substantially proportional to the delay amount even if the data identification timing is delayed by the delay device 313 as long as the delay amount Δt is smaller than the period T to some extent. Only the difference is made. On the contrary, when the cross point timing of the eye pattern, that is, the data is identified when the value of the data signal DA is indefinite, the possibility of identifying the correct data is about 50%. On the other hand, if the predetermined amount Δt is delayed from that timing and the delay amount Δt exceeds the indefinite state (dead zone) and is large enough to be the identification timing at which data identification can be performed substantially accurately, the possibility of correct data identification is high. It will be close to 100%. As a result, the identification result based on such identification timing is significantly different from the identification result when there is no delay (that is, when the identification rate is about 50% in an indefinite state), and the difference is near the center of the above eye pattern. It is considerably larger than the case of identification in. To explain this point again with FIG. 27, in the case of data identification near the center of the eye pattern, that is, in the case of point P in the same figure, the phase comparison outputs with and without delay are D1 and D2, respectively, and the difference is It is ΔV. On the other hand, in the case of the vicinity of the cross point of the eye pattern, that is, in the case of the Q point, the phase comparison outputs with and without delay are D1'and D2', respectively, and the difference is ΔV'. Obviously as shown ΔV &lt;ΔV'. Therefore, erroneous synchronization can be detected by detecting that ΔV becomes larger than a predetermined reference value. It should be noted that the present invention is not limited to the above examples, and various modifications according to the basic idea of the present invention can be implemented, and it goes without saying that these modifications are also included in the scope of the present invention. The present invention includes the following configurations. (Structure 1) Compare the phases between the input data signal and the identification timing signal in the PLL circuit for making the phase relationship of the identification timing signal for identifying the data with respect to the input data signal a predetermined phase relationship. It is a phase comparison gain detection circuit that detects the phase comparison gain at the time, and is a first phase comparison means for detecting the phase relationship between the input data signal and the identification timing signal, and the input data signal and the identification timing signal. A phase relationship shifting means for shifting the phase relationship between them by a predetermined amount, a second phase comparison means for detecting the phase relationship between the input data signal shifted by the phase relationship shifting means and the identification timing signal, and a second phase comparison means. Phase comparison gain detection including phase comparison gain detection means that detects phase comparison gain based on the difference between the outputs of the first and second phase comparison means and a predetermined amount by which the phase relationship shift means shifts the phase relationship. circuit. (Structure 2) In the phase comparison gain detection circuit of the above configuration 1, the first phase comparison means detects the phase relationship between the input data signal and the identification timing signal in a substantially synchronized state, and performs a second phase comparison. The means is a phase comparison gain detection circuit having a configuration that detects the phase relationship between the input data signal and the identification timing signal when they are shifted by a predetermined amount from the substantially synchronized state. (Structure 3) The input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data to the predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle. It is a phase comparison gain detection circuit that detects the phase comparison gain when comparing the phases between them. Between the data identification output of the data identification unit that identifies the data of the input data signal and the data identification output of the switching detection unit that detects the switching of the data of the input data signal by shifting the data identification timing by the first predetermined amount. When the first phase comparison means for comparing the phases of the two by detecting the data correlation, the data identification output of the data identification unit, and the data identification timing of the switching detection unit are further shifted by a second predetermined amount. The difference between the outputs of the second phase comparison means for comparing the phases of the two by detecting the data correlation with the data identification output and the outputs of the first and second phase comparison means and the identification timing are shifted. A phase comparison gain detection circuit comprising a phase comparison gain detecting means for detecting a phase comparison gain based on a predetermined amount of 2. (Structure 4) Compare the phases between the input data signal and the identification timing signal in the PLL circuit for making the phase relationship of the identification timing signal for identifying the data into a predetermined phase relationship with respect to the input data signal. It is a phase comparison gain detection circuit that detects the phase comparison gain at the time. A first phase comparison means for comparing phases by detecting a data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal by the identification timing signal. The phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing deviated from the identification timing of the identification timing signal by a predetermined amount. Phase comparison gain that detects the phase comparison gain based on the difference between the outputs of the second phase comparison means and the first and second phase comparison means and a predetermined amount that shifts the identification timing of the identification timing signal. A phase comparison gain detection circuit consisting of a detection means. (Structure 5) The phase comparison gain detection circuit of the above configuration 3 or 4 having a configuration realized by exclusive OR operation for data correlation detection between data in the first and second phase comparison means. (Structure 6) The phase comparison gain detection circuit of the above configuration 5 having a configuration in which the exclusive OR output is smoothed and input to the phase comparison gain detection means. (Structure 7) A phase comparison gain detection circuit according to any one of the above configurations 3 to 6, wherein each data identification is performed by a flip-flop circuit. (Structure 8) An erroneous synchronization detection circuit for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with an input data signal. The first phase comparison means for detecting the phase relationship between the input data signal and the identification timing signal, and the phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount. Based on the difference in output between the second phase comparison means that detects the phase relationship between the input data signal shifted by the phase relationship shift means and the identification timing signal, and the outputs of the first and second phase comparison means. An erroneous synchronization detection circuit configured to detect an erroneous synchronization state. (Structure 9) An erroneous synchronization detection circuit for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with an input data signal. hand, Between the data identification output of the data identification unit that identifies the data of the input data signal and the data identification output of the switching detection unit that detects the switching of the data of the input data signal by shifting the data identification timing by the first predetermined amount. When the first phase comparison means for comparing the phases of the two by detecting the data correlation, the data identification output of the data identification unit, and the data identification timing of the switching detection unit are further shifted by a second predetermined amount. A missynchronization state is determined based on the difference between the outputs of the second phase comparison means that compares the phases of the two by detecting the data correlation with the data identification output and the outputs of the first and second phase comparison means. An erroneous synchronization detection circuit that serves as an erroneous synchronization detection means for detection. (Structure 10) An erroneous synchronization detection circuit for detecting erroneous synchronization between an input data signal and an erroneous timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with an input data signal. The first phase comparison means for comparing the phases by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal by the identification timing signal. , The phase is determined by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing deviated from the identification timing of the identification timing signal by a predetermined amount. An erroneous synchronization detection circuit comprising a second phase comparison means for comparison and a erroneous synchronization detection means for detecting an erroneous synchronization state based on the difference in output between the first and second phase comparison means. (Structure 11) A PLL circuit including at least one of the phase-locked loop detection circuit according to any one of the above configurations 1 to 7 and the false synchronization detection circuit according to any one of the above configurations 8 to 11. A control circuit that controls the loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit, and a control circuit that controls the phase lock operation based on the false synchronization detection result of the false synchronization detection circuit. A PLL circuit that further has at least one of the control circuits. (Structure 12) The control circuit has a configuration in which the loop gain of the PLL circuit is controlled by changing at least one of the current amplitude of the charge pump constituting the PLL circuit, the transfer function of the loop filter, and the control gain of the VCO. Configuration 11 PLL circuit. (Structure 13) Compare the phases between the input data signal and the identification timing signal in the PLL circuit for making the phase relationship of the identification timing signal for identifying the data with respect to the input data signal a predetermined phase relationship. This is a phase comparison gain detection method for detecting the phase comparison gain at the time, in which the first phase comparison step of detecting the phase relationship between the input data signal and the identification timing signal and the input data signal and the identification timing signal are used. A phase relationship shift step that shifts the phase relationship between them by a predetermined amount, a second phase comparison step that detects the phase relationship between the input data signal shifted by the phase relationship shift means and the identification timing signal, the first, and the first A phase comparison gain consisting of a phase comparison gain detection step that detects the phase comparison gain based on the difference in output values obtained in each of the second phase comparison steps and a predetermined amount that shifts the phase relationship in the phase relationship shift step. Detection method. (Structure 14) In the phase comparison detection method of the above configuration 13, in the first phase comparison method, the phase relationship between the input data signal and the identification timing signal in a substantially synchronized state is detected, and the second phase comparison step is performed. Is a phase comparison detection method having a configuration in which the phase relationship between the input data signal and the identification timing signal is detected in a state in which the input data signal and the identification timing signal are substantially synchronized to a state in which the identification timing signal is shifted by a predetermined amount. (Structure 15) The input data signal and the identification timing signal in the PLL circuit for making the phase relationship of the identification timing signal for identifying the data a predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle. It is a phase comparison gain detection method that detects the phase comparison gain when comparing the phases between them, and shifts the data identification output of the data identification unit that identifies the data of the input data signal and the data identification timing by a first predetermined amount. Therefore, the first phase comparison step of comparing the phases of the two by detecting the data correlation with the data identification output of the switching detection unit that detects the switching of the data of the input data signal, The phase of both is compared by detecting the data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount. A phase comparison gain detection step that detects the phase comparison gain based on the difference between the comparison output values in each of the first and second phase comparison stages and the second predetermined amount that shifts the identification timing. A phase comparison gain detection method consisting of. (Structure 16) Compare the phases between the input data signal and the identification timing signal in the PLL circuit for making the phase relationship of the identification timing signal for identifying the data with respect to the input data signal a predetermined phase relationship. This is a phase comparison gain detection method for detecting the phase comparison gain at the time, and is a data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal by the identification timing signal. The first phase comparison step, which compares the phases by detecting The phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing deviated from the identification timing of the identification timing signal by a predetermined amount. Phase comparison that detects the phase comparison gain based on the difference in the comparison output between the second phase comparison stage and the first and second phase comparison stages and a predetermined amount that shifts the identification timing of the identification timing signal. Phase comparison gain detection method consisting of a gain detection stage. (Structure 17) An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with an input data signal. A first phase comparison step for detecting the phase relationship between the input data signal and the identification timing signal, and a phase relationship shift step for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount. A second phase comparison step that detects the phase relationship between the input data signal shifted by the phase relationship shifting means and the identification timing signal, and A missynchronization detection method having a configuration in which a missynchronization state is detected based on the difference between the outputs in the first and second phase comparison stages. (Structure 18) An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with an input data signal. The data identification output of the data identification unit that identifies the data of the input data signal and the data identification output of the switching detection unit that detects the switching of the data of the input data signal by shifting the data identification timing by the first predetermined amount. The first phase comparison step of comparing the phases of the two by detecting the data correlation between them, the data identification output of the data identification unit, and the data identification timing of the switching detection unit are further shifted by a second predetermined amount. Missynchronization based on the difference in output between the second phase comparison stage, which compares the phases of the two by detecting the data correlation with the data identification output, and the first and second phase comparison stages, respectively. An erroneous synchronization detection method consisting of a erroneous synchronization detection stage for detecting a state. (Structure 19) An erroneous synchronization detection circuit for detecting erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit that synchronizes an identification timing signal for identifying the data with respect to an input data signal, and is input data. A first phase comparison step in which the phases are compared by detecting the correlation between the signal data and the identification output data obtained by identifying the input data signal by the identification timing signal, and the input data signal. The phase is compared by detecting the correlation between the data of the above and the data of the identification output obtained by identifying the input data signal at a timing deviated from the identification timing of the identification timing signal by a predetermined amount. An erroneous synchronization detection method consisting of two phase comparison stages and an erroneous synchronization detection step that detects an erroneous synchronization state based on the difference in output between the first and second phase comparison stages.