Flip-chip bonder with induction coils and a heating element

BACKGROUND

0001The present invention generally relates to a flip chip assembly apparatus employing induction coils, and more particularly to selective area heating during flip chip assembly.

0002New integrated circuit technologies include three-dimensional integrated circuits. One type of 3D integrated circuit may include two or more layers of active electronic components stacked vertically and electrically joined with through-substrate vias and solder bumps. The 3D integrated circuit may provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through-silicon-vias. The 3D integrated circuit described above may be fabricated in any number of known methods. Some 3D integrated circuits may include a silicon interposer which may be used to re-direct circuitry between a ship carrier and one or more top chips.

0003Warping or uneven heating of the components of the 3D integrated circuit during typical assembly may result in failed solder bump connections and short circuits. For example, non-wetting and bridging may be a result of warping or uneven heating. The influence warping and uneven heating has on 3D chip packaging may become more significant as the chip size increases and the component thickness decreases.

0004There are two primary methods for wetting solder bump connections: belt reflow furnaces and flip-chip bonders. A belt reflow furnace works by conveying one or more chips through one or more constant temperature ovens, in order to gradually increase the temperature to the point where the solder material can form a connection. Flip-chip bonders bond only a single chip at a time by quickly ramping up the temperature of the solder material to form connections.

BRIEF SUMMARY

0005An embodiment of the invention may include a method of forming a flip chip assembly. The method may include joining a chip to a chip carrier with a plurality of solder bumps. Joining the chip to the chip carrier may include heating the solder bumps to a temperature greater than the reflow temperature of the plurality of solder bumps using conductive heating and inductive heating.

0006Another embodiment of the invention may include a method of forming a flip chip assembly. The method may include joining a chip layer, where the chip layer includes at least a first chip and a second chip, to a chip carrier with a plurality of solder bumps. Joining the chip to the chip carrier includes heating the solder bumps to a temperature greater than the reflow temperature of the plurality of solder bumps using conductive heating and inductive heating.

0007Another embodiment of the invention may include a flip chip bonding apparatus. The flip chip bonding apparatus may contain a tool base having a first surface and a tool head having a second surface. The first surface of the tool base and the second surface of the tool head may facing each other, and the tool head may be moved with respect to the tool base. The flip chip bonding apparatus may contain a conductive heating element located in the tool head or the tool base. The flip chip bonding apparatus may contain an inductive heating element.

BRIEF DESCRIPTION OF THE SEVERAL DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a 3D integrated circuit package.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates an intermediate step in a flip chip assembly process.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates an intermediate step in a flip chip assembly process with pre-applied underfill.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a thermal compression tool used in the flip chip assembly process according to an exemplary embodiment.

<figref idref="DRAWINGS">FIG. 5</figref> is a cross section view of <figref idref="DRAWINGS">FIG. 4</figref> depicting a tool head of the thermal compression tool according to an exemplary embodiment.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates a temperature gradients, without inductive heating, of the heated chip during bonding process shown in <figref idref="DRAWINGS">FIG. 5</figref> according to an exemplary embodiment.

<figref idref="DRAWINGS">FIG. 7</figref> illustrates a chart depicting temperature versus zone of the heat profiles shown in <figref idref="DRAWINGS">FIG. 6</figref> according to an exemplary embodiment.

<figref idref="DRAWINGS">FIG. 8</figref> illustrates a temperature gradients, with inductive heating, of the heated chip during bonding process shown in <figref idref="DRAWINGS">FIG. 5</figref> according to an exemplary embodiment.

<figref idref="DRAWINGS">FIG. 9</figref> illustrates a chart depicting temperature versus zone of the heat profiles shown in <figref idref="DRAWINGS">FIG. 8</figref> according to an exemplary embodiment.

0017The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

0018Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, dimensions of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

0019Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

0020For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

0021In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

0022The present invention generally relates to flip chip assemblies, and more particularly to selectively controlling the heating of one or more regions of a chip during a flip chip assembly process. The flip chip assembly process may include multiple steps in which heating may be controlled to yield specific assembly results.

0023By way of example, <figref idref="DRAWINGS">FIG. 1</figref> illustrates a structure <b>100</b> representing a 3D integrated circuit (hereinafter “3D package”). The 3D package may include a chip carrier <b>102</b>, an interposer <b>104</b>, and at least one chip, such as a first top chip <b>105</b> and a second top chip <b>106</b>. The interposer <b>104</b> may be joined on top of the chip carrier <b>102</b> via a plurality of solder bumps <b>108</b>, while the first top chip <b>105</b> and the second top chip <b>106</b> may be joined on top of the interposer <b>104</b> via a second plurality of solder bumps <b>110</b>. The first and second plurality of solder bumps <b>108</b>, <b>110</b> may generally form connections to metalized pads (not shown) integrated into the surfaces of the chip carrier <b>102</b>, the interposer <b>104</b>, and the first top chip <b>105</b> and the second top chip <b>106</b>. The chip carrier <b>102</b> may include a silicon substrate, a glass substrate or a laminated composite. Some 3D packages may include multiple chips stacked vertically on the chip carrier with or without an interposer.

0024The interposer <b>104</b> may simply include an electrical interface which may provide connectivity between the chip carrier <b>102</b> and the first top chip <b>105</b> and the second top chip <b>106</b>. The interposer <b>104</b> may be used to spread one connection array to a wider pitch or reroute a particular connection to a different location. Like the first top chip <b>105</b> and the second top chip <b>106</b>, the interposer <b>104</b> may include semiconductor devices, such as, for example, a passive device and a field affect transistor. The first top chip <b>105</b> and the second top chip <b>106</b> may include multiple semiconductor devices joined by multiple metallization layers. The chip carrier <b>102</b>, the interposer <b>104</b>, the first top chip <b>105</b> and the second top chip <b>106</b>, all of the structure <b>100</b>, may generally and collectively be referred to as components of a 3D assembly process (hereinafter “3D assembly”).

0025The 3D assembly may include physically stacking one or more components described above and applying a temperature and a pressure to cause the solder bumps to reflow and form an electromechanical connection between the components. A thermal compression tool, such as a flip-chip bonder, may be used to apply the temperature and the pressure, and form the solder bump connections, for example, the first and second plurality of solder bumps <b>108</b>, <b>110</b>. A temperature in excess of the reflow temperature of the solder may be used to form the requisite electromechanical connection. The reflow temperatures of common lead-free solder bumps may range from about 230° C. to about 260° C., and the temperatures used in the thermal compression tool may range from about 230° C. to about 400° C. The applied temperatures of the thermal compression tool may depend on the interconnect material and chip size. A pressure ranging from about 6.0×10⁴Pa to about 6.0×10⁵Pa may be applied during the 3D assembly using the thermal compression tool, although this pressure may be adjusted based on the contact area and materials to be interconnected. In one embodiment, a force ranging from about 5 N to about 50 N may be applied. The force too may be adjusted based on the contact area and materials to be interconnected. In some cases, there may be between 20,000 and 170,000 solder bump connections between components, for example between the interposer <b>104</b> and the first top chip <b>105</b> and the second top chip <b>106</b>.

0026Now referring to <figref idref="DRAWINGS">FIG. 2</figref>, a step in the flip chip assembly of the structure <b>120</b> is shown. In this step, heat and a vertical pressure <b>132</b>, as described above, may be applied to structure <b>120</b>. This may allow for the solder bumps <b>128</b> to reflow to form a solid connection between the chip <b>124</b> and the substrate <b>122</b>. In another example embodiment, illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, an organic polymer <b>126</b> may be located between the solder bumps <b>128</b>, which may eliminate the need to add underfill material in subsequent steps by curing during the reflow of the of the solder bumps <b>128</b>.

0027Referring now to <figref idref="DRAWINGS">FIG. 4</figref>, a thermal compression tool <b>300</b> may be used to join the chip <b>204</b> to the chip carrier <b>202</b> using a plurality of solder bumps <b>206</b>. The chip carrier <b>202</b> may include a silicon substrate, a glass substrate, an organic substrate, or some combination thereof. The thermal compression tool <b>300</b> may generally include a tool base <b>302</b> and a tool head <b>304</b>. The tool base <b>302</b> and the tool head <b>304</b> may include a vacuum bias base stage with heating capabilities. The vacuum may be used to secure the components and hold them flat during a bonding sequence. Additionally, an induction coil <b>308</b> may be located on an anterior portion of the head, or located adjacent to the head. The induction coil <b>308</b> may be powered with a power source <b>320</b>. The power source <b>320</b> may receive input from temperature controller <b>322</b> to change the frequency or intensity of induction which may change the inductive heating performed. The temperature controller <b>322</b> may receive temperature reading of an outer portion of the interposer from a temperature sensor <b>324</b>, which may be a thermocouple or infrared temperature sensor. The chip <b>204</b> with the plurality of solder bumps <b>206</b> may be stacked on top of the chip carrier <b>202</b> using a pneumatic pick-and-place system, and then placed between the tool base <b>302</b> and the tool head <b>304</b>. A heat profile and a uniform vertical pressure <b>310</b> may be applied to the stack, which may cause the chip <b>204</b> to be joined to the chip carrier <b>202</b>. Preferably, the heat profile may be implemented in the tool head <b>304</b> and applied directly to the top component of the stack, for example the chip <b>204</b>. In one embodiment, the heat profile may be implemented in the tool base <b>302</b>, or both the tool head <b>304</b> and the tool base <b>302</b>.

0028Referring now to <figref idref="DRAWINGS">FIG. 5</figref> a cross section view, along section line A-A of <figref idref="DRAWINGS">FIG. 4</figref>, is shown. In the present embodiment, the tool head <b>304</b> may include at least one heat source <b>306</b> located in the tool head <b>304</b>. The heat source <b>306</b> may be distributed evenly across the tool head <b>304</b>, or may be placed in different locations of the tool head <b>304</b> based on the geometry of the heating desired. The induction coil <b>308</b> may be located separately from the tool head <b>304</b>, or additionally may be located on the outer edge of the tool head. In either instance, the induction coil should be located such that the inductive heating performed is concentrated on the solder bumps located on the outer portion of the chip <b>204</b>. The heat source <b>306</b> may include an electronic cartage heater or a hot gas supply. In one embodiment, the temperature of the heat source <b>306</b> may range from about 27° C. to about 400° C.

0029Generally, a uniform heating arrangement is applied to achieve the requisite temperatures to cause the solder bumps to transition from a solid phase to a liquid phase, or reflow, and to form the desired permanent electromechanical connection between the chip carrier <b>202</b> and the chip <b>204</b>. However, heating the chip using only conductive heat that originates from the head may lead to temperature gradients across the chip, due to the geometry and dynamics of the heating. This may account for bridging of solder in the middle of a chip, and inadequate heating at the edges of a chip. <figref idref="DRAWINGS">FIG. 6</figref> and <figref idref="DRAWINGS">FIG. 7</figref> show a representative example temperature gradient of the chip <b>204</b> during the thermal bonding process, performed only with the heat source <b>306</b> in the tool head <b>304</b>. <figref idref="DRAWINGS">FIG. 8</figref> and <figref idref="DRAWINGS">FIG. 9</figref> show a representative example temperature gradient of the chip <b>204</b> during the thermal bonding process, performed using the heat source <b>306</b> in the tool head <b>304</b> and the induction coil <b>308</b>.

0030Referring now to <figref idref="DRAWINGS">FIG. 6</figref>, a temperature gradient <b>402</b> of the chip <b>204</b> during bonding without inductive heating is depicted. <figref idref="DRAWINGS">FIG. 6</figref> is a representative example of the temperature gradient <b>402</b>, which may vary based on the placement of the heat source <b>306</b>. The temperature gradient <b>402</b> may be depicted using four temperature zones, a first zone <b>414</b>, a second zone <b>416</b>, a third zone <b>418</b>, and a fourth zone <b>420</b>. It should be noted, however, that the number of temperature zones depicted and their relative spatial relationship to one another is provided for illustrative purposes only. The relationship between the temperatures of each zone depicted in <figref idref="DRAWINGS">FIG. 6</figref> is illustrated in the chart depicted in <figref idref="DRAWINGS">FIG. 7</figref>.

0031In cases where the heat source <b>306</b> is distributed relatively uniformly, and the induction coil <b>308</b> is not used, the center, or the first zone <b>414</b>, of the temperature gradient <b>402</b> may have a first zone maximum temperature T₁about equal to or less than the set temperature of the heat source <b>306</b>. It should be noted that when the tool head <b>304</b> has uniform temperature just prior to the bonding process, the chip <b>204</b> temperature may not be uniform a during bonding, as energy may dissipate unevenly, therefore causing a temperature gradient across the chip during the bonding process. Additionally, each temperature zone may have its own maximum temperature, i.e. first zone temperature T₁, second zone temperature T₂, third zone temperature T₃, and fourth zone temperature T₄and an outer edge temperature T₅. Moreover, the first zone <b>414</b> may generally have the highest temperature of the temperature gradient <b>402</b> in such instances. In this example, the temperature may decrease as the distance from the center increases according to known principles of heat transfer, i.e. T₁>T₂>T₃>T₄>T₅. Thus, the temperature may generally decrease from the first zone <b>414</b> to the fourth zone <b>420</b>. Additionally, various factors, such as for example, tool head materials, or the size or power of the heat source <b>306</b> may affect or change the respective heat profile.

0032Referring now to <figref idref="DRAWINGS">FIG. 7</figref>, a chart <b>400</b> corresponding to the temperature gradient <b>402</b> of the chip <b>204</b> during bonding without inductive heating is depicted. The different shaded columns of the chart <b>400</b> correspond to the different zones depicted in <figref idref="DRAWINGS">FIG. 6</figref>. The column on the far left of the chart <b>400</b> represents the approximate temperature of the heat source <b>306</b> of both <figref idref="DRAWINGS">FIG. 5</figref>, and the highest temperature of all the zones depicted. Additionally, each temperature zone may have their own maximum temperature, i.e. zone <b>1</b><b>414</b> has a first zone temperature T₁, zone <b>2</b><b>416</b> has a second zone temperature T₂, zone <b>3</b><b>418</b> has a third zone temperature T₃, and zone <b>4</b><b>420</b> has a fourth zone temperature T₄and an outer edge temperature T₅. In some instances, this temperature gradient may cause overheating of the solder bumps in zone <b>1</b><b>414</b>, which may contribute to bridging of the solder bumps. This temperature gradient may also cause inadequate heating of the solder bumps in zone <b>4</b><b>420</b>, which may cause for inadequate wetting of the solder bumps.

0033In order to provide better control on the heating distribution on the chip <b>204</b> and solder bumps <b>206</b>, inductive heating may be provided using the induction coil <b>308</b>. This may allow for a more uniform bonding, such that the temperature at the center of the chip <b>204</b> is within 5° C. of the temperature at the edge of the chip <b>204</b>, or in some instances to create a temperature gradient where the fourth zone <b>440</b> has the highest temperature as shown in <figref idref="DRAWINGS">FIG. 9</figref>. Inductive heating occurs by oscillating a magnetic field to induce a current in conductive materials. This induced current may then heat the conductive materials, such as the tool head <b>304</b>, the tool base <b>306</b> and solder bumps <b>206</b>. Heating rate and distribution may be manipulated by changing the frequency or magnitude of oscillation of the magnetic field, in order to achieve the desired results. The frequency of oscillation should be large enough to induce current to produce sufficient heat to the solder bumps, while being low enough as to not create a substantial voltage in the semiconductor device, which may damage the semiconductor device. In a preferred embodiment, the frequency of oscillation may be from 1 to 1000 kHz.

0034Referring now to <figref idref="DRAWINGS">FIG. 8</figref>, a temperature gradient <b>422</b> of the chip <b>204</b> during bonding with inductive heating is depicted. The temperature gradient <b>422</b> may be depicted using four temperature zones, a first zone <b>434</b>, a second zone <b>436</b>, a third zone <b>438</b>, and a fourth zone <b>440</b>. It should be noted, however, that the number of temperature zones depicted and their relative spatial relationship to one another is provided for illustrative purposes only. The relationship between the temperatures of each zone depicted in <figref idref="DRAWINGS">FIG. 8</figref> is illustrated in the chart depicted in <figref idref="DRAWINGS">FIG. 9</figref>. Further, the placement of the induction coil <b>308</b> on the anterior to the head, or on the outer portion of the head, means that inductive heating would have the greatest effect on the solder bumps located in zone <b>4</b><b>440</b>, with the effect decreasing towards the center of the chip. This may allow for better control of the temperature of zone <b>4</b><b>440</b>, independent from the control of the temperature of zone <b>1</b><b>434</b>.

0035In cases where the heat source <b>306</b> is distributed relatively uniformly, and the induction coil <b>308</b> is used, the center, or the first zone <b>434</b>, of the temperature gradient <b>422</b> may have a first zone temperature T′₅about equal the set temperature of the heat source <b>306</b>. Additionally, each temperature zone boundary may have its own temperature, i.e. first boundary temperature T′₄(located between the first zone <b>434</b> and second zone <b>436</b>), second boundary temperature T′₃(located between the third zone <b>438</b> and second zone <b>436</b>), and third boundary temperature T′₂(located between the third zone <b>438</b> and fourth zone <b>440</b>). Additionally, an outer edge temperature T′₁may represent the temperature on the outer edge of the chip <b>204</b>. In some embodiments, the induction coil <b>308</b> may be operated so that the temperature of the outer edge T′₁is approximately the same as the temperature of the first zone T′₅. In such embodiments, this may allow for the temperature of the heating element to be decreased because supplemental heating is occurring due to the induction coils. Thus, the heat introduced by the heat source <b>306</b> only needs to be enough to reflow the solder bumps <b>206</b> in the center of the chip, and not enough to reflow the solder bumps <b>206</b> throughout the chip. This may allow for uniform heating of the solder bumps, which may eliminate bridging that occurs during overheating, and incomplete formation that occurs from underheating. In other embodiments, the induction coil may be operated. In additional embodiments, the outer edge temperature T′₁may be higher than the first zone temperature T′₅in order to more precisely control the reflow of the solder bumps <b>206</b>.

0036Referring now to <figref idref="DRAWINGS">FIG. 9</figref>, a chart <b>430</b> corresponding to the temperature gradient <b>422</b> of the chip <b>204</b> during bonding with inductive heating is depicted. In the illustrated example, the outer edge temperature T′₁is greater than the temperature in the first zone T′₅. The different shaded columns of the chart <b>430</b> correspond to the different zones depicted in <figref idref="DRAWINGS">FIG. 8</figref>. The column on the far left of the chart <b>430</b> represents the approximate temperature of the heat source <b>306</b>. Additionally, each temperature zone may have their own maximum temperature, i.e. zone <b>1</b><b>434</b> has a first zone temperature T′₄, zone <b>2</b><b>436</b> has a second zone temperature T′₃, zone <b>3</b><b>438</b> has a third zone temperature T′₂, and zone <b>4</b><b>440</b> has a fourth zone temperature T′₁. By using inductive heating, the heat profile <b>430</b> may occur, where the temperature in zone <b>4</b><b>440</b> is higher than the temperature in zone <b>1</b><b>434</b>. By using inductive heating, in addition to a heating element, the temperature profile may be inverted.

0037The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.