Apparatus and method for compression of configuration data
Summary by NHIP
Multi-core configuration compression apparatus
The apparatus compresses configuration data for multiple processor cores using a device programmer with a virtual fuse array and compressor. The compressor employs distinct algorithms for system hardware data and microcode patch data before programming semiconductor fuses on the die.
Claim Score by NHIP
Abstract
An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.
Term
6.9 yearsleft in the term
Expires 21 August 2033.
- Priority
- Filed
- Granted
- Today
- Expires
14 claims: 3 independent, 11 dependent
- 1An apparatus for compressing and storing configuration data for a multi-core processor, the apparatus comprising:a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program said plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on said die, wherein each of said plurality of cores, upon power-up/reset, accesses and decompresses all of said compressed configuration data, for initialization of elements within said each of said plurality of cores, and wherein a first one of said plurality of data types comprises system hardware configuration data that said each of said plurality of cores employs to initialize control circuit elements within said each of said plurality of cores, and wherein a second one of said plurality of data types comprises microcode patch data that said each of said plurality of cores employs to initialize microcode patch elements within said each of said plurality of cores, said device programmer comprising:a virtual fuse array, configured to store the configuration data for said plurality of cores, said configuration data comprising a plurality of data types;anda compressor, coupled to said virtual fuse array, configured to read said virtual fuse array, and configured to compress the configuration data by employing a plurality of compression algorithms to generate said compressed configuration data, wherein said plurality of compression algorithms correspond to said plurality of data types.
- 5An apparatus for compressing and storing configuration data for a multi-core processor, the apparatus comprising:a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program said plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on said die, said device programmer comprising: a virtual fuse array, configured to store the configuration data for said plurality of cores, said configuration data comprising a plurality of data types, said plurality of data types comprising: system hardware configuration data, wherein said system hardware configuration data is not compressed, is programmed into each of said plurality of semiconductor fuses, is accessed by said each of said plurality of cores, and is employed to initialize control circuit elements within said each of said plurality of cores;microcode patch data, wherein said microcode patch data is compressed, is programmed into said plurality of semiconductor fuses, is accessed and decompressed by said each of said plurality of cores, and is employed to initialize microcode patch elements within said each of said plurality of cores;microcode register data;andcache correction data;anda compressor, coupled to said virtual fuse array, configured to read said virtual fuse array, and configured to compress the configuration data by employing a plurality of compression algorithms to generate said compressed configuration data, wherein said plurality of compression algorithms correspond to said plurality of data types.
- 10Broadest claimClaim Score 45, average(NHIP)A method for compressing and storing configuration data for a multi-core processor, the method comprising:coupling a device programmer to a plurality of semiconductor fuses disposed on a die, and programming the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die, wherein a first one of the plurality of data types comprises system hardware configuration data that each of the plurality of cores employs to initialize control circuit elements within the each of the plurality of cores, and wherein a second one of the plurality of data types comprises microcode patch data that the each of the plurality of cores employs to initialize microcode patch elements within the each of the plurality of cores, said coupling comprising:storing the configuration data for the plurality of cores in a virtual fuse array, the configuration data comprising a plurality of data types;andreading the virtual fuse array, and compressing the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, wherein the plurality of compression algorithms corresponds to the plurality of data types.
Independent claims3
97 paragraphs in 6 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of the following U.S. Patent Application.
<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="42pt" align="left" /><colspec colname="2" colwidth="56pt" align="left" /><colspec colname="3" colwidth="119pt" align="left" /><thead><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>SER.</entry><entry>FILING</entry><entry /></row><row><entry>NO.</entry><entry>DATE</entry><entry>TITLE</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>13/972,782</entry><entry>Aug. 21, 2013</entry><entry>MICROPROCESSOR MECHANISM </entry></row><row><entry /><entry /><entry>FOR DECOMPRESSION OF</entry></row><row><entry /><entry /><entry>CACHE CORRECTION DATA</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>
This application is related to the following co-pending U.S. Patent Applications, each of which has a common assignee and common inventors.
<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="35pt" align="left" /><colspec colname="2" colwidth="49pt" align="left" /><colspec colname="3" colwidth="175pt" align="left" /><thead><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>SER.</entry><entry>FILING</entry><entry /></row><row><entry>NO.</entry><entry>DATE</entry><entry>TITLE</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>14/635,006</entry><entry>Mar. 2, 2015</entry><entry>APPARATUS AND METHOD FOR STORAGE AND</entry></row><row><entry /><entry /><entry>DECOMPRESSION OF CONFIGURATION DATA</entry></row><row><entry>14/635,026</entry><entry>Mar. 2, 2015</entry><entry>MULTI-CORE FUSE DECOMPRESSION MECHANISM</entry></row><row><entry>14/635,040</entry><entry>Mar. 2, 2015</entry><entry>EXTENDED FUSE REPROGRAMMABILITY</entry></row><row><entry /><entry /><entry>MECHANISM</entry></row><row><entry>14/635,069</entry><entry>Mar. 2, 2015</entry><entry>APPARATUS AND METHOD FOR EXTENDED CACHE</entry></row><row><entry /><entry /><entry>CORRECTION</entry></row><row><entry>14/635,090</entry><entry>Mar. 2, 2015</entry><entry>CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-</entry></row><row><entry /><entry /><entry>CORE DIE</entry></row><row><entry>14/635,113</entry><entry>Mar. 2, 2015</entry><entry>APPARATUS AND METHOD FOR CONFIGURABLE</entry></row><row><entry /><entry /><entry>REDUNDANT FUSE BANKS</entry></row><row><entry>14/635,933</entry><entry>Mar. 2, 2015</entry><entry>APPARATUS AND METHOD FOR RAPID FUSE BANK</entry></row><row><entry /><entry /><entry>ACCESS IN A MULTI-CORE PROCESSOR</entry></row><row><entry>14/635,969</entry><entry>Mar. 2, 2015</entry><entry>MULTI-CORE MICROPROCESSOR CONFIGURATION</entry></row><row><entry /><entry /><entry>DATA COMPRESSION AND DECOMPRESSION</entry></row><row><entry /><entry /><entry>SYSTEM</entry></row><row><entry>13/972,768</entry><entry>Aug. 21, 2013</entry><entry>MICROPROCESSOR MECHANISM FOR</entry></row><row><entry /><entry /><entry>DECOMPRESSION OF FUSE CORRECTION DATA</entry></row><row><entry>13/972,785</entry><entry>Aug. 21, 2013</entry><entry>MICROPROCESSOR MECHANISM FOR</entry></row><row><entry /><entry /><entry>DECOMPRESSION OF CACHE CORRECTION DATA</entry></row><row><entry>13/972,794</entry><entry>Aug. 21, 2013</entry><entry>APPARATUS AND METHOD FOR COMPRESSION</entry></row><row><entry /><entry /><entry>AND DECOMPRESSION OF MICROPROCESSOR</entry></row><row><entry /><entry /><entry>CONFIGURATION DATA</entry></row><row><entry>13/972,812</entry><entry>Aug. 21, 2013</entry><entry>CORRECTABLE CONFIGURATION DATA</entry></row><row><entry /><entry /><entry>COMPRESSION AND DECOMPRESSION SYSTEM</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to apparatus and methods for providing compressed configuration data in a fuse array associated with a multi-core device.
Description of the Related Art
Integrated device technologies have exponentially advanced over the past 40 years. More specifically directed to the microprocessor fields, starting with 4-bit, single instruction, 10-micrometer devices, the advances in semiconductor fabrication technologies have enabled designers to provide increasingly more complex devices in terms of architecture and density. In the 80's and 90's so-called pipeline microprocessors and superscalar microprocessors were developed comprising millions of transistors on a single die. And now 20 years later, 64-bit, 32-nanometer devices are being produced that have billions of transistors on a single die and which comprise multiple microprocessor cores for the processing of data.
One requirement that has persisted since these early devices were produced is the need to initialize these devices with configuration data when they are turned on or when they are reset. For example, many architectures enable devices to be configured to execute at one of many selectable frequencies and/or voltages. Other architectures require that each device have a serial number and other information that can be read via execution of an instruction. Yet other devices require initialization data for internal registers and control circuits. Still other devices utilize configuration data to implement redundant circuits when primary circuits are fabricated in error or outside of marginal constraints.
As one skilled in the art will appreciate, designers have traditionally employed semiconductor fuse arrays on-die to store and provide initial configuration data. These fuse arrays are generally programmed by blowing selected fuses therein after a part has been fabricated and the arrays contain thousands of bits of information which is read by its corresponding device upon power-up/reset to initialize and configure the device for operation.
As device complexity has increase over the past years, the amount of configuration data that is required for a typical device has proportionately increased. Yet, as one skilled in the art will appreciate, though transistor size shrinks in proportion to the semiconductor fabrication process employed, semiconductor fuse size increases to the unique requirements for programming fuses on die. This phenomenon, in and of itself, is a problem for designers, who are prevalently constrained by real estate and power considerations. That is, there is just not enough real estate on a given die to fabricate a huge fuse array.
In addition, the ability to fabricate multiple device cores on a single die has geometrically exacerbated the problem, because configuration requirements for each of the cores results in requirement for a number of fuses on die, in a single array or distinct arrays, that are equal to the number of cores disposed thereon.
Therefore, what is needed is apparatus and methods that enable configuration data to be stored and provided to a multi-core device that require significantly less real estate and power on a single die than that which has heretofore been provided.
In addition, what is needed is a fuse array mechanism that can store and provide significantly more configuration data than current techniques while requiring the same or less real estate on a multi-core die.
SUMMARY OF THE INVENTION
The present invention, among other applications, is directed to solving the above-noted problems and addresses other problems, disadvantages, and limitations of the prior art by providing a superior technique for utilizing compressed configuration data in a fuse array associated with a multi-core device. In one embodiment, an apparatus is contemplated for compressing and storing configuration data for a multi-core processor. The apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.
One aspect of the present invention contemplates an apparatus for compressing and storing configuration data for a multi-core processor. The apparatus has a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer includes a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores, the configuration data including a plurality of data types. The plurality of data types include system hardware configuration data, microcode patch data, microcode register data, and cache correction data. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.
Another aspect of the present invention comprehends a method for compressing and storing configuration data for a multi-core processor. The method includes coupling a device programmer to a plurality of semiconductor fuses disposed on a die, and programming the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The coupling includes storing the configuration data for the plurality of cores in a virtual fuse array, the configuration data including a plurality of data types; and reading the virtual fuse array, and compressing the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.
Regarding industrial applicability, the present invention is implemented within a MICROPROCESSOR which may be used in a general purpose or special purpose computing device.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:
<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a present day microprocessor core that includes a fuse array for providing configuration data to the microprocessor core;
<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram depicting a fuse array within the microprocessor core of <figref idref="DRAWINGS">FIG. 1</figref> which includes redundant fuse banks that may be blown subsequent to blowing first fuse banks within the fuse array;
<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram featuring a system according to the present invention that provides for compression and decompression of configuration data for a multi-core device;
<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram showing a fuse decompression mechanism according to the present invention;
<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram illustrating an exemplary format for compressed configuration data according to the present invention;
<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating an exemplary format for decompressed microcode patch configuration data according to the present invention;
<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram depicting an exemplary format for decompressed microcode register configuration data according to the present invention;
<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram featuring an exemplary format for decompressed cache correction data according to the present invention;
<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram showing an exemplary format for decompressed fuse correction data according to the present invention;
<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram illustrating configurable redundant fuse arrays in a multi-core device according to the present invention;
<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram detailing a mechanism according to the present invention for rapidly loading configuration data into a multi-core device; and
<figref idref="DRAWINGS">FIG. 12</figref> is a block diagram showing an error checking and correction mechanism according to the present invention.
DETAILED DESCRIPTION
Exemplary and illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification, for those skilled in the art will appreciate that in the development of any such actual embodiment, numerous implementation specific decisions are made to achieve specific goals, such as compliance with system-related and business related constraints, which vary from one implementation to the next. Furthermore, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The present invention will now be described with reference to the attached figures. Various structures, systems, and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase (i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art) is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning (i.e., a meaning other than that understood by skilled artisans) such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
In view of the above background discussion on device fuse arrays and associated techniques employed within present day integrated circuits for providing configuration data during initial power-up, a discussion of the limitations and disadvantages of those techniques will be presented with reference to <figref idref="DRAWINGS">FIGS. 1-2</figref>. Following this, a discussion of the present invention will be presented with reference to <figref idref="DRAWINGS">FIGS. 3-12</figref>. The present invention overcomes all of the limitations and disadvantages discussed below by providing apparatus and methods for employing compressed configuration in a multi-core die which utilize less power and real estate on the multi-core die, and which are more reliable than that which has heretofore been provided.
DEFINITIONS
Integrated Circuit (IC): A set of electronic circuits fabricated on a small piece of semiconductor material, typically silicon. An IC is also referred to as a chip, a microchip, or a die.
Central Processing Unit (CPU): The electronic circuits (i.e., “hardware”) that execute the instructions of a computer program (also known as a “computer application” or “application”) by performing operations on data that include arithmetic operations, logical operations, and input/output operations.
Microprocessor: An electronic device that functions as a CPU on a single integrated circuit. A microprocessor receives digital data as input, processes the data according to instructions fetched from a memory (either on-die or off-die), and generates results of operations prescribed by the instructions as output. A general purpose microprocessor may be employed in a desktop, mobile, or tablet computer, and is employed for uses such as computation, text editing, multimedia display, and Internet browsing. A microprocessor may also be disposed in an embedded system to control a wide variety of devices including appliances, mobile telephones, smart phones, and industrial control devices.
Multi-Core Processor: Also known as a multi-core microprocessor, a multi-core processor is a microprocessor having multiple CPUs (“cores”) fabricated on a single integrated circuit.
Instruction Set Architecture (ISA) or Instruction Set: A part of a computer architecture related to programming that includes data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and input/output. An ISA includes a specification of the set of opcodes (i.e., machine language instructions), and the native commands implemented by a particular CPU.
x86-Compatible Microprocessor: A microprocessor capable of executing computer applications that are programmed according to the x86 ISA.
Microcode: A term employed to refer to a plurality of micro instructions. A micro instruction (also referred to as a “native instruction”) is an instruction at the level that a microprocessor sub-unit executes. Exemplary sub-units include integer units, floating point units, MMX units, and load/store units. For example, micro instructions are directly executed by a reduced instruction set computer (RISC) microprocessor. For a complex instruction set computer (CISC) microprocessor such as an x86-compatible microprocessor, x86 instructions are translated into associated micro instructions, and the associated micro instructions are directly executed by a sub-unit or sub-units within the CISC microprocessor.
Fuse: A conductive structure typically arranged as a filament which can be broken at select locations by applying a voltage across the filament and/or current through the filament. Fuses may be deposited at specified areas across a die topography using well known fabrication techniques to produce filaments at all potential programmable areas. A fuse structure is blown (or unblown) subsequent to fabrication to provide for desired programmability of a corresponding device disposed on the die.
Turning to <figref idref="DRAWINGS">FIG. 1</figref>, a block diagram <b>100</b> is presented illustrating a present day microprocessor core <b>101</b> that includes a fuse array <b>102</b> for providing configuration data to the microprocessor core <b>101</b>. The fuse array <b>102</b> comprises a plurality of semiconductor fuses (not shown) typically arranged in groups known as banks. The fuse array <b>102</b> is coupled to reset logic <b>103</b> that includes both reset circuits <b>104</b> and reset microcode <b>105</b>. The reset logic <b>103</b> is coupled to control circuits <b>107</b>, microcode registers <b>108</b>, microcode patches elements <b>109</b>, and cache correction elements <b>110</b>. An external reset signal RESET is coupled to the microprocessor core <b>101</b> and is routed to the reset logic <b>103</b>.
As one skilled in the art will appreciate, fuses (also called “links” or “fuse structures”) are employed in a vast number of present day integrated circuit devices to provide for configuration of the devices after the devices have been fabricated. For example, consider that the microprocessor core <b>101</b> of <figref idref="DRAWINGS">FIG. 1</figref> is fabricated to provide functionality selectively either as a desktop device or a mobile device. Accordingly, following fabrication, prescribed fuses within the fuse array <b>102</b> may be blown to configure the device as, say, a mobile device. Accordingly, upon assertion of RESET, the reset logic <b>103</b> reads the state of the prescribed fuses in the fuse array <b>102</b> and the reset circuits <b>104</b> (rather than reset microcode <b>105</b>, in this example) enable corresponding control circuits <b>107</b> that deactivate elements of the microprocessor core <b>101</b> exclusively associated with desktop operations and activate elements of the microprocessor core <b>101</b> exclusively associated with mobile operations. Consequently, the microprocessor core <b>101</b> is configured upon power-up reset as a mobile device. In addition, the reset logic <b>103</b> reads the state of the other fuses in the fuse array <b>102</b> and the reset circuits <b>104</b> (rather than reset microcode <b>105</b>, in this example) enable corresponding cache correction elements <b>110</b> provide corrective mechanisms for one or more cache memories associated (not shown) with the microprocessor core <b>101</b>. Consequently, the microprocessor core <b>101</b> is configured upon power-up reset as a mobile device and corrective mechanisms for its cache memories are in place.
The above example is merely one of many different uses for configuration fuses in an integrated circuit device such as a microprocessor core <b>101</b> of <figref idref="DRAWINGS">FIG. 1</figref>. One skilled in the art will appreciate that other uses for configuration fuses include, but are not limited to, configuration of device specific data (e.g., serial numbers, unique cryptographic keys, architecture mandated data that can be accessed by users, speed settings, voltage settings), initialization data, and patch data. For example, many present day devices execute microcode and often require initialization of microcode registers <b>108</b> that are read by the microcode. Such initialization data may be provided by microcode register fuses (not shown) within the fuse array <b>102</b>, which are read upon reset and provided to the microcode registers <b>108</b> by the reset logic <b>103</b> (using either the reset circuits <b>104</b>, the reset microcode <b>105</b>, or both elements <b>104</b>-<b>105</b>). For purposes of the present application, the reset circuits <b>104</b> comprise hardware elements that provide certain types of configuration data, which cannot be provided via the execution of the reset microcode <b>105</b>. The reset microcode <b>105</b> comprises a plurality of micro instructions disposed within an internal microcode memory (not shown) that is executed upon reset of the microprocessor core <b>101</b> to perform functions corresponding to initialization of the microprocessor core <b>101</b>, those functions including provision of configuration data that is read from the fuse array <b>102</b> to elements such as microcode registers <b>108</b> and microcode patch mechanisms <b>109</b>. The criteria for whether certain types of configuration data provided via fuses can be distributed to the various elements <b>107</b>-<b>110</b> in the microprocessor core <b>101</b> via reset microcode <b>105</b> or not is a function primarily of the specific design of the microprocessor core <b>101</b>. It is not the intent of the present application to provide a comprehensive tutorial on specific configuration techniques that are employed to initialize integrated circuit devices, for one skilled in the art will appreciate that for a present day microprocessor core <b>101</b> the types of configurable elements <b>107</b>-<b>110</b> generally fall into four categories as are exemplified in <figref idref="DRAWINGS">FIG. 1</figref>: control circuits, microcode registers, microcode patch mechanisms, and cache correction mechanisms. Furthermore, one skilled will appreciate that the specific values of the configuration data significantly vary based upon the specific type of data. For instance, a 64-bit control circuit <b>107</b> may include ASCII data that prescribes a serial number for the microprocessor core <b>101</b>. Another 64-bit control register may have 64 different speed settings, only one of which is asserted to specify an operating speed for the microprocessor core <b>101</b>. Microcode registers <b>108</b> may typically be initialized to all zeroes (i.e. logic low states) or to all ones (i.e., logic high states). Microcode patch mechanisms <b>109</b> may include an approximately uniform distribution of ones and zeroes to indicate addresses in a microcode ROM (not shown) along with replacement microcode values for those addresses. Finally, cache correction mechanisms may comprise very sparse settings of ones to indicate substitution control signals to replace a certain cache sub-bank element (i.e., a row or a column) with a particular replacement sub-bank element.
Fuse arrays <b>102</b> provide an excellent means for configuring a device such as a the microprocessor core <b>101</b> subsequent to fabrication of the device. By blowing selected fuses in the fuse array <b>102</b>, the microprocessor core <b>101</b> can be configured for operation in its intended environment. Yet, as one skilled in the art will appreciate, operating environments may change following programming of the fuse array <b>102</b>. Business requirements may dictate that microprocessor core <b>101</b> originally configured as, say, as a microprocessor core <b>101</b> for a desktop device, be reconfigured as a a microprocessor core <b>101</b> for a mobile device. Accordingly, designers have provided techniques that utilize redundant banks of fuses within the fuse array <b>102</b> to provide for “unblowing” selected fuses therein, thus enabling the microprocessor core <b>101</b> to be reconfigured, fabrication errors to be corrected, and etc. These redundant array techniques will now be discussed with reference to <figref idref="DRAWINGS">FIG. 2</figref>.
Referring now to <figref idref="DRAWINGS">FIG. 2</figref>, a block diagram <b>200</b> is presented depicting a fuse array <b>201</b> within the microprocessor core <b>101</b> of <figref idref="DRAWINGS">FIG. 1</figref> including redundant fuse banks <b>202</b> RFB<b>1</b>-RFBN that that may be blown subsequent to blowing first fuse banks <b>202</b> PFB<b>1</b>-PFBN within the fuse array <b>201</b>. Each of the fuse banks <b>202</b> PFB<b>1</b>-PFBN, RFB<b>1</b>-RFBN comprises a prescribed number of individual fuses <b>203</b> corresponding to specific design of the microprocessor core <b>101</b>. For example, the number of fuses <b>203</b> in a given fuse bank <b>202</b> may be 64 fuses <b>203</b> in a 64-bit microprocessor core <b>101</b> to facilitate provision of configuration data in a format that is easily implemented in the microprocessor core <b>101</b>.
The fuse array <b>201</b> is coupled to a set of registers <b>210</b>-<b>211</b> that are typically disposed within reset logic in the microprocessor core <b>101</b>. A primary register PR<b>1</b> is employed to read one of the first fuse banks PFB<b>1</b>-PFBN (say, PFB<b>3</b> as is shown in the diagram <b>200</b>) and a redundant register RR<b>1</b> is employed to read a corresponding one of the redundant fuse banks RFB<b>1</b>-RFBN. The registers <b>210</b>-<b>211</b> are coupled to exclusive-OR logic <b>212</b> that generates an output FB<b>3</b>.
In operation, subsequent to fabrication of the microprocessor core <b>101</b>, the first fuse banks PFB<b>1</b>-PFBN are programmed by known techniques with configuration data for the microprocessor core <b>101</b>. The redundant fuse banks RFB<b>1</b>-RFBN are not blown and remain at a logic low state for all fuses therein. Upon power-up/reset of the microprocessor core <b>101</b>, both the first fuse banks PFB<b>1</b>-PFBN and the redundant fuse banks RFB<b>1</b>-RFBN are read as required for configuration into the primary and redundant registers <b>210</b>-<b>211</b>, respectively. The exclusive-OR logic <b>212</b> generates the output FB<b>3</b> that is a logical exclusive-OR result of the contents of the registers <b>210</b>-<b>211</b>. Since all of the redundant fuse banks are unblown (i.e., logic low states), the output FB<b>3</b> value is simply that which was programmed into the first fuse banks PFB<b>1</b>-PFBN subsequent to fabrication.
Consider now, though, that design or business requirements dictate that some of the information that was programmed into the first fuse banks PFB<b>1</b>-PFBN needs to change. Accordingly, a programming operation is performed to blow corresponding fuses <b>203</b> within the redundant fuse banks RFB<b>1</b>-RFBN in order to change the information that is read at power-up. By blowing a fuse <b>203</b> in a selected redundant bank RFB<b>1</b>-RFBN, the value of a corresponding fuse <b>203</b> in the primary fuse bank PFB<b>1</b>-PFBN is logically complemented.
The mechanism of <figref idref="DRAWINGS">FIG. 2</figref> may be employed to provide for “reblow” of fuses <b>203</b> within the microprocessor core <b>101</b>, but as one skilled in the art will appreciate, a given fuse <b>203</b> may only be reblown one time as there is only one set of redundant fuse banks RFB<b>1</b>-RFBN. To provide for additional reblows, a corresponding number of additional fuse banks <b>202</b> and registers <b>210</b>-<b>211</b> must be added to the microprocessor core <b>101</b>.
Heretofore, the fuse array mechanisms as discussed above with reference to <figref idref="DRAWINGS">FIGS. 1-2</figref> has provided enough flexibility to sufficiently configure microprocessor cores and other related devices, while also allowing for a limited number of reblows. This is primarily due to the fact that former fabrication technologies, say 65 nanometer and 45 nanometer processes, allow ample real estate on a die for the implementation of enough fuses to provide for configuration of a microprocessor core <b>101</b> disposed on the die. However, the present inventors have observed that present day techniques are limited going forward due to two significant factors. First, the trend in the art is to dispose multiple device microprocessor cores <b>101</b> on a single die to increase processing performance. These so-called multi-core devices may include, say, 2-16 individual microprocessor cores <b>101</b>, each of which must be configured with fuse data upon power-up/reset. Accordingly, for a 4-core device, four fuse arrays <b>201</b> are required in that some of the data associated with individual microprocessor cores may vary (e.g., cache correction data, redundant fuse data, etc.). Secondly, as one skilled in the art will appreciate, as fabrication process technologies shrink to, say, 32 nanometers, while transistor size shrinks accordingly, fuse size increases, thus requiring more die real estate to implement the same size fuse array on a 32-nanometer die opposed to that on a 45-nanometer die.
Both of the above limitations, and others, pose significant challenges to device designers, and more specifically to multi-core device designers, and the present inventors note that significant improvements over conventional device configuration mechanisms can be implemented in accordance with the present invention, which allows for programming of individual cores in a multi-core device along with substantial increases in cache correction and fuse reprogramming (“reblow”) elements. The present invention will now be discussed with reference to <figref idref="DRAWINGS">FIGS. 3-12</figref>.
Turning to <figref idref="DRAWINGS">FIG. 3</figref>, a block diagram is presented featuring a system <b>300</b> according to the present invention that provides for compression and decompression of configuration data for a multi-core device. The multi-core device comprises a plurality of microprocessor cores <b>332</b> disposed on a die <b>330</b>. For illustrative purposes, four cores <b>332</b> CORE <b>1</b>-CORE <b>4</b> are depicted on the die <b>330</b>, although the present invention contemplates various numbers of cores <b>332</b> disposed on the die <b>330</b>. In one embodiment, all the microprocessor cores <b>332</b> share a single cache memory <b>334</b> that is also disposed on the die <b>330</b>. A fuse array <b>336</b> is also disposed on the die <b>330</b> and each of the microprocessor cores <b>332</b> are configured to access the fuse array <b>336</b> to retrieve and decompress configuration data as described above during power-up/reset.
In one embodiment, the microprocessor cores <b>332</b> comprise microprocessor cores configured as a multi-core microprocessor disposed on the die <b>330</b>. In another embodiment, the multi-core microprocessor is configured as an x86-compatible multi-core microprocessor. In yet another embodiment, the cache <b>334</b> comprises a level 2 (L2) cache <b>334</b> associated with the microprocessor cores <b>332</b>. In one embodiment, the fuse array <b>336</b> comprises 8192 (<b>8</b>K) individual fuses (not shown), although other numbers of fuses are contemplated. In a single-core embodiment, only one core <b>332</b> is disposed on the die <b>330</b> and the core <b>332</b> is coupled to the cache <b>334</b> and fuse array <b>336</b>. The present inventors note that although features and functions of the present invention will henceforth be discussed in the context of a multi-core device disposed on the die <b>330</b>, these features and functions are equally applicable to a single-core embodiment as well.
The system <b>300</b> also includes a device programmer <b>310</b> that includes a compressor <b>320</b> that is coupled to a virtual fuse array <b>303</b>. In one embodiment, the device programmer <b>310</b> may comprise a CPU (not shown) that is configured to process configuration data and to program the fuse array <b>336</b> following fabrication of the die <b>330</b> according to well known programming techniques. The CPU may be integrated into a wafer test apparatus that is employed to test the die <b>330</b> following fabrication. In one embodiment, the compressor <b>320</b> may comprise an application program that executes on the device programmer <b>310</b> and the virtual fuse array <b>303</b> may comprise locations within a memory that is accessed by the compressor <b>320</b>. The virtual fuse array <b>303</b> includes a plurality of virtual fuse banks <b>301</b>, that each comprise a plurality of virtual fuses <b>302</b>. In one embodiment the virtually fuse array <b>303</b> comprises 128 virtual fuse banks <b>301</b> that each comprise 64 virtual fuses <b>302</b>, resulting in a virtual fuse array <b>303</b> that is 8 Kb in size.
Operationally, configuration information for the die <b>330</b> is entered into the virtual fuse array <b>303</b> as part of the fabrication process, and as is described above with reference to <figref idref="DRAWINGS">FIG. 1</figref>. Accordingly, the configuration information comprises control circuits configuration data, initialization data for microcode registers, microcode patch data, and cache correction data. Further, as described above, the distributions of values for associated with each of the data types is substantially different from type to type. The virtual fuse array <b>303</b> is a logical representation of a fuse array (not shown) that comprises configuration information for each of the microprocessor cores <b>332</b> on the die <b>330</b> and correction data for each of the caches <b>334</b> on the die <b>330</b>.
After the information is entered into the virtual fuse array <b>303</b>, the compressor <b>320</b> reads the state of the virtual fuses <b>302</b> in each of the virtual fuse banks <b>301</b> and compresses the information using distinct compression algorithms corresponding to each of the data types to render compressed fuse array data within the virtual fuse array <b>303</b>. In one embodiment, system data for control circuits is not compressed, but rather is transferred without compression. To compress microcode register data, a microcode register data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the microcode register data. To compress microcode patch data, a microcode patch data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the microcode patch data. To compress cache correction data, a cache correction data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the cache correction data.
The device programmer <b>310</b> then programs the uncompressed and compressed fuse array data into the fuse array <b>336</b> on the die <b>330</b>.
Upon power-up/reset, each of the microprocessor cores <b>332</b> may access the fuse array <b>336</b> to retrieve the uncompressed and compressed fuse array data, and reset circuits/microcode (not shown) disposed within each of the microprocessor cores <b>332</b> distributes the uncompressed fuse array data, and decompresses the compressed fuse array data according to distinct decompression algorithms corresponding to each of the data types noted above to render values originally entered into the virtual fuse array <b>303</b>. The reset circuits/microcode then enter the configuration information into control circuits (not shown), microcode registers (not shown), patch elements (not shown), and cache correction elements (not shown).
Advantageously, the fuse array compression system <b>300</b> according to the present invention enables device designers to employ substantially fewer numbers of fuses in a fuse array <b>336</b> over that which has heretofore been provided, and to utilize the compressed information programmed therein to configure a multi-core device disposed on the die disposed on the die <b>330</b> during power-up/reset.
Turning now to <figref idref="DRAWINGS">FIG. 4</figref>, a block diagram <b>400</b> is presented showing a fuse decompression mechanism according to the present invention. The decompression mechanism may be disposed within each of the microprocessor cores <b>332</b> of <figref idref="DRAWINGS">FIG. 3</figref>. For purposes of clearly teaching the present invention, only one core <b>420</b> is depicted in <figref idref="DRAWINGS">FIG. 4</figref> and each of the microprocessor cores <b>332</b> disposed on the die comprise substantially equivalent elements as the core <b>420</b> shown. A physical fuse array <b>401</b> disposed on the die as described above is coupled to the core <b>420</b>. The physical fuse array <b>401</b> comprises compressed microcode patch fuses <b>403</b>, compressed register fuses <b>404</b>, compressed cache correction fuses <b>405</b>, and compressed fuse correction fuses <b>406</b>. The physical fuse array <b>401</b> may also comprise uncompressed configuration data (not shown) such as system configuration data as discussed above and/or block error checking and correction (ECC) codes (not shown). The inclusion of ECC features according to the present invention will be discussed in further detail below.
The microprocessor core <b>420</b> comprises a reset controller <b>417</b> that receives a reset signal RESET which is asserted upon power-up of the core <b>420</b> and in response to events that cause the core <b>420</b> to initiate a reset sequence of steps. The reset controller <b>417</b> includes a decompressor <b>421</b>. The decompressor <b>421</b> has a patch fuses element <b>408</b>, a register fuses element <b>409</b>, and a cache fuses element <b>410</b>. The decompressor also comprises a fuse correction element <b>411</b> that is coupled to the patch fuses element <b>408</b>, the register fuses element <b>409</b>, and the cache fuses element <b>410</b> via bus <b>412</b>. The patch fuses element <b>408</b> is coupled to microcode patch elements <b>414</b> in the core <b>420</b>. The register fuses element <b>409</b> is coupled to microcode registers <b>415</b> in the core <b>420</b>. And the cache fuses element <b>410</b> is coupled to cache correction elements <b>416</b> in the core <b>420</b>. In one embodiment, the cache correction elements <b>416</b> are disposed within an on-die L2 cache (not shown) that is shared by all the cores <b>420</b>, such as the cache <b>334</b> of <figref idref="DRAWINGS">FIG. 3</figref>. Another embodiment contemplates cache correction elements <b>416</b> disposed within an L1 cache (not shown) within the core <b>420</b>. A further embodiment considers cache correction elements <b>416</b> disposed to correct both the L2 and L1 caches described above.
In operation, upon assertion of RESET the reset controller <b>417</b> reads the states of the fuses <b>403</b>-<b>406</b> in the physical fuse array <b>401</b> and distributes the states of the fuses <b>403</b>-<b>406</b> to the decompressor <b>421</b>. After the fuse data has been read and distributed, the fuse correction element <b>411</b> of the decompressor <b>421</b> decompresses the compressed fuse correction fuses states to render data that indicates one or more fuse addresses in the physical fuse array <b>401</b> whose states are to be changed from that which was previously programmed. The data may also include a value for each of the one or more fuse addresses. The one or more fuse addresses (and optional values) are routed via bus <b>412</b> to the elements <b>408</b>-<b>410</b> so that the states of corresponding fuses processed therein are changed prior to decompression of their corresponding compressed data.
In one embodiment, the patch fuses element <b>408</b> comprises microcode that operates to decompress the states of the compressed microcode patch fuses <b>403</b> according to a microcode patch decompression algorithm that corresponds the microcode patch compression algorithm described above with reference to <figref idref="DRAWINGS">FIG. 3</figref>. In one embodiment, the register fuses element <b>409</b> comprises microcode that operates to decompress the states of the compressed register fuses <b>404</b> according to a register fuses decompression algorithm that corresponds to the register fuses compression algorithm described above with reference to <figref idref="DRAWINGS">FIG. 3</figref>. In one embodiment, the cache fuses element <b>410</b> comprises microcode that operates to decompress the states of the compressed cache correction fuses <b>405</b> according to a cache correction fuses decompression algorithm that corresponds to the cache correction fuses compression algorithm described above with reference to <figref idref="DRAWINGS">FIG. 3</figref>. After each of the elements <b>408</b>-<b>410</b> change the states of any fuses whose addresses (and optional values) are provided via bus <b>412</b> from the fuse correction element <b>411</b>, their respective data is decompressed according to the corresponding algorithm employed. As will be described in further detail below, the present invention contemplates multiple “reblows” of any fuse address within the physical fuse array prior to the initiation of the decompression process executed by any of the decompressors <b>408</b>-<b>411</b>. In one embodiment bus <b>412</b> may comprise conventional microcode programming mechanisms that are employed to transfer data between respective routines therein. The present invention further contemplates a comprehensive decompressor <b>421</b> having capabilities to recognize and decompress configuration data based upon its specific type. Accordingly, the recited elements <b>408</b>-<b>411</b> within the decompressor <b>421</b> are presented in order to teach relevant aspects of the present invention, however, contemplated implementations of the present invention may not necessarily include distinct elements <b>408</b>-<b>411</b>, but rather a comprehensive decompressor <b>421</b> that provides functionality corresponding to each of the elements <b>408</b>-<b>411</b> discussed above.
In one embodiment, the reset controller <b>417</b> initiates execution of microcode within the patch fuses element <b>408</b> to decompress the states of the compressed microcode patch fuses <b>403</b>. The reset controller <b>417</b> also initiates execution of microcode within the register fuses element <b>409</b> to decompress the states of the compressed register fuses <b>404</b>. And the reset controller <b>417</b> further initiates execution of microcode within the cache fuses element <b>410</b> to decompress the states of the compressed cache correction fuses <b>405</b>. The microcode within the decompressor <b>421</b> also operates to change the states of any fuses addressed by fuse correction data provided by the compressed fuse correction fuses <b>406</b> prior to decompression of the compressed data.
The reset controller <b>417</b>, decompressor <b>421</b>, and elements <b>408</b>-<b>411</b> therein according to the present invention are configured to perform the functions and operations as discussed above. The reset controller <b>417</b>, decompressor <b>421</b>, and elements <b>408</b>-<b>411</b> therein may comprise logic, circuits, devices, or microcode, or a combination of logic, circuits, devices, or microcode, or equivalent elements that are employed to execute the functions and operations according to the present invention as noted. The elements employed to accomplish these operations and functions within the reset controller <b>417</b>, decompressor <b>421</b>, and elements <b>408</b>-<b>411</b> therein may be shared with other circuits, microcode, etc., that are employed to perform other functions and/or operations within the reset controller <b>417</b>, decompressor <b>421</b>, and elements <b>408</b>-<b>411</b> therein or with other elements within the core <b>420</b>.
After the states of the fuses <b>403</b>-<b>406</b> within the physical fuse array <b>401</b> have been changed and decompressed, the states of the decompressed “virtual” fuses are then routed, as appropriate to the microcode patch elements <b>414</b>, the microcode registers <b>415</b>, and the cache correction elements <b>416</b>. Accordingly, the core <b>420</b> is configured for operation following completion of a reset sequence.
The present inventors note that the decompression functions discussed above need not necessarily be performed in a particular order during a reset sequence. For example, microcode patches may be decompressed following decompression of microcode registers initialization data. Likewise, the decompression functions may be performed in parallel or in an order suitable to satisfy design constraints.
Furthermore, the present inventors note that the implementations of the elements <b>408</b>-<b>411</b> need not necessarily be implemented in microcode versus hardware circuits, since in a typical microprocessor core <b>420</b> there exist elements of the core <b>420</b> which can more easily be initialized via hardware (such as a scan chain associated with a cache) as opposed to direct writes by microcode. Such implementation details are left up to designer judgment. However, the present inventors submit that the prior art teaches that cache correction fuses are conventionally read and entered into a cache correction scan chain by hardware circuits during reset prior to initiating the execution of microcode, and it is a feature of the present invention to implement the cache fuses decompressor <b>410</b> in microcode as opposed to hardware control circuits since a core's caches are generally not turned on until microcode runs. By utilizing microcode to implement the cache fuses element <b>410</b>, a more flexible and advantageous mechanisms is provided for entering cache correction data into a scan chain, and significant hardware is saved.
Now referring to <figref idref="DRAWINGS">FIG. 5</figref>, a block diagram is presented illustrating an exemplary format <b>500</b> for compressed configuration data <b>500</b> according to the present invention. The compressed configuration data <b>500</b> is compressed by the compressor <b>320</b> of <figref idref="DRAWINGS">FIG. 3</figref> from data residing in the virtual fuse array <b>303</b> and is programmed (i.e., “blown”) into the fuse array <b>336</b> of the multi-core device <b>330</b>. During a reset sequence, as is described above, the compressed configuration data <b>500</b> is retrieved from the fuse array <b>336</b> by each of the cores <b>332</b> and is decompressed and corrected by the elements <b>408</b>-<b>411</b> of the decompressor <b>421</b> within each of the cores <b>420</b>. The decompressed and corrected configuration data is then provided to the various elements <b>414</b>-<b>416</b> within the core <b>420</b> to initialize the core <b>420</b> for operation.
The compressed configuration data <b>500</b> comprises one or more compressed data fields <b>502</b> for each of the configuration data types discussed above and are demarcated by end-of-type fields <b>503</b>. Programming events (i.e., “blows”) are demarcated by an end-of-blow field <b>504</b>. The compressed data fields <b>502</b> associated with each of the data types are encoded according to a compression algorithm that is optimized to minimize the number of bits (i.e., fuses) that are required to store the particular bit patterns associated with each of the data types. The number of fuses in the fuse array <b>336</b> that make up each of compressed data fields <b>502</b> is a function of the compression algorithm that is employed for a particular data type. For example, consider a core that comprises sixty-four 64-bit microcode registers which must be initialized to, say, all ones or all zeroes. An optimum compression algorithm may be employed to yield 64 compressed data fields <b>502</b> for that data type, where each of the compressed data fields <b>502</b> comprises initialization data for a particular microcode register where the compressed data fields <b>502</b> are prescribed in register number order (i.e., 1-64). And each of the compressed data fields <b>502</b> comprises a single fuse which is blown if a corresponding microcode register is initialized to all ones, and which is not blown if the corresponding microcode register is initialized to all zeroes.
The elements <b>408</b>-<b>410</b> of the decompressor <b>421</b> in the core <b>420</b> are configured to utilize the end-of-type fields <b>503</b> to determine where their respective compressed data is located within the fuse array <b>336</b> and the fuse correction decompressor <b>411</b> is configured to utilize the end-of-blow fields <b>504</b> to locate compressed fuse correction data that has been programmed (i.e., blown) subsequent to an initial programming event. It is a feature of the present invention to provide a substantial amount of spare fuses in the fuse array <b>336</b> to allow for a significant number of subsequent programming events, as will be discussed in more detail below.
The exemplary compressed type format discussed above is presented to clearly teach aspects of the present invention that are associated with compression and decompression of configuration data. However, the manner in which specific type data is compressed, demarcated, and the number and types of data to be compressed within the physical fuse array <b>401</b> is not intended to be restricted to the example of <figref idref="DRAWINGS">FIG. 5</figref>. Other numbers, types, and formats are contemplated that allow for tailoring of the present invention to various devices and architectures extant in the art.
Turning now to <figref idref="DRAWINGS">FIG. 6</figref>, a block diagram is presented illustrating an exemplary format for decompressed microcode patch configuration data <b>600</b> according to the present invention. During a reset sequence, compressed microcode patch configuration data is read by each core <b>420</b> from the physical fuse array <b>401</b>. The compressed microcode patch configuration data is then corrected according to fuse correction data provided via bus <b>412</b>. Then, the corrected compressed microcode patch configuration data is decompressed by the patch fuses decompressor <b>408</b>. The result of the decompression process is the decompressed microcode patch configuration data <b>600</b>. The data <b>600</b> comprises a plurality of decompressed data blocks <b>604</b> corresponding to the number of microcode patch elements <b>414</b> within the core <b>420</b> that require initialization data. Each decompressed data block <b>604</b> comprises a core address field <b>601</b>, a microcode ROM address field <b>602</b>, and a microcode patch data field <b>603</b>. The sizes of the fields <b>601</b>-<b>603</b> are a function of the core architecture. As part of the decompression process, the patch fuses decompressor <b>408</b> creates a complete image of the target data required to initialize the microcode patch elements <b>414</b>. Following decompression of the microcode patch configuration data <b>600</b>, conventional distribution mechanisms may be employed to distribute the data <b>603</b> to respectively addressed core and microcode ROM substitution circuits/registers in the microcode patch elements <b>414</b>.
Now turning to <figref idref="DRAWINGS">FIG. 7</figref>, a block diagram is presented depicting an exemplary format for decompressed microcode register configuration data <b>700</b> according to the present invention. During a reset sequence, compressed microcode register configuration data is read by each core <b>420</b> from the physical fuse array <b>401</b>. The compressed microcode register configuration data is then corrected according to fuse correction data provided via bus <b>412</b>. Then, the corrected compressed microcode register configuration data is decompressed by the register fuses decompressor <b>409</b>. The result of the decompression process is the decompressed microcode register configuration data <b>700</b>. The data <b>700</b> comprises a plurality of decompressed data blocks <b>704</b> corresponding to the number of microcode registers <b>415</b> within the core <b>420</b> that require initialization data. Each decompressed data block <b>704</b> comprises a core address field <b>701</b>, a microcode register address field <b>702</b>, and a microcode register data field <b>703</b>. The sizes of the fields <b>701</b>-<b>703</b> are a function of the core architecture. As part of the decompression process, the register fuses decompressor <b>409</b> creates a complete image of the target data required to initialize the microcode registers element <b>415</b>. Following decompression of the microcode register configuration data <b>700</b>, conventional distribution mechanisms may be employed to distribute the data <b>703</b> to respectively addressed core and microcode registers element <b>415</b>.
Referring now to <figref idref="DRAWINGS">FIG. 8</figref>, a block diagram is presented featuring an exemplary format for decompressed cache correction data <b>800</b> according to the present invention. During a reset sequence, compressed cache correction data is read by each core <b>420</b> from the physical fuse array <b>401</b>. The compressed cache correction data is then corrected according to fuse correction data provided via bus <b>412</b>. Then, the corrected compressed cache correction data is decompressed by the cache fuses decompressor <b>410</b>. The result of the decompression process is the decompressed cache correction data <b>800</b>. Various cache mechanisms may be employed in the multi-core processor <b>330</b> and the decompressed cache correction data <b>800</b> is presented in the context of a shared L2 cache <b>334</b>, where all of the cores <b>332</b> may access a single cache <b>334</b>, utilizing shared areas. Accordingly, the exemplary format is provided according to the noted architecture. The data <b>800</b> comprises a plurality of decompressed data blocks <b>804</b> corresponding to the number of cache correction elements <b>416</b> within the core <b>420</b> that require corrective data. Each decompressed data block <b>804</b> comprises a sub-unit column address field <b>802</b> and a replacement column address field <b>803</b>. As one skilled in the art will appreciate, memory caches are fabricated with redundant columns (or rows) in sub-units of the caches to allow for a functional redundant column (or row) in a particular sub-unit to be substituted for a non-functional column (or row). Thus, the decompressed cache correction data <b>800</b> allows for substitution of functional columns (as shown in <figref idref="DRAWINGS">FIG. 8</figref>) for non-functional columns. In addition, as one skilled in the art will concur, conventional fuse array mechanisms associated with cache correction include fuses associated with each sub-unit column that are blown when substitution is required by redundant sub-unit columns. Accordingly, because such a large number of fuses are required (to address all sub-units and columns therein), only a portion of the sub-units are typically covered, and then the resulting conventional cache correction fuses are very sparsely blown. And the present inventors note that it is a feature of the present invention to address and compress sub-unit column addresses and replacement column addresses only for those sub-unit columns that require replacement, thus minimizing the number of fuses that are required to implement cache correction data. Consequently, the present invention, as limited by physical fuse array size and the amount of additional configuration data that is programmed therein, provides the potential for expanding the number of sub-unit columns (or rows) in a cache <b>334</b> that can be corrected over that which has heretofore been provided. In the embodiment shown in <figref idref="DRAWINGS">FIG. 8</figref>, it is noted that the associated cores <b>332</b> are configured such that only one of the cores <b>332</b> sharing the L2 cache <b>334</b> would access and provide the corrective data <b>802</b>-<b>803</b> to its respective cache correction elements <b>416</b>. The sizes of the fields <b>802</b>-<b>803</b> are a function of the core architecture. As part of the decompression process, the cache correction fuses decompressor <b>410</b> creates a complete image of the target data required to initialize the cache correction elements <b>416</b>. Following decompression of the cache correction data <b>800</b>, conventional distribution mechanisms in the responsible core <b>332</b> may be employed to distribute the data <b>802</b>-<b>803</b> to respectively addressed cache correction elements <b>416</b>.
Turning now to <figref idref="DRAWINGS">FIG. 9</figref>, a block diagram is presented showing an exemplary format for decompressed fuse correction data <b>900</b> according to the present invention. As has been discussed above, during reset the fuse correction decompressor <b>411</b> accesses compressed fuse correction data <b>406</b> within the physical fuse array <b>401</b>, decompresses the compressed fuse correction data, and supplies the resulting decompressed fuse correction data <b>900</b> to the other decompressors <b>408</b>-<b>410</b> within the core <b>420</b>. The decompressed fuse correction data comprises one or more end-of-blow fields <b>901</b> that indicate the end of successively programming events in the physical fuse array <b>401</b>. If a subsequent programming event has occurred, a reblow field <b>902</b> is programmed to indicate that a following one or more fuse correction fields <b>903</b> indicate fuses within the physical fuse array <b>401</b> that are to be reblown. Each of the fuse correction fields comprises an address of a specific fuse within the physical fuse array <b>401</b> that is to be reblown along with a state (i.e., blown or unblown) for the specific fuse. Only those fuses that are to be reblown are provided in the fuse correction blocks fields <b>903</b>, and each group of fields <b>903</b> within a given reblow event is demarcated by an end-of-blow field <b>901</b>. If reblow field <b>902</b>, properly encoded, is present after a given end-of-blow field <b>901</b>, then subsequent one or more fuses may be configured reblown as indicated by corresponding fuse correction fields. Thus, the present invention provides the capability for a substantial number of reblows for the same fuse, as limited by array size and other data provided therein.
The present inventors have also observed that the real estate and power gains associated with utilization of a shared physical fuse array within which compressed configuration data is stored presents opportunities for additional features disposed on a multi-core die. In addition, the present inventors have noted that, as one skilled in the art will appreciate, present day semiconductor fuse structures often suffer from several shortcomings, one of which is referred to as “growback.” Growback is the reversal of the programming process such that a fuse will, after some time, reconnect after it has been blown, that is, it goes from a programmed (i.e., blown) state back to an unprogrammed (i.e., unblown) state.
To address growback, and other challenges, the present invention provides several advantages, one of which is provision of redundant, yet configurable, physical fuse arrays. Accordingly, a configurable, redundant fuse bank mechanism will now be presented with reference to <figref idref="DRAWINGS">FIG. 10</figref>.
Referring to <figref idref="DRAWINGS">FIG. 10</figref>, a block diagram is presented illustrating configurable, redundant fuse arrays <b>1001</b> in a multi-core device <b>1000</b> according to the present invention. The multi-core device <b>1000</b> includes a plurality of cores <b>1002</b> that are configured substantially as described above with reference to <figref idref="DRAWINGS">FIGS. 3-9</figref>. In addition, each of the cores <b>1002</b> includes array control <b>1003</b> that is programmed with configuration data within a configuration data register <b>1004</b>. Each of the cores <b>1002</b> is coupled to the redundant fuse arrays <b>1001</b>.
For purposes of illustration, only four cores <b>1002</b> and two physical fuse arrays <b>1001</b> are shown, however the present inventors note that the novel and inventive concepts according to the present invention can be extended to a plurality of cores <b>1002</b> of any number and to more than two physical fuse arrays <b>1001</b>.
In operation, each of the cores <b>1002</b> receives configuration data within the configuration data register <b>1004</b> that indicates a specified configuration for the physical fuse arrays <b>1001</b>. In one embodiment, the arrays may be configured according to the value of the configuration data as an aggregate physical fuse array. That is, the size of the aggregate physical fuse array is equal to the sum of the sizes of the individual physical fuse arrays <b>1001</b>, and the aggregate physical fuse array may be employed to store substantially more configuration data than is provided for by a single one of the individual physical fuse arrays <b>1001</b>. Accordingly, the array control <b>1003</b> directs its corresponding core <b>1002</b> to read the physical fuse arrays <b>1001</b> as an aggregate physical fuse array. In another embodiment, to address growback, according to the value of the configuration data, the physical fuse arrays <b>1001</b> are configured as redundant fuse arrays that are programmed with the same configuration data, and the array control <b>1003</b> within each of the cores <b>1002</b> comprises elements that enable the contents of the two (or more) arrays to be logically OR-ed together so that if one or more of the blown fuses within a given array <b>1001</b> exhibits growback, at least one of its corresponding fuses in the remaining arrays <b>1001</b> will still be blown. In a fail-safe embodiment, according to the value of the configuration data, one or more of the physical fuse arrays <b>1001</b> may be selectively disabled, and the remaining arrays <b>1001</b> enabled for use in either an aggregate configuration or a logically OR-ed configuration. Accordingly, the array control <b>1003</b> in each of the cores <b>1002</b> will not access contents of the selectively disabled arrays <b>1001</b>, and will access the remaining arrays according to the configuration specified by the configuration data in the configuration data register <b>1004</b>.
The configuration data registers <b>1004</b> may be programmed by any of a number of well known means to include programmable fuses, external pin settings, JTAG programming, and the like.
In another aspect, the present inventors have noted that there may exist challenges when one or more physical fuse arrays are disposed on a single die that comprises multiple cores which access the arrays. More specifically, upon power-up/reset each core in a multi-core processor must read the physical fuse array in a serial fashion. That is, a first core reads the array, then a second core, then a third core, and so on. As one skilled in the art will appreciate, compared to other operations performed by the core, the reading of a fuse array is exceedingly time consuming and, thus, when multiple cores must read the same array, the time required to do so is roughly the time required for one core to read the array multiplied by the number of cores on the die. And as one skilled in the art will appreciate, semiconductor fuses degrade as they are read and there are lifetime limitations, according to fabrication process, for the reading of those fuses to obtain reliable results. Accordingly, another embodiment of the present invention is provided to 1) decrease the amount of time required for all cores to read a physical fuse array and 2) increase the overall lifetime of the fuse array by decreasing the number of accesses by the cores in a multi-core processor upon power-up/reset.
Attention is now directed to <figref idref="DRAWINGS">FIG. 11</figref>, where a block diagram is presented detailing a mechanism according to the present invention for rapidly loading configuration data into a multi-core device <b>1100</b>. The device <b>1100</b> includes a plurality of cores <b>1102</b> that are configured substantially as described above with reference to <figref idref="DRAWINGS">FIGS. 3-10</figref>. In addition, each of the cores <b>1102</b> includes array control <b>1103</b> that is programmed with load data within a load data register <b>1104</b>. Each of the cores <b>1102</b> are coupled to a physical fuse array <b>1101</b> that is configured as described above with reference to <figref idref="DRAWINGS">FIGS. 3-10</figref>, and to a random access memory (RAM) <b>1105</b> that is disposed on the same die as the cores <b>1102</b>, but which is not disposed within any of the cores <b>1102</b>. Hence, the RAM <b>1105</b> is referred to as “uncore” RAM <b>1105</b>.
For purposes of illustration, only four cores <b>1102</b> and a single physical fuse array <b>1101</b> are shown, however the present inventors note that the novel and inventive concepts according to the present invention can be extended to a plurality of cores <b>1102</b> of any number and to a plurality of physical fuse arrays <b>1101</b>.
In operation, each of the cores <b>1102</b> receives load data within the load data register <b>1104</b> that indicates a specified load order for data corresponding to the physical fuse array <b>1101</b>. The value of contents of the load register <b>1104</b> designates one of the cores <b>1102</b> as a “master” core <b>1102</b>, and the remaining cores as “slave” cores <b>1102</b> having a load order associated therewith. Accordingly, upon power-up/reset, the array control <b>1103</b> directs the master core <b>1102</b> to read the contents of the physical fuse array <b>1101</b> and then to write the contents of the physical fuse array <b>1101</b> to the uncore RAM <b>1105</b>. If a plurality of physical fuse arrays <b>1101</b> are disposed on the die, then the uncore RAM <b>1105</b> is sized appropriately to store the contents of the plurality of arrays <b>1101</b>. After the master core <b>1102</b> has written the contents of the physical fuse array <b>1101</b> to the uncore RAM <b>1105</b>, then array control <b>1103</b> directs their corresponding slave cores <b>1102</b> to read the fuse array contents from the uncore RAM <b>1105</b> in the order specified by contents of the load data register <b>1104</b>.
The load data registers <b>1104</b> may be programmed by any of a number of well known means to include programmable fuses, external pin settings, JTAG programming, and the like. It is also noted that the embodiment of <figref idref="DRAWINGS">FIG. 11</figref> may be employed in conjunction with any of the embodiments of the configurable, redundant fuse array mechanism discussed above with reference to <figref idref="DRAWINGS">FIG. 10</figref>.
Now referring to <figref idref="DRAWINGS">FIG. 12</figref>, a block diagram <b>1200</b> is presented illustrating an error checking and correction (ECC) mechanism according to the present invention. The ECC mechanism may be employed in conjunction with any of the embodiments of the present invention described above with reference to <figref idref="DRAWINGS">FIGS. 3-11</figref> and provides for another layer of robustness for the compression and decompression of configuration data. The diagram depicts a microprocessor core <b>1220</b> disposed on a die that is coupled to a physical fuse array <b>1201</b> comprising compressed configuration data blocks <b>1203</b> as is described above. In addition to the compressed configuration data blocks <b>1203</b>, the array <b>1201</b> includes ECC code blocks <b>1202</b> that each are associated with a corresponding one of the data blocks <b>1203</b>. In one embodiment, the data blocks <b>1203</b> are 64 bits (i.e., fuses) in size and the ECC code blocks <b>1202</b> are 8 bits in size. The core <b>1220</b> includes a reset controller <b>1222</b> that receives a reset signal RESET. The reset controller <b>1222</b> has an ECC element <b>1224</b> that is coupled to a decompressor <b>1226</b> via bus CDATA. The ECC element <b>1224</b> is coupled to the fuse array <b>1201</b> via an address bus ADDR, a data bus DATA, and a code bus CODE.
In operation, the physical fuse array <b>1201</b> is programmed with configuration data in the data blocks <b>1203</b> as is described above with reference to <figref idref="DRAWINGS">FIGS. 3-11</figref>. The configuration data corresponding to a particular data type (e.g., microcode path data, microcode register data) is not required to be programmed within the boundaries of a given data block <b>1203</b>, but rather may span more than one data block <b>1203</b>. Furthermore, configuration data corresponding to two or more types of configuration data may be programmed into the same data block <b>1203</b>. In addition, the array <b>1201</b> is programmed with ECC codes in the ECC code blocks <b>1202</b> that each result from ECC generation for the data programmed into a corresponding data block <b>1203</b> according to one of a number of well known ECC mechanisms including, but not limited to, SECDED Hamming ECC, Chipkill ECC, and variations of forward error correction (FEC) codes. In one embodiment, the addresses associated with a given data block <b>1203</b> and its corresponding ECC code block <b>1202</b> are known. Thus, it is not required that the corresponding ECC code block <b>1202</b> be located adjacent to the given data block <b>1203</b>, as is depicted in <figref idref="DRAWINGS">FIG. 12</figref>.
The decompressor <b>1226</b> is configured and functions substantially similar to the decompressor <b>421</b> described above with reference to <figref idref="DRAWINGS">FIG. 4</figref>, and as allude to with reference to <figref idref="DRAWINGS">FIGS. 5-11</figref>. Upon reset of the core <b>1220</b>, prior to execution of any of the decompression functions described above, the ECC element within the reset controller <b>1222</b> accesses the fuse array <b>1201</b> to obtain its contents. Addresses associated with given data blocks <b>1203</b> and ECC code blocks <b>1202</b> may be obtained via bus ADDR. Compressed configuration data within each of the data blocks <b>1203</b> may be obtained via bus DATA. And ECC codes for each of the ECC code blocks <b>1202</b> may be obtained via bus CODE. As the noted data, addresses, and codes are obtained, the ECC element <b>1224</b> operates to generate ECC checks for the data retrieved for each data block <b>1203</b> according to the ECC mechanism that was employed to generate the ECC code stored in the corresponding ECC code block <b>1202</b>. The ECC element <b>1224</b> also compares the ECC checks with corresponding ECC codes obtained from the array <b>1201</b> to produce ECC syndromes. The ECC element <b>1224</b> further decodes the ECC syndromes to determine if no error occurred, a correctable error occurred, or a non-correctable error occurred. The ECC element <b>1224</b> moreover operates to correct correctable errors. Correct and corrected data is then routed to the decompressor <b>1226</b> via bus CDATA for decompression as described above. Non-correctable data is also passed to the decompressor <b>1226</b> via bus CDATA along with an indication of such. If an operationally critical portion of the configuration data is determined to be non-correctable, the decompressor <b>1226</b> may cause the core <b>1220</b> to shut down or otherwise flag the error.
One embodiment contemplates that the ECC element <b>1224</b> comprises one or more microcode routines that are executed to perform the ECC functions noted above.
Portions of the present invention and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, a microprocessor, a central processing unit, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Note also that the software implemented aspects of the invention are typically encoded on some form of program storage medium or implemented over some type of transmission medium. The program storage medium may be electronic (e.g., read only memory, flash read only memory, electrically programmable read only memory), random access memory magnetic (e.g., a floppy disk or a hard drive) or optical (e.g., a compact disk read only memory, or “CD ROM”), and may be read only or random access. Similarly, the transmission medium may be metal traces, twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. The invention is not limited by these aspects of any given implementation.
The particular embodiments disclosed above are illustrative only, and those skilled in the art will appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention, and that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as set forth by the appended claims.
Contents6
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| US2016314080A1 | United States of America | A1 | |
| US2016321004A1 | United States of America | A1 | |
| US2016321005A1 | United States of America | A1 | |
| US2016321192A1 | United States of America | A1 | |
| US9535847B2This record | United States of America | B2 | |
| US9710390B2 | United States of America | B2 | |
| US9715456B2 | United States of America | B2 | |
| US9715457B2 | United States of America | B2 | |
| US9727477B2 | United States of America | B2 | |
| US9727478B2 | United States of America | B2 | |
| US9740622B2 | United States of America | B2 | |
| CN104200837B | China | B | |
| EP2840508B1 | European Patent Office (EPO) | B1 | |
| EP2840491B1 | European Patent Office (EPO) | B1 |
105 transactions on the USPTO file
Allowed after 1 non-final rejection and 1 RCE.
- Non-final rejections
- 1
- Final rejections
- 0
- RCEs
- 1
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Supplemental ResponseSA.. | SA.. | |
| Paralegal or electronic terminal disclaimer approvedP574 | P574 | |
| Terminal Disclaimer FiledDIST | DIST | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Email NotificationEML_NTR | EML_NTR | |
| Application Is Now CompleteCOMP | COMP | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Application Dispatched from OIPEOIPE | OIPE | |
| FITF set to YES - revise initial settingFTFS | FTFS | |
| Cleared by OIPE CSRL194 | L194 | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE |
4 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS |
Numbers
- Publication
- 09535847
- Publication, DOCDB
- 9535847
- Publication, EPODOC
- US9535847
- Application
- 14635990
- Application, DOCDB
- 201514635990
- Application, EPODOC
- US201514635990
Titles
- English
- Apparatus and method for compression of configuration data
Classification
- CPC, 34
- G06F12/0875
- G11C17/16
- G06F3/0619
- G06F1/24
- G06F3/0632
- G06F3/0604
- G06F3/0688
- G06F9/4401
- G06F9/4403
- G06F3/0638
- G06F9/4405
- G06F3/0679
- G06F9/44505
- G06F11/1008
- G06F12/0646
- G06F12/0692
- G06F12/0802
- G06F12/0806
- G06F11/1068
- G11C17/18
- G11C29/802
- G06F12/12
- G06F2212/1008
- G06F2212/1012
- G06F2212/1032
- G06F12/0811
- G06F2212/452
- G06F12/084
- G06F2212/453
- G06F2212/601
- G06F12/128
- G06F2212/62
- G06F2212/283
- G11C29/52
- IPC, 12
- G06F13 12
- G11C17 18
- G11C7 00
- G11C8 00
- G06F12 08
- G11C17 16
- G06F3 06
- G06F9 44
- G06F9 445
- G06F12 06
- G11C29 00
- G06F11 10
- USPC, 1
- 001001000