Nova Patents
EP2840508A2

Apparatus and method for extended cache correction

Abstract

An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

EP2840508A2, drawing sheet 1
Sheet 1 of 10

Term

7.2 yearsto projected expiry

Projected expiry 19 November 2033, counted from filing; an application has no term until it is granted.

  1. Priority
  2. Filed
  3. Published
  4. Today
  5. Projected expiry

21 claims: 3 independent, 18 dependent

  1. 1
    An apparatus for providing configuration data to an integrated circuit, the apparatus comprising:a semiconductor fuse array, disposed on a die, into which is programmed the configuration data, said semiconductor fuse array comprising: a first plurality of semiconductor fuses, configured to store compressed cache correction data;a cache memory, disposed on said die;and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array and said cache memory, and is configured to access said semiconductor fuse array upon power-up/reset, to decompress said compressed cache correction data, and to distribute decompressed cached correction data to initialize said cache memory.
  2. 8
    An apparatus for providing configuration data to an integrated circuit, the apparatus comprising:a multi-core microprocessor, comprising: a semiconductor fuse array, disposed on a die, into which is programmed the configuration data, said semiconductor fuse array comprising: a first plurality of semiconductor fuses, configured to store compressed cache correction data;a cache memory, disposed on said die;and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array and said cache memory, and is configured to access said semiconductor fuse array upon power-up/reset, to decompress said compressed cache correction data, and to distribute decompressed cached correction data to initialize said cache memory.
  3. 15
    A method for providing configuration data to an integrated circuit, the method comprising:first disposing a semiconductor fuse array on a die, said first disposing comprising: storing compressed cache correction data in a first plurality of semiconductor fuses;second disposing a cache memory on the die;and third disposing a plurality of cores on the die, wherein each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory;via each of the plurality of cores, accessing the semiconductor fuse array upon power-up/reset, decompressing the compressed cache correction data, and distributing decompressed cached correction data to initialize the cache memory.
Independent claims3