US8312307B2

Systems and methods for reducing power consumption during communication between link partners

Summary by NHIP

Active Idle Ethernet Controller

The Ethernet controller alternates between active and low power states to reduce energy consumption during data transmission and reception. It signals link partners to enter specific low power modes, waits for predefined periods, and then resumes operations at negotiated speeds using 10GBASE-T or 1000BASE-T PHYs.

Claim Score by NHIP

Read claim 11, the broadest

Abstract

US8312307B2, drawing sheet 1 — Sheet 1 of 7

Term

3.6 yearsleft in the term

Expires 14 May 2030, including 919 days of term adjustment.

37 claims: 4 independent, 33 dependent

1
An Ethernet controller, comprising:at least one Media Access Controller (MAC);at least one interface to at least one PHY;and circuitry arranged to, when operational: cause generation of a signal for a first link partner signaling a first low power state;enter the first low power state, the first low power state to cause a reduction in power consumed by transmit circuitry during the first low power state;cause generation of a signal for the first link partner signaling end of the first low power state;await a first predefined period of time;after the first predefined period of time, cause transmission, in a first active power state, of at least one Ethernet data frame to the first link partner, the first active power state being a higher power consumption state of the transmit circuitry than the first low power state;receive an indication of a signal of the first link partner signaling a second low power state;enter the second low power state, the second low power state to cause a reduction in power consumed by receive circuitry during the second low power state;receive an indication of a signal of the first link partner signaling end of the second low power state;and enter a second active power state, the second active power state being a higher power consumption state of the receive circuitry than the second low power state and after a second predefined period of time, receive at least one Ethernet data frame from the first link partner.
11
Broadest claimClaim Score 43, average(NHIP)A system comprising:network controller circuitry arranged to, when operational: cause generation of a signal for a first link partner signaling a first low power state;cause generation of a signal for the first link partner signaling end of the first low power state;await a first predefined period of time;after the first predefined period of time, cause transmission of at least one Ethernet data frame to the first link partner;receive indication of a signal from a the first link partner signaling a second low power state;receive indication of a signal from the first link partner indicating end of the second low power state;and after a second predefined period of time, receive at least one Ethernet data frame from the first link partner;wherein the network controller circuitry comprises receive circuitry and transmit circuitry.
24
A method, comprising, at a network controller:causing generation of a signal for a first link partner signaling a first low power state;causing entering of the first low power state, the first low power state to cause a reduction in power consumed by the transmit circuitry during the first low power state;causing generation a signal for the first link partner signaling end of the first low power state;causing awaiting a first predefined period of time;after the first predefined period of time, causing transmission, in a first active power state, of at least one Ethernet data frame to the first link partner, the first active power state being a higher power consumption state of the transmit circuitry than the first low power state;receiving an indication of a signal of the first link partner signaling a second low power state;causing entering of the second low power state, the second low power state to cause a reduction in power consumed by the receive circuitry during the second low power state;receiving an indication of a signal of the first link partner signaling end of the second low power state;and causing entering a second active power state, the second active power state being a higher power consumption state of the receive circuitry than the second low power state and after a second predefined period of time, receive at least one Ethernet data frame.
35
An article comprising a non-transitory storage medium having stored thereon instructions that when executed by a processor results in the following:causing generation of a signal for a first link partner signaling a first low power state;causing entering of the first low power state, the first low power state to cause a reduction in power consumed by the transmit circuitry during the first low power state;causing generation a signal for the first link partner signaling end of the first low power state;causing awaiting a first predefined period of time;after the first predefined period of time, causing transmission, in a first active power state, of at least one Ethernet data frame to the first link partner, the first active power state being a higher power consumption state of the transmit circuitry than the first low power state;receiving an indication of a signal of the first link partner signaling a second low power state;causing entering of the second low power state, the second low power state to cause a reduction in power consumed by the receive circuitry during the second low power state;receiving an indication of a signal of the first link partner signaling end of the second low power state;and causing entering a second active power state, the second active power state being a higher power consumption state of the receive circuitry than the second low power state and after a second predefined period of time, receive at least one Ethernet data frame.

Independent claims4

41 paragraphs in 4 sections, as filed

FIELD

The present disclosure relates to Ethernet communications, and, more particularly, to energy efficient Ethernet using active/idle toggling.

BACKGROUND

Current Ethernet solutions either remain operating at a given speed, e.g. 1000BASE-T, regardless of the bandwidth utilization, and thus consume more power than necessary, or they require software drivers to drop the link and auto-negotiate to a new, lower speed to save power, but losing link for several seconds in the process making that option unsuitable for many applications. IEEE 802.3 Working Group has recently formed an Energy-Efficient Ethernet (EEE) Task Force, officially named 802.3az, to define a solution for reducing the average power consumption of Ethernet by addressing the issues noted above with current solutions. So far there have been two proposals to the IEEE Task Force for EEE, both of which recommend rate-shifting to track the bandwidth utilization demand. Rate-shifting, as proposed by the EEE Task Force, is a technique where the Ethernet communication speed may be up-shifted or down-shifted, depending on bandwidth demand. For example, during periods of low demand, the speed may be shifted down from a fast communication speed to a slower communication speed (e.g., 1000BASE-T to 100BASE-TX). As demand increases, the speed may be shifted up.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which:

<figref idrefs="DRAWINGS">FIG. 1</figref> depicts a graph of power vs. time consistent with one exemplary embodiment of the present disclosure;

<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a system embodiment consistent with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 3</figref> depicts a flowchart of exemplary data transmission operations consistent with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 4</figref> depicts a flowchart of exemplary data reception operations consistent with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 5A</figref> depicts a power profile graph according to a rate-shifting Ethernet communications technique; and

<figref idrefs="DRAWINGS">FIG. 5B</figref> depicts a power profile graph consistent with the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.

DETAILED DESCRIPTION

Generally, this disclosure describes an energy-efficient Ethernet communications approach. In at least one embodiment described herein, an Ethernet controller may be configured to operate in an active power state to transmit or receive data packets (when available) at a maximum available link speed. The maximum available link speed (e.g., 1000BASE-T (GbE), 10 GBASE-T, etc.) may be determined by a negotiation between the Ethernet controller and a link partner coupled to the Ethernet controller. Once the data packets are transmitted or received, the Ethernet controller may be configured to operate in an idle power state to reduce energy consumption. The “idle power state”, as used herein, may be defined as a power state that is sufficient to maintain an open link with the link partner, but insufficient to transmit or receive data. In other words, the “idle power state”, as used herein, is a threshold power consumption state that is below a power consumption state to transmit at least one data packet, while maintaining the Ethernet communications link between the Ethernet controller and the link partner. The “active power state”, as used herein, may include an “active data transmission power state” defined as a power state to transmit data at a maximum available link speed, and an “active data receive power state” defined as a power state to receive data at a maximum available link speed.

<figref idrefs="DRAWINGS">FIG. 1</figref> depicts a graph 100 of power vs. time consistent with one exemplary embodiment of the present disclosure. In this embodiment, data packets 102a, 102b, 102c may be transmitted or received in a burst fashion at a maximum active power state 104 (e.g., a maximum available link speed). When data packets are available to be transmitted or received, an Ethernet controller (not shown in this Figure) may toggle power between an idle power state 108 and an active state 104. In this example, the active power state 104 is a power state associated with the maximum available data transmission or reception speed. The idle power state 108 is a power state that is sufficient to maintain an open link with the link partner, but insufficient to transmit or receive data. The idle power state 108, in this example, represents a power consumption that is slightly larger than an off state 106 and significantly lower than the active power state 104.

During a transition from idle power state 108 to active power state 104, there may be a first delay period 110. Likewise, during a transition between the active power state 104 to the idle power state 108, there may be a second delay period 112. The idle interval 114 between packet bursts (e.g., between burst 102a and 102b) may be based on bandwidth considerations and/or the amount of data available in a data buffer.

<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a system embodiment 200 consistent with the present disclosure. The system 200 includes a host system 202 and an Ethernet controller 220. The host system 202 may include a host processor 204, chipset circuitry 206 and system memory 208. The host processor 204 may include one or more processor cores and may be configured to execute system software 210. System software 210 may include, for example, operating system code 212 (e.g., OS kernel code) and local area network (LAN) driver code 214. LAN driver code 214 may be configured to control, at least in part, the operation of the Ethernet controller 220 operation, as will be described in greater detail below. System memory 208 may include I/O memory buffers 216 configured to store one or more data packets that are to be transmitted by, or received by, Ethernet controller 220. Chipset circuitry 206 may generally include “North Bridge” circuitry (not shown) to control communication between the processor 204, Ethernet controller 220 and system memory 208. Also, chipset circuitry 206 may include “South Bridge” circuitry (not shown) to control I/O communications between the host system 202 and the Ethernet controller 220. “South Bridge” circuitry may include I/O bus circuitry which may comply, or is compatible, with PCI-Express communications protocol to provide communications between chipset circuitry 206 and the Ethernet controller 220.

Ethernet controller 220 may be logically and/or physically divided into a transmit path 221A and a receive path 221B. The Ethernet controller may generally include Ethernet media access control (MAC) circuitry 222 and physical interface (PHY) circuitry 224. MAC circuitry 222 may include transmit MAC circuitry 222A configured to assemble data to be transmitted into frames, or packets, that include destination and source addresses along with network control information and error detection hash values. MAC circuitry 222 may also include receive MAC circuitry 222B configured to remove data from received frames and place the data in system memory 208. PHY circuitry 224 may include encoding circuitry 240A configured to encode data packets and decoding circuitry 240B configured to decode data packets. Encoding circuitry 240A and decoding circuitry 240B may collectively be embodied as a processor (for example, a digital signal processor) configured to perform analog-to-digital and digital-to-analog conversion, encoding and decoding of data, analog parasitic cancellation (for example, cross talk cancellation), and recovery of received data. PHY circuitry 224 may also include transmit (Tx) circuitry 226 configured to transmit one or more data packets and receive (Rx) circuitry 228 configured to receive one or more data packets. Rx circuitry 228 may include phase lock loop circuitry (PLL, not shown) configured to coordinate timing of data reception. The PHY circuitry 224 may be coupled to an Ethernet communications link 230. The Ethernet communications link 230 may comprise, for example, a media dependent interface which may include, for example Category 6 (Cat6) Ethernet cable.

Transmit MAC circuitry 222A may include a controllable clock input 242 and a controllable power input 244. Clock input 242 may generally include a clock signal that controls the clocking of the MAC circuitry 222A. Power input 244 may generally include a power supply signal to supply power to one or more components of the MAC circuitry 222A. Similarly, Receive MAC circuitry 222B may include a controllable clock input 246 and a controllable power input 248. Clock input 246 may generally include a clock signal that controls the clocking of the MAC circuitry 222B. Power input 248 may generally include a power supply signal to supply power to one or more components of the MAC circuitry 222B. Encoding circuitry 240A may include a controllable clock input 254 and a controllable power input 256, and decoding circuitry 240B may include a controllable clock input 258 and a controllable power input 260. Transmit circuitry 226 may include a controllable clock input 262 and a controllable power input 264. In one embodiment, clocking of the transmit path 221A and receive path 221B may be independently controlled. Also, in one embodiment, the power of transmit path 221A and receive path 221B may be independently controlled.

The Ethernet controller 220 may be configured to exchange commands and data with a link partner 232, via communications link 230. “Link partner” as used herein, means any device that is configured to communicate with the Ethernet controller 220 using an Ethernet communications protocol. In at least one embodiment, the link partner 232 may include a switch, bridge, router and/or other Ethernet controller (which may be associated with a host system similar to host system 202) that may be configured and operate in a manner consistent with the description of the Ethernet controller 220 provided herein.

Ethernet controller 220 may be configured to transmit at least one data packet to the link partner 232, or receive at least one data packet from the link partner 232. As stated, the Ethernet controller 220 may be configured to operate, at least in part, in an idle power state and an active power state. In one embodiment, to transition into the idle state from the active data transmission power state, the Ethernet controller 220 may be configured to control the clock input 242, 254 and/or 262. To transition into the idle power state from an active data reception power state, the Ethernet controller 220 may be configured to control the clock input 246 and/or 258. To that end, the clock inputs 242, 254, 262, 246 and/or 258 may be gated (clock gating) to turn the clock signal OFF to the corresponding circuitry.

To permit asymmetric power management, the clock inputs of the transmit path circuitry may be controlled independently of the clock inputs of the receive path circuitry. This may allow, for example, the circuitry in that transmit path 221A to be in the idle power state while the circuitry in the receive path 221B is in the active state (or, vice-versa). Clock gating, as used herein, may provide a mechanism to achieve idle power state, as defined herein, in which the power consumption of the circuitry that is clock gated is sufficient to maintain an open link with the link partner 232 (via communications link 230), but insufficient for the Ethernet controller 220 to transmit or receive data. To transition from the idle power state to the active power state, the Ethernet controller 220 may be configured to turn the clock signals 242, 254, 262, 246 and/or 258 to an ON state to permit, for example, the Ethernet controller 220 to transmit and/or receive data.

Operations of the Ethernet controller 220 during data transmission and data reception, in conjunction with other features of the system of <figref idrefs="DRAWINGS">FIG. 2</figref>, are described below:

Tx Active Transition

As stated, the Ethernet controller 220 may be configured to transition, at least in part, from an idle power state to an active data transmission power state to transmit data. To that end, the LAN driver code 214, as may be executed by host processor 204, may be configured to determine the presence of at least one data packet, as may be stored in the I/O memory buffer 216, to be transmitted. The driver 214 may generate a transmit active control signal to control the Ethernet controller 220 to transition from the idle power state into an active data transmission power state. The clock signals 242 may be applied to the transmit MAC circuitry 222A, and clock signals 254 and 262 may be applied to the encoding circuitry 240A and transmit circuitry 226, respectively. If the link partner 232 is configured in a similar manner, transmit circuitry 226 may be configured to generate a receive active control signal to “wake up” the corresponding receive circuitry and MAC circuitry of the link partner 232 in order to prepare the link partner 232 to receive data from the Ethernet controller 220. After a specified delay period (e.g., delay period 110 depicted in <figref idrefs="DRAWINGS">FIG. 1</figref>), the Ethernet controller 220 may begin to transmit data to the link partner 232.

Tx Idle Transition

As stated, the Ethernet controller 220 may be configured to transition from an active data transmission power state to an idle power state. To that end, the LAN driver code 214, as may be executed by host processor 204, may be configured to determine that there are no data packets ready for transmission, for example, by monitoring the I/O memory buffer 216, to determine if the buffer is empty. The driver 214 may generate an idle control signal to control the Ethernet controller 220 to transition from the active data transmission power state into the idle power state. The clock signal 242 may be gated to the MAC circuitry 222A to permit the MAC circuitry 222A to drop to an idle power consumption mode. Likewise, clock signals 254 and/or 262 may be gated to the encoding circuitry 240A and/or transmit circuitry 226, respectively, to permit the encoding circuitry 240A and/or the transmit circuitry 226 to drop to an idle power consumption mode. If the link partner 232 is configured in a similar manner, transmit circuitry 226 may be configured to generate a receive idle control signal to transition the corresponding decoding circuitry and MAC circuitry of the link partner 232 into an idle power state.

Rx Active Transition

The Ethernet controller 220 may also be configured to transition, at least in part, from an idle power state to an active data reception power state to receive data from the link partner 232. To that end, the link partner 232 may generate a receive active control signal to the receive circuitry 228. To that end, while the decoding circuitry 240B and the receive MAC circuitry 222B may each be in an idle power state, the receive circuitry 228 may be in an active power state so that link 230 between the PHY circuitry 224 and the link partner 232 remains open. The receive active control signal generated by the link partner 232 may comprise a burst signal that can be received and recognized by the receive circuitry 228. In response thereto, the PHY circuitry 224 may transition the decoding circuitry 240B from an idle power state to an active power state, and PHY circuitry 224 may also generate a receive active control signal to transition the receive MAC circuitry 222B from an idle power state to the active power state. To that end, the clock signals 258 and 246 may be applied (e.g., ungated) to the encoding circuitry 240B and MAC circuitry 222B, respectively, to permit the MAC circuitry 222B and decoding circuitry 240B to receive data from the link partner 232. After a defined delay period (e.g., delay period 110 depicted in <figref idrefs="DRAWINGS">FIG. 1</figref>), the Ethernet controller 220 may begin to receive data from the link partner 232. The data may be stored in the buffer memory 216.

Rx Idle Transition

As stated, the Ethernet controller 220 may be configured to transition, at least in part, from an active data reception power state to an idle power state. To that end, PHY circuitry 224 may be configured to receive a receive idle control signal from the link partner 232. In response thereto, the PHY circuitry 224 may transition the decoding circuitry 240B from an active power state to the idle power state (which, as noted above, may include clock gating of the decoding circuitry 240B). PHY circuitry 224 may also generate a receive idle control signal to transition the receive MAC circuitry 222B from an active data reception power state to the idle power state.

The control signals exchanged between the Ethernet controller 220 and the link partner 232, as described above, may include, for example, control frames generated by respective PHY circuitry that include encoded signals to transition to the active power state or the idle power state. Alternatively, the control signals may comprise analog burst signals having predefined characteristics that may be interpreted by respective PHY circuitry as control signals to transition into the active power state or the idle power state. Further alternatively, such control signals may be generated by MAC circuitry 222 in the form of, for example, header or footer data within a data packet.

<figref idrefs="DRAWINGS">FIG. 3</figref> depicts a flowchart 300 of exemplary data transmission operations consistent with the present disclosure. Operations may include determining if data packets are in memory and available for transmissions 302. Operations may also include generating a transmit active control signal to transition an Ethernet controller, at least in part, from an idle power state to an active data transmission power state 304. If a link partner, coupled to the Ethernet controller is similarly configured, operations may also include generating a receive active control signal to the link partner to cause the link partner to transition, at least in part, from an idle power state to an active data reception power state 306. Operations may also include transmitting data packets to the link partner using a maximum negotiated speed 308. Once the data packets are transmitted, operations may further include generating an idle control signal to transition the Ethernet controller from the active data transmission power state to the idle power 310. Again, if the link partner is similarly configured, operations may also include generating a receive idle control signal to the link partner to cause the link partner to transition from the active data reception power state to the idle power state 312.

<figref idrefs="DRAWINGS">FIG. 4</figref> depicts a flowchart 400 of exemplary data reception operations consistent with the present disclosure. Operations may include receiving, by an Ethernet controller, a receive active control signal from a link partner 402. Operations may also include transitioning, at least in part and in response to the receive active control signal, the Ethernet controller from an idle power state to an active data reception power state 404. Operations may also include receiving, by the Ethernet controller, data packets from the link partner 406. The data packets may be stored in memory 408. Operations may also include receiving, by the Ethernet controller, a receive idle control signal from the link partner 410. Operations may also include transitioning, at least in part and in response to the receive idle control signal, the Ethernet controller from the active data reception power state to the idle power state 412.

The foregoing description of idle power state in connection with an Ethernet controller offer significant power savings over other approaches. <figref idrefs="DRAWINGS">FIG. 5A</figref> depicts a power profile graph 502 according to a rate-shifting Ethernet communications technique, and <figref idrefs="DRAWINGS">FIG. 5B</figref> depicts a power profile graph 504 consistent with the present disclosure. In general, power consumption (energy consumption) may be expressed as the area under the power curve, i.e.,

<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><msubsup><mo>∫</mo><mrow><mi>t</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>1</mn></mrow><mrow><mi>t</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow></msubsup><mo>⁢</mo><mrow><mrow><mi>power</mi><mo>⁡</mo><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>⁢</mo><mstyle><mspace width="0.2em" height="0.2ex" /></mstyle><mo>⁢</mo><mrow><mo>ⅆ</mo><mi>t</mi></mrow></mrow></mrow></math></maths>

Average power may be defined as energy consumption over a given time interval. As shown, the power profile 502 of the rate-shifting technique starts at a first power level 506 where data transmission or reception is possible but at a relatively low bandwidth, for example 1/10th or 1/100th the maximum rate, and, based on increased bandwidth utilization or other considerations, increases power to a second higher level 508 for faster data transmission or reception. Thus, the energy consumption is defined as both the area under region 506 and under region 508. In contrast, the power profile 504 according to the present disclosure, data is transmitted or received at a maximum available speed, as depicted as the area in regions 510 and 511. Once data is transmitted or received, the power is reduced to the idle power state 108. The average power utilized by the rate shifting technique is greater than the average power utilized by the active/idle toggle technique of the present disclosure, especially when long-term usage is considered. Unexpectedly, the applicant herein has determined that while the operating power is greater at the fastest available speed, total energy consumption is reduced, by completing the transmission more quickly and transitioning to the idle power state after data transmission or reception.

The foregoing examples are described in reference to power gating of one or more components of the Ethernet controller to achieve an idle power state. In other embodiments, additionally or as an alternative to clock gating, the Ethernet controller may also be configured to discontinue power (e.g., power gating) to the MAC circuitry 222 and/or the PHY circuitry 224. While power gating may achieve the appropriate idle power state as defined herein, this technique may cause an additional delay between idle to active transition.

Ethernet controller 220 may also include I/O bus circuitry (not shown) to provide I/O communications between the Ethernet controller 220 and the chipset circuitry 206 (such bus circuitry may comply with the aforementioned PCI-Express communications protocol). Ethernet controller may also include MAC/PHY interface circuitry (not shown) configured to provide I/O communications between the MAC circuitry 220 and the PHY circuitry 224 (which may include, for example SGMII or XAUI).

Memory 208 and/or memory associated with the Ethernet controller 220 (not shown) may comprise one or more of the following types of memory: semiconductor firmware memory, programmable memory, non-volatile memory, read only memory, electrically programmable memory, random access memory, flash memory, magnetic disk memory, and/or optical disk memory. Either additionally or alternatively, memory 208 and/or memory associated with the Ethernet controller 220 (not shown) may comprise other and/or later-developed types of computer-readable memory. Embodiments of the methods described herein may be implemented in a computer program that may be stored on a storage medium having instructions to program a system to perform the methods. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software modules executed by a programmable control device.

The Ethernet communications protocol, described herein, may be capable permitting communication using a Transmission Control Protocol/Internet Protocol (TCP/IP). The Ethernet protocol may comply or be compatible with the Ethernet standard published by the Institute of Electrical and Electronics Engineers (IEEE) titled “IEEE 802.3 Standard”, published in March, 2002 and/or later versions of this standard.

As used herein, a “PHY” may be defined as an object and/or circuitry used to interface to one or more devices, and such object and/or circuitry may be defined by one or more of the communication protocols set forth herein. The PHY may comprise a physical PHY comprising transceiver circuitry to interface to the applicable communication link. The PHY may alternately and/or additionally comprise a virtual PHY to interface to another virtual PHY or to a physical PHY. PHY circuitry 224 may comply or be compatible with, the aforementioned IEEE 802.3 Ethernet communications protocol, which may include, for example, 100BASE-TX, 100BASE-T, 10GBASE-T, 10GBASE-KR, 10GBASE-KX4/XAUI, 40 GbE and or 100 GbE compliant PHY circuitry, and/or PHY circuitry that is compliant with an after-developed communications protocol.

“Circuitry”, as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Contents4

Every citation, both waysCites: the store holds 11 of 12

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Holt et al., "Observations and Thoughts on Rate Switching", Mar. 31, 2001, pp. 1-8.	Non-patent	–	Applicant
"IEEE Energy Efficient Ethernet Study Group", Unapproved Minutes, Orlando, FL, Mar. 13-15, 2006, 10 pages.	Non-patent	–	Applicant
Nordman, Bruce, "Energy Efficient Ethernet: Outstanding Questions", IEEE 802 interim meeting, Monterey, California, Jan. 15-16, 2007, pp. 1-10.	Non-patent	–	Applicant
Nordman, Bruce, "Energy Efficient Ethernet: Outstanding Questions-Update: Mar. 2007", IEEE 802 interim meeting, Orlando, Florida, Mar. 13-15, 2007, pp. 1-5.	Non-patent	–	Applicant
Nordman, Bruce, "EEE Savings Estimates", IEEE 802 Plenary Meeting, San Francisco, Jul. 18, 2007, 9 pages.	Non-patent	–	Applicant
Nordman, Bruce, "EEE Savings Estimates", May 25, 2007, pp. 1-11.	Non-patent	–	Applicant
Nordman, Bruce, "Energy Efficient Ethernet: Outstanding Questions", Mar. 12, 2007, 3 pages.	Non-patent	–	Applicant
Nordman, Bruce, "Energy Efficient Ethernet: Outstanding Questions", Mar. 19, 2007, 3 pages.	Non-patent	–	Applicant
Paxson, Vern, "Some Perspectives on the Perfomance Impact of Link-Speed Switching Outages", Jul. 18, 2007, 10 pages.	Non-patent	–	Applicant
Powell et al., "Technical Considerations and Possible Solution Sets for EEE", IEEE 802.3 Energy Efficient Ethernet Study Group Interim Meeting, Broadcom, May 2007, pp. 1-7.	Non-patent	–	Applicant
Thompson, Geoff, "0-Base-T Possibilities", Presented to Energy Efficient Ethernet Study Group, Jul. 2007, 10 pages.	Non-patent	–	Applicant
Woodruff, "10GEEE-Time to Switch", Mar. 2007, pp. 1-8.	Non-patent	–	Applicant
Woodruff et al., "Efficiency and EEE-Technical Feasibility", May 29, 2007, pp. 1-15.	Non-patent	–	Applicant
Zimmerman, George, "Considerations for Technical Feasibility of EEE with 10GBASE 10GBASE-T", Mar. 7, 2007, pp. 1-10.	Non-patent	–	Applicant
"Magic Packet Technology", AMD, Publicaiton No. 20213, Rev: A, Amendment/0, Nov. 1995, pp. 1-6.	Non-patent	–	Applicant
Zimmerman et al., "Update on Technical Feasibility of EEE with 10GBASE 10GBASE-T", Solarfare Communication, Jul. 16, 2007, pp. 1-9.	Non-patent	–	Applicant
Bennett, Mike, "IEE 802.3 Energy Efficient Ethernet Study Group", Agenda and general information, San Francisco, California, Jul. 2007, pp. 1-31.	Non-patent	–	Applicant
Barnette et al., "Speed Switching without Communication Interruption", VITESSE, Prepared for the IEEE 802.3 Study Group, pp. 1-15.	Non-patent	–	Applicant
Barrass, Hugh, "IEEE Backplane Architecture", IEEE 802.3az EEE Task Force, Vancouver, British Columbia, Mar. 2009, pp. 1-10.	Non-patent	–	Applicant
Kasturia, "Generating the EEE Draft", 10 pages.	Non-patent	–	Applicant
Koenen, "Conditions for Backploane PHY EEE Transitions", HP, IEEE 802.3az, Nov. 2007, pp. 1-10.	Non-patent	–	Applicant
Law, "IEEE P802.3az Wait Time (Tw) From a System Design Perspective", IEEE P802.3az, IEEE Task Force, Version 3.0, pp. 1-18.	Non-patent	–	Applicant
Law, "IEEE 802.3 Clause 30 Management, MIB, Registers and Function", IEEE P802.3az, Energy-efficient Ethernet Task Force, Plenary Week Meeting, Nov. 2007, pp. 1-13.	Non-patent	–	Applicant
Nedevschi et al., "Reducing Network Energy Consumption via Sleeping and Rate-Adaptation", 12 pages.	Non-patent	–	Applicant
Parnaby, "10GBASE-T Parameter Values", 1 page.	Non-patent	–	Applicant
Powell, "A Gigabit "Subset PHYSubset PHY" Approach for 10GBASE for 10GBASE-T Energy Efficient Ethernet", BROADCOM, IEEE 802.3az EEE, Nov. 2007, 11 pages.	Non-patent	–	Applicant
Ratnasamy et al., "Reducing Network Energy Consumption Via Sleeping and Rate-Adaptation", pp. 1-29.	Non-patent	–	Applicant
Diab, Wael W., "Energy Efficient Ethernet and 802.1", IEEE 802 Plenary, Altanta, GA, Nov. 16, 2007, 23 pages.	Non-patent	–	Applicant
Hays, Robert, "ACtive/Idle Toggling with 0BASE-x for Energy Efficient Ethernet", IEEE 802.3az Task Force, Nov. 2007, pp. 1-22.	Non-patent	–	Applicant
Teener, Michael D., "Joint ITU-T/IEEE Workshop on Carrier-class Ethernet", AudioNideo Bridging for Home Networks, IEEE 802.1 AV Bridging Task Group, Geneva, May 31, 2007-Jun. 1, 2007, 35 pages.	Non-patent	–	Applicant
Taich et al., "Alert Signal Proposal for 10GBASE-T FEE ", Energy Efficient Ethernet (802.3az), Seoul, Korea, Sep. 2007, pp. 1-7.	Non-patent	–	Applicant
Thompson, Geoff, "Another Piece of EEE", An additional requirement for Energy Efficient Ethernet, Atlanta, Nov. 2007, 7 pages.	Non-patent	–	Applicant
Woodruff et al., "10GBASE T EEE Proposal xLPI", Aquantia, pp. 1-11.	Non-patent	–	Applicant
Zimmerman et al., "Deep Sleep Idle Concept for PHYs", Energy Efficient Ethernet, Solarflare Communication, Nov. 6, 2007, pp. 1-14.	Non-patent	–	Applicant
Barrass, Hugh, "EEE control protocol proposal", IEEE 802.3az EEE Task Force, Atlanta, Georgia, Nov. 2007, pp. 1-11.	Non-patent	–	Applicant
Bennett, Mike, "IEEE 802.3az Energy Efficient Ethernet", Open Questions for the Task Force, IEEE Plenary Meeting, Atlanta, GA, Nov. 2007, pp. 1-13.	Non-patent	–	Applicant
Diminico, Chris, "Physical Layer Considerations for Link Speed Transitions", EEE Study Group, pp. 1-8.	Non-patent	–	Applicant
"Broad Market Potential", IEEE interim meeting, Geneva, CH, May 2007, pp. 1-5.	Non-patent	–	Applicant
"Energy Efficient Ethernet Call Call-For For-Interest summary and Motion", IEEE 802.3 Working Group, Dallas, TX, Nov. 16, 2006, pp. 1-8.	Non-patent	–	Applicant
Bennett, Mike, "IEEE 802.3 Energy Efficient Ethernet Study Group", Agenda and general Information, Monterey, CA, Jan. 2007, pp. 1-25.	Non-patent	–	Applicant
Bennett, Mike, "IEEE 802.3 Energy Efficient Study Group", Agenda and general information, Orlando, FL, Mar. 2007, pp. 1-26.	Non-patent	–	Applicant
Bennet, Mike, "IEEE 802.3 Energy Efficient Ethernet Study Group", Agenda and general information, Ottawa, ON, Apr. 2007, pp. 1-27.	Non-patent	–	Applicant
Bennet, Mike, "IEEE 802.3 Energy Efficient Ethernet Study Group", Agenda and general information, Geneva, Switzerland, May 2007, pp. 1-31.	Non-patent	–	Applicant
"IEEE Energy Efficient Ethernet Study Group", Unapproved Minutes, Ottawa, ON, Canada, Apr. 17-18, 2007, 5 pages.	Non-patent	–	Applicant
Barrass, Hugh, "Energy Efficient Ethernet Objectives & 5 Criteria", A strawman to spur discussion and drive towards consensus, IEEE 802.3 Energy Efficient Ethernet, Monterey, CA, Jan. 2007, pp. 1-12.	Non-patent	–	Applicant
Barrass, Hugh, "Energy Efficient Ethernet Setting the bar", A system developer's view of neew PHY proposals, IEEE 802.3 Energy Efficient Ethernet, Orlando, Florida, Mar. 2007, pp. 1-7.	Non-patent	–	Applicant
Barrass, Hugh, "Energy Efficient Ethernet Beyond the PHY", Power savings in networked systems, IEEE 802.3 Energy Efficient Ethernet, Geneva, Switzerland, May 2007, pp. 1-12.	Non-patent	–	Applicant
Barrass, Hugh, "Energy Efficient Ethernet Transparent-not invisible", Some important considerations for management of EEE, IEEE 802.3 Energy Efficient Ethernet, San Francisco, Jul. 2007, pp. 1-8.	Non-patent	–	Applicant
Bennett, Mike, "IEEE 802.3 Energy Efficient Ethernet Study Group, " Server Bandwidth Utilization plots, Orlando, FL, Mar. 2007, pp. 1-13.	Non-patent	–	Applicant
Booth, Brad, "802.3 Standards Development Lessons Learned", AMCC, Jan. 2007, pp. 1-19.	Non-patent	–	Applicant
Chadha et al., "Feasibility of 1000-Base-T RPS Restart", Vitesse, IEEE 802.3 EEE SG, Interim Meeting, Apr. 2007, pp. 1-9.	Non-patent	–	Applicant
Chadha et al., "10BT Amplitude Optimization", Vitesse, IEEE 802.3 EEE SG, Interim Meeting, Apr. 2007, pp. 1-5.	Non-patent	–	Applicant
Chalupsky et al., "A Brief Tutorial on Power Management in Computer Systems", Intel Corporation, Mar. 11, 2007, pp. 1-28.	Non-patent	–	Applicant
Christensen, Ken, "Rapid PHY Selection (RPS): A Performance Evaluation of Control Policies Policies", IEEE 802.3 EEE Study Group, Monterey CA Jan. 15, 2007, pp. 1-45.	Non-patent	–	Applicant
Christensen, Ken "Rapid PHY Selection (RPS): Emulation and Experiments using PAUSE", IEEE 802.3 Eee Study Group, Orlando, FL, Mar. 13, 2007, pp. 1-16.	Non-patent	–	Applicant

Showing 100 of 110

14 members in 4 offices

This recordMember, by publication datePriority claim

Priority claims2

Priority claims
Document	Office	Kind	Date
93632707	United States of America	A	2007-11-07
US20070936327	–	–	–

Members14

Family members, oldest first
Document	Office	Kind
US2009119524A1	United States of America	A1	2009-05-07
WO2009061880A2	World Intellectual Property Organization (WIPO)	A2	2009-05-14
WO2009061880A3	World Intellectual Property Organization (WIPO)	A3	2009-07-09
EP2210368A2	European Patent Office (EPO)	A2	2010-07-28
CN101855865A	China	A	2010-10-06
US8312307B2This record	United States of America	B2	2012-11-13
CN102843239A	China	A	2012-12-26
US2013039363A1	United States of America	A1	2013-02-14
EP2210368A4	European Patent Office (EPO)	A4	2013-10-30
US8839015B2	United States of America	B2	2014-09-16
US2015046731A1	United States of America	A1	2015-02-12
EP2210368B1	European Patent Office (EPO)	B1	2015-07-29
US9489033B2	United States of America	B2	2016-11-08
CN102843239B	China	B	2017-09-08

90 transactions on the USPTO file

Allowed after 2 non-final rejections, 1 final rejection and 1 RCE.

Non-final rejections: 2
Final rejections: 1
RCEs: 1
Appeals: 0

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Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2023-12-06	Payment of Maintenance Fee, 12th Year, Large EntityM1553	M1553
2020-04-30	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2017-04-13	Email NotificationEML_NTR	EML_NTR
2017-04-13	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2017-04-11	Correspondence Address ChangeC.AD	C.AD
2015-04-03	Email NotificationEML_NTR	EML_NTR
2015-04-03	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2015-04-02	Correspondence Address ChangeC.AD	C.AD
2012-11-13	Recordation of Patent Grant MailedPGM/	PGM/
2012-11-13	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2012-10-25	Email NotificationEML_NTR	EML_NTR
2012-10-24	Issue Notification MailedAllowedWPIR	WPIR
2012-10-12	Dispatch to FDCD1935	D1935
2012-10-12	Application Is Considered Ready for IssuePILS	PILS
2012-10-08	Issue Fee Payment VerifiedN084	N084
2012-10-08	Issue Fee Payment ReceivedIFEE	IFEE
2012-07-18	Electronic ReviewELC_RVW	ELC_RVW
2012-07-18	Email NotificationEML_NTF	EML_NTF
2012-07-18	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2012-07-15	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2012-07-12	Examiner's Amendment CommunicationEX.A	EX.A
2012-07-06	Information Disclosure Statement consideredIDSC	IDSC
2012-07-06	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-07-06	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-05-29	Date Forwarded to ExaminerFWDX	FWDX
2012-05-24	Information Disclosure Statement consideredIDSC	IDSC
2012-05-24	Information Disclosure Statement consideredIDSC	IDSC
2012-05-24	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-05-24	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-05-24	Response after Non-Final ActionA...	A...
2012-05-24	Request for Extension of Time - GrantedXT/G	XT/G
2012-05-24	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-05-24	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-01-24	Electronic ReviewELC_RVW	ELC_RVW
2012-01-24	Email NotificationEML_NTF	EML_NTF
2012-01-24	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2012-01-13	Non-Final RejectionNon-final rejectionCTNF	CTNF
2011-11-28	Information Disclosure Statement consideredIDSC	IDSC
2011-11-28	Information Disclosure Statement consideredIDSC	IDSC
2011-11-28	Information Disclosure Statement consideredIDSC	IDSC
2011-11-28	Electronic Information Disclosure StatementEIDS.	EIDS.
2011-11-28	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-11-28	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-11-28	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-11-28	Date Forwarded to ExaminerFWDX	FWDX
2011-11-28	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2011-11-27	Information Disclosure Statement consideredIDSC	IDSC
2011-11-27	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-11-27	Electronic Information Disclosure StatementEIDS.	EIDS.
2011-11-27	Request for Continued Examination (RCE)RCEX	RCEX
2011-11-27	Workflow - Request for RCE - BeginBRCE	BRCE
2011-10-31	Email NotificationEML_NTR	EML_NTR
2011-10-31	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2011-10-26	Correspondence Address ChangeC.AD	C.AD
2011-08-26	Electronic ReviewELC_RVW	ELC_RVW
2011-08-26	Email NotificationEML_NTF	EML_NTF
2011-08-26	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2011-08-22	Final RejectionFinal rejectionCTFR	CTFR
2011-06-15	Date Forwarded to ExaminerFWDX	FWDX
2011-06-10	Information Disclosure Statement consideredIDSC	IDSC
2011-06-10	Response after Non-Final ActionA...	A...
2011-06-10	Request for Extension of Time - GrantedXT/G	XT/G
2011-06-10	Electronic Information Disclosure StatementEIDS.	EIDS.
2011-06-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-01-11	Electronic ReviewELC_RVW	ELC_RVW
2011-01-11	Email NotificationEML_NTF	EML_NTF
2011-01-11	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2011-01-06	Non-Final RejectionNon-final rejectionCTNF	CTNF
2010-08-20	Information Disclosure Statement consideredIDSC	IDSC
2010-08-20	Electronic Information Disclosure StatementEIDS.	EIDS.
2010-08-20	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2010-07-15	Case Docketed to Examiner in GAUDOCK	DOCK
2009-07-29	Information Disclosure Statement consideredIDSC	IDSC
2009-07-29	Electronic Information Disclosure StatementEIDS.	EIDS.
2009-07-29	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2009-05-08	Email NotificationEML_NTR	EML_NTR
2009-05-07	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2009-02-02	Case Docketed to Examiner in GAUDOCK	DOCK
2008-05-21	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2008-03-26	Application Dispatched from OIPEOIPE	OIPE
2008-02-08	Sent to Classification ContractorPGPC	PGPC
2008-02-08	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2008-02-08	Application Is Now CompleteCOMP	COMP
2008-02-01	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2008-02-01	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2007-12-03	Filing ReceiptFLRCPT.O	FLRCPT.O
2007-12-03	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2007-11-16	Cleared by OIPE CSRL194	L194
2007-11-07	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2007-11-07	Initial Exam Team nnIEXX	IEXX

6 legal events, as the office reported them to INPADOC

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Events

Legal events, newest first
	Event	Code
2023-12-06	Maintenance fee paymentMAFP	MAFP
2020-04-30	Maintenance fee paymentMAFP	MAFP
2016-04-29	Fee paymentFPAY	FPAY
2014-12-04	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2012-10-24	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2008-02-01	AssignmentAS	AS