Power saving techniques in computing devices

PRIORITY CLAIMS

The present application claims priority to U.S. Provisional Patent Application Ser. No. 61/916,498 filed on Dec. 16, 2013 and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is incorporated herein by reference in its entirety.

The present application also claims priority to U.S. Provisional Patent Application Ser. No. 62/019,073 filed on Jun. 30, 2014 and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to power saving techniques in computing devices.

II. Background

Computing devices are common within modem society. Ranging from small, mobile computing devices, such as a smart phone or tablet, to large server farms with numerous blades and memory banks, these devices are expected to communicate across myriad networks while providing various other base functions. While desktop devices and servers are generally immune to concerns about power consumption, mobile devices constantly struggle to find a proper balance between available functions and battery life. That is, as more functions are provided, power consumption increases, and battery life is shortened. Servers may likewise have power consumption concerns when assembled in large server farms.

Concurrent with power consumption concerns, improvements in network communications have increased data rates. For example, copper wires have been replaced with higher bandwidth fiber optic cables, and cellular networks have evolved from early Advanced Mobile Phone System (AMPS) and Global System for Mobile Communications (GSM) protocols to 4G and Long Term Evolution (LTE) protocols capable of supporting much higher data rates. As the data rates have increased, the need to be able to process these increased data rates within computing devices has also increased. Thus, earlier mobile computing devices may have had internal buses formed according to a High Speed Inter-Chip (HSIC) standard, universal serial bus (USB) standard (and particularly USB 2.0), or universal asynchronous receiver/transmitter (UART) standard. However, these buses do not support current data rates.

In response to the need for faster internal buses, the peripheral component interconnect express (PCIe) standard, as well as, later generations of USB (e.g., USB 3.0 and subsequent versions) have been adopted for some mobile computing devices. However, while PCIe and USB 3.0 can handle the high data rates currently being used, usage of such buses results in excessive power consumption and negatively impacts battery life by shortening the time between recharging events.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset. By holding or accumulating the data at a source processor in this fashion, unnecessary transitions between low power states and active states on the PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on the expiration of the downlink timer (with or without expiration of the uplink timer), accumulated data transfer may be initiated based on expiration of just an uplink accumulation timer. The uplink accumulation timer may be within a host or a device associated with the interconnectivity bus.

In another alternate aspect, initiation of the data transfer may be based on reaching a predefined threshold for a byte accumulation limit counter. The byte accumulation limit counter is not mutually exclusive relative to the other counters and may operate as an override mechanism for one of the other accumulation timers. Use of such an override may be useful in situations where a sudden burst of data arrives that would exceed buffer space and/or bus bandwidth. Likewise, instead of a byte counter, a packet size counter or a “total number of packets” counter may be used to cover situations where numerous packets or a particularly large packet is delivered by the network.

In further aspects of the present disclosure, the timers may be overridden by other factors or parameters. Such an override is alluded to above with the byte accumulation limit counters and the total number of packets counter, which causes data transfers independently of the timers. Other parameters may also override the timers, such as the presence of low latency traffic (e.g., control messages), synchronizing the uplink and downlink data transfers, or low latency quality of service requirements. When such traffic is present, an interrupt or other command may be used to initiate data transfers before expiration of a timer. Still other factors may override the timers, such as an indication that a device or host is not in an automatic polling mode.

In this regard in one aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem timer. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until expiration of the modem timer. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

In another aspect, a method of controlling power consumption in a computing device is disclosed. The method comprises holding data received by a modem processor from a remote network until expiration of a downlink timer. The method also comprises passing the data received by the modem processor to an application processor over an interconnectivity bus. The method also comprises holding application data generated by an application associated with the application processor for until receipt of the data from the modem processor or expiration of an uplink timer, whichever occurs first.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor. The mobile terminal also comprises an application timer. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until expiration of the application timer. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem byte accumulation limit counter. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until a predefined threshold of bytes has been reached by the modem byte accumulation limit counter. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

With regards to another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem packet counter. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until a predefined threshold of packets has been reached by the modem packet counter. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor. The mobile terminal also comprises an application byte counter. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until a predefined threshold of bytes has been reached by the application byte counter. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor and an application packet counter. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until a predefined threshold of packets has been reached by the application packet counter. The mobile terminal comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold the modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

With regards to another aspect, a method is disclosed. The method comprises starting an application timer at an application processor. The method also comprises accumulating data at the application processor until expiration of the application timer. The method comprises sending the accumulated data from the application processor to a modem processor across an interconnectivity bus. The method further comprises holding modem processor data at the modem processor until receipt of the accumulated data from the application processor.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem timer. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until expiration of the modem timer. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until the modem processor pulls data from the application processor after transmission of the modem processor to application processor data.

BRIEF DESCRIPTION OF THE FIGURES

<figref idref="DRAWINGS">FIG. <b>1</b>A</figref> is a simplified view of a mobile computing device operating with remote networks;

<figref idref="DRAWINGS">FIG. <b>1</b>B</figref> is a simplified view of a mobile terminal operating with remote networks;

<figref idref="DRAWINGS">FIG. <b>1</b>C</figref> is an expanded block diagram view of the mobile terminal of <figref idref="DRAWINGS">FIG. <b>1</b>B</figref> with an interconnectivity bus illustrated;

<figref idref="DRAWINGS">FIG. <b>2</b></figref> is a block diagram of the mobile terminal of <figref idref="DRAWINGS">FIG. <b>1</b>B</figref>;

<figref idref="DRAWINGS">FIG. <b>3</b></figref> is an exemplary time versus link power graph in a conventional computing device;

<figref idref="DRAWINGS">FIG. <b>4</b></figref> is a flowchart of an exemplary process for achieving power savings in the mobile terminal of <figref idref="DRAWINGS">FIG. <b>1</b>B</figref>;

<figref idref="DRAWINGS">FIG. <b>5</b></figref> is an exemplary time versus link power graph in a mobile computing device using the process of <figref idref="DRAWINGS">FIG. <b>4</b></figref>;

<figref idref="DRAWINGS">FIG. <b>6</b></figref> is a flowchart of another exemplary process for achieving power savings in the mobile computing device;

<figref idref="DRAWINGS">FIG. <b>7</b></figref> is an exemplary time versus link power graph in the mobile computing device using the process of <figref idref="DRAWINGS">FIG. <b>6</b></figref>;

<figref idref="DRAWINGS">FIG. <b>8</b></figref> is a flowchart of an exemplary process that uses a byte counter to control data accumulation;

<figref idref="DRAWINGS">FIG. <b>9</b></figref> is a flowchart of an exemplary process that uses a packet counter to control data accumulation;

<figref idref="DRAWINGS">FIG. <b>10</b></figref> is a flowchart of a consolidated accumulation process with overrides illustrated from a downlink priority perspective;

<figref idref="DRAWINGS">FIG. <b>11</b></figref> is a continuation of the flowchart of <figref idref="DRAWINGS">FIG. <b>10</b></figref>; and

<figref idref="DRAWINGS">FIG. <b>12</b></figref> is a simplified flowchart of a consolidated accumulation process with overrides illustrated from an uplink priority perspective.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset. By holding or accumulating the data at a source processor in this fashion, unnecessary transitions between low power states and active states on the PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on the expiration of the downlink timer (with or without expiration of the uplink timer), accumulated data transfer may be initiated based on expiration of just an uplink accumulation timer. The uplink accumulation timer may be within a host or a device associated with the interconnectivity bus.

In another alternate aspect, initiation of the data transfer may be based on reaching a predefined threshold for a byte accumulation limit counter. The byte accumulation limit counter is not mutually exclusive relative to the other counters and may operate as an override mechanism for one of the other accumulation timers. Use of such an override may be useful in situations where a sudden burst of data arrives that would exceed buffer space and/or bus bandwidth. Likewise, instead of a byte counter, a packet size counter or a “total number of packets” counter may be used to cover situations where numerous packets or a particularly a large packet is delivered by the network.

In further aspects of the present disclosure, the timers may be overridden by other factors or parameters. Such an override is alluded to above with the byte accumulation limit counters and the total number of packets counter, which causes data transfers independently of the timers. Other parameters may also override the timers, such as the presence of low latency traffic (e.g., control messages), synchronizing the uplink and downlink data transfers, or low latency quality of service requirements. When such traffic is present, an interrupt or other command may be used to initiate data transfers before expiration of a timer. Still other factors may override the timers, such as an indication that a device or host is not in an automatic polling mode.

While it is contemplated that the power saving techniques of the present disclosure are used in mobile terminals, such as smart phones or tablets, the present disclosure is not so limited. Accordingly, <figref idref="DRAWINGS">FIGS. <b>1</b>A and <b>1</b>B</figref> illustrate computing devices coupled to remote networks via modems that may implement exemplary aspects of the power saving techniques of the present disclosure. In this regard, <figref idref="DRAWINGS">FIG. <b>1</b>A</figref> illustrates a computing device <b>10</b> coupled to a network <b>12</b>, which, in an exemplary aspect, is the internet. The computing device <b>10</b> may include a housing <b>14</b> with a central processing unit (CPU) (not illustrated), therein. A user may interact with the computing device <b>10</b> through a user interface formed from input/output elements such as a monitor <b>16</b> (sometimes referred to as a display), a keyboard <b>18</b>, and/or a mouse <b>20</b>. In some aspects, the monitor <b>16</b> may be incorporated into the housing <b>14</b>. While a keyboard <b>18</b> and mouse <b>20</b> are illustrated input devices, the monitor <b>16</b> may be a touchscreen display, which may supplement or replace the keyboard <b>18</b> and mouse <b>20</b> as an input device. Other input/output devices may also be present as is well understood in conjunction with desktop or laptop style computing devices. While not illustrated in <figref idref="DRAWINGS">FIG. <b>1</b>A</figref>, the housing <b>14</b> may also include a modem, therein. The modem may be positioned on a network interface card (NIC), as is well understood. Likewise, a router and/or an additional modem may be external to the housing <b>14</b>. For example, the computing device <b>10</b> may couple to the network <b>12</b> through a router and a cable modem, as is well understood. However, even where such external routers and modems are present, the computing device <b>10</b> is likely to have an internal modem to effectuate communication with such external routers and modems.

In addition to the computing device <b>10</b>, exemplary aspects of the present disclosure may also be implemented on a mobile terminal, which is a form of computing device as that term is used herein. In this regard, an exemplary aspect of a mobile terminal <b>22</b> is illustrated in <figref idref="DRAWINGS">FIG. <b>1</b>B</figref>. The mobile terminal <b>22</b> may be a smart phone, such as a SAMSUNG GALAXY™ or APPLE iPHONE®. Instead of a smart phone, the mobile terminal <b>22</b> may be a cellular telephone, a tablet, a laptop, or other mobile computing device. The mobile terminal <b>22</b> may communicate with a remote antenna <b>24</b> associated with a base station (BS) <b>26</b>. The BS <b>26</b> may communicate with the public land mobile network (PLMN) <b>28</b>, the public switched telephone network (PSTN, not shown), or a network <b>12</b> (e.g., the internet), similar to the network <b>12</b> in <figref idref="DRAWINGS">FIG. <b>1</b>A</figref>. It is also possible that the PLMN <b>28</b> communicates with the internet (e.g., the network <b>12</b>) either directly or through an intervening network (e.g., the PSTN). It should be appreciated that most contemporary mobile terminals <b>22</b> allow for various types of communication with elements of the network <b>12</b>. For example, streaming audio, streaming video, and/or web browsing are all common functions on most contemporary mobile terminals <b>22</b>. Such functions are enabled through applications stored in the memory of the mobile terminal <b>22</b> and using the wireless transceiver of the mobile terminal <b>22</b>.

To effectuate functions, such as streaming video, data arrives from the remote antenna <b>24</b> at an antenna <b>30</b> of the mobile terminal <b>22</b>, as illustrated in <figref idref="DRAWINGS">FIG. <b>1</b>C</figref>. The data is initially processed at a mobile device modem (MDM) <b>32</b> of the mobile terminal <b>22</b> and passed to an application processor <b>34</b> by an interconnectivity bus <b>36</b>. In this context, the application processor <b>34</b> may be a host, and the MDM <b>32</b> may be a device as those terms are used in the PCIe standard. While exemplary aspects contemplate operating over a PCIe-compliant interconnectivity bus <b>36</b>, it is possible that the interconnectivity bus <b>36</b> may comply with High Speed Interconnect (HSIC), Universal Asynchronous Receiver/Transmitter (UART), universal serial bus (USB), or the like.

A more detailed depiction of the components of the mobile terminal <b>22</b> is provided with reference to <figref idref="DRAWINGS">FIG. <b>2</b></figref>. In this regard, a block diagram of some of the elements of the mobile terminal <b>22</b> of <figref idref="DRAWINGS">FIG. <b>1</b>B</figref> is illustrated. The mobile terminal <b>22</b> may include a receiver path <b>38</b>, a transmitter path <b>40</b>, the antenna <b>30</b> (mentioned above with reference to <figref idref="DRAWINGS">FIG. <b>1</b>C</figref>), a switch <b>42</b>, a modem processor <b>44</b>, and the application processor <b>34</b> (also introduced above in reference to <figref idref="DRAWINGS">FIG. <b>1</b>C</figref>). Optionally, a separate control system (not shown) may also be present with a CPU as is well understood. The application processor <b>34</b> and the modem processor <b>44</b> are connected by the interconnectivity bus <b>36</b>. The application processor <b>34</b> and/or the control system (if present) may interoperate with a user interface <b>46</b> and memory <b>48</b> with software <b>50</b> stored therein.

The receiver path <b>38</b> receives information bearing radio frequency (RF) signals from one or more remote transmitters provided by a base station (e.g., the BS <b>26</b> of <figref idref="DRAWINGS">FIG. <b>1</b>B</figref>). A low noise amplifier (not shown) amplifies the signal. A filter (not shown) minimizes broadband interference in the received signal. Down conversion and digitization circuitry (not shown) down converts the filtered, received signal to an intermediate or baseband frequency signal. The baseband frequency signal is then digitized into one or more digital streams. The receiver path <b>38</b> typically uses one or more mixing frequencies generated by the frequency synthesizer. The modem processor <b>44</b> may include a base band processor (BBP) (not shown) that processes the digitized received signal to extract the information or data bits conveyed in the signal. As such, the BBP is typically implemented in one or more digital signal processors (DSPs) within the modem processor <b>44</b> or as a separate integrated circuit (IC) as needed or desired.

With continued reference to <figref idref="DRAWINGS">FIG. <b>2</b></figref>, on the transmit side, the modem processor <b>44</b> receives digitized data, which may represent voice, data, or control information, from the application processor <b>34</b>, which it encodes for transmission. The encoded data is output to the transmitter path <b>40</b>, where it is used by a modulator (not shown) to modulate a carrier signal at a desired transmit frequency. An RF power amplifier (not shown) amplifies the modulated carrier signal to a level appropriate for transmission, and delivers the amplified and modulated carrier signal to the antenna <b>30</b> through the switch <b>42</b>. Collectively, the modem processor <b>44</b>, the receiver path <b>38</b>, and the transmitter path <b>40</b> form the MDM <b>32</b> of <figref idref="DRAWINGS">FIG. <b>1</b>C</figref> (sometimes also referred to as a wireless modem). While the MDM <b>32</b> is specifically described with relation to the RF signals associated with a cellular signal, the present disclosure is not so limited. For example, a wireless modem using other wireless protocols may also benefit from inclusion of aspects of the present disclosure. Thus, modems operating according to standards such as BLUETOOTH®, the various IEEE 802.11 standards, Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Long Term Evolution (LTE), and other wireless protocols may all use aspects of the present disclosure.

With continued reference to <figref idref="DRAWINGS">FIG. <b>2</b></figref>, a user may interact with the mobile terminal <b>22</b> via the user interface <b>46</b>, such as a microphone, a speaker, a keypad, and a display. Audio information encoded in the received signal is recovered by the BBP, and converted into an analog signal suitable for driving the speaker. The keypad and display enable the user to interact with the mobile terminal <b>22</b>. For example, the keypad and display may enable the user to input numbers to be dialed, access address book information, or the like, as well as monitor call progress information. The memory <b>48</b> may have the software <b>50</b> therein as noted above, which may effectuate exemplary aspects of the present disclosure.

In conventional mobile terminals that have a PCIe interconnectivity bus (i.e., the interconnectivity bus <b>36</b>), the PCIe standard allows the interconnectivity bus <b>36</b> to be placed into a sleep mode. While placing the interconnectivity bus <b>36</b> in a sleep mode generally saves power, such sleep modes do have a drawback in that they consume relatively large amounts of power as they transition out of the sleep mode. This power consumption is exacerbated because of the asynchronous nature of the PCIe interconnectivity bus <b>36</b>. That is, first data may arrive at the modem processor <b>44</b> for transmission to the application processor <b>34</b> at a time different than when the second data is ready to pass from the application processor <b>34</b> to the modem processor <b>44</b>. This problem is not unique to the PCIe interconnectivity bus <b>36</b>.

<figref idref="DRAWINGS">FIG. <b>3</b></figref> illustrates a time versus link power graph <b>52</b> that highlights how downlink data <b>54</b> may have a different transmission time than uplink data <b>56</b> within a given time slot <b>58</b>. In particular, the interconnectivity bus <b>36</b> (<figref idref="DRAWINGS">FIG. <b>2</b></figref>) begins in a sleep or low power mode and transitions up to an active power mode by transition <b>60</b> so that the downlink data <b>54</b> may be transmitted to the application processor <b>34</b>. However, the downlink data <b>54</b> may not occupy the entirety of the time slot <b>58</b>, and the interconnectivity bus <b>36</b> may return to a low power state. However, subsequently, but still within the same time slot <b>58</b>, the uplink data <b>56</b> from the application processor <b>34</b> is sent to the modem processor <b>44</b>. Accordingly, the interconnectivity bus <b>36</b> is again transitioned from the low power state to the active power state by a second transition <b>62</b>. In an exemplary aspect, the time slot <b>58</b> is approximately one millisecond long. Thus, if two transitions (i.e., <b>60</b>, <b>62</b>) from low power to active power occur every time slot <b>58</b>, then thousands of transitions <b>60</b>, <b>62</b> occur every second. Thousands of transitions <b>60</b>, <b>62</b> consume substantial amounts of power and reduce the battery life of the mobile terminal <b>22</b>.

Exemplary aspects of the present disclosure reduce the number of transitions (i.e., <b>60</b>, <b>62</b>) from low power to active power by synchronizing packet transmission from the modem processor <b>44</b> and the application processor <b>34</b>, which in turn allows the link to be maintained in a low power mode more efficiently since the communication on the link is consolidated to eliminate the second power state transition. In an exemplary aspect, the data (i.e., the modem data) from the modem processor <b>44</b> transmits first, and the data (i.e., the application data) from the application processor <b>34</b> is sent after arrival of the modem data and before the interconnectivity bus <b>36</b> can return to the low power state. The synchronization is done through the use of timers at the modem processor <b>44</b> and the application processor <b>34</b>. The timers may be longer than a time slot <b>58</b> of the interconnectivity bus <b>36</b>.

In a first exemplary aspect, the timer on the application processor <b>34</b> is longer than the timer on the modem processor <b>44</b>. The accumulation may be done on a per logical channel basis. The timer may be configurable by the application processor <b>34</b> using a mechanism suitable to the interconnectivity bus <b>36</b>. For example, on a fusion device using a modem host interface (MHI) over PCIe, the timer is maintained for every inbound MHI channel and the time value used by the timers shall be configured via a MHI command message or a PCIe memory mapped input/output (MMIO) device configuration register exposed via a base address register (BAR). The BAR is a PCIe standard defined mechanism by which a host maps the registers of a device into its virtual address map. For more information about MHI, the interested reader is referred to U.S. patent application Ser. No. 14/163,846, filed Jan. 24, 2013, which is herein incorporated by reference in its entirety. In other exemplary aspects, the timer on the modem processor <b>44</b> is longer than the timer on the application processor <b>34</b>. In still other exemplary aspects, counters may be used in place of timers. The counters may be bit counters, packet counters, packet size counters, or the like. In other exemplary aspects, use of such alternate counters may be combined with the timers. In still other exemplary aspects, other override criteria may allow for data to be sent before timer or counter expiration so as to reduce latency and/or satisfy the quality of service requirements. The present disclosure steps through each of these aspects in turn, beginning with the situation where there are two timers, and the application processor <b>34</b> has a timer that is longer than the timer of the modem processor <b>44</b>.

In this regard, <figref idref="DRAWINGS">FIG. <b>4</b></figref> illustrates an exemplary power saving process <b>70</b>. The process <b>70</b> begins with the interconnectivity bus <b>36</b> in a low power state (block <b>72</b>). The modem timer and the application timer are started (block <b>74</b>). The timers may be software stores in the modem processor <b>44</b> and the application processor <b>34</b> or may be physical elements, as desired. Data is generated by the application processor <b>34</b> and data is received from the network <b>12</b> by the modem processor <b>44</b>. The application data is held at the application processor <b>34</b> (block <b>76</b>), and the modem data is held at the modem processor <b>44</b> (block <b>78</b>) while the timers are running. As noted above, in an exemplary aspect, the time slot <b>58</b> of the interconnectivity bus <b>36</b> is one millisecond. In such an aspect, the modem timer may be approximately two to six milliseconds, and the application timer is three to seven milliseconds, or at least longer than the modem timer. The modem timer expires (block <b>80</b>). If modem data is present, the modem data is released by the modem processor <b>44</b> through the interconnectivity bus <b>36</b> to the application processor <b>34</b> (block <b>82</b>).

The mechanism for data transfer may be initiated and controlled by the modem processor <b>44</b> (i.e., the device). For example, on a fusion device using MHI over PCIe, the modem processor <b>44</b> may poll (read) the MHI channel Context Write Pointer to determine data buffers where downlink packets can be transferred. The application processor <b>34</b> updates the channel context data structure's Context Write Pointer field to point to the data transfer descriptors without ringing an Inbound channel doorbell. The modem processor <b>44</b> may poll for updates on the Context Write Pointer field as necessitated by downlink traffic. When the modem processor <b>44</b> runs out of buffers, i.e., a transfer ring is empty, and no buffers are present to transfer downlink data, the modem processor <b>44</b> may generate an event (e.g., an “out-of-buffer”) notification to the application processor <b>34</b>, followed by an interrupt. Upon receiving the event notification from the modem processor <b>44</b>, the application processor <b>34</b> shall provide data buffers by updating the channel Context Write Pointer and shall ring the Inbound channel doorbell.

After arrival of the modem data at the application processor <b>34</b>, the application processor <b>34</b> releases any application data that has been held at the application processor <b>34</b> and resets the application timer (block <b>84</b>). Note that the application timer can run on the modem processor <b>44</b> or the application processor <b>34</b>. As an alternative, the modem processor <b>44</b> may continue to pull the uplink data <b>56</b> from the application processor <b>34</b> until it detects no further downlink data <b>54</b> activity. That is, the modem processor <b>44</b> may intersperse pulling the uplink data <b>56</b> while receiving the downlink data <b>54</b>. If, however, no modem data is present at the modem processor <b>44</b> when the modem timer expires, the application timer continues (i.e., another millisecond) (block <b>86</b>). At the expiration of the application timer, the application processor <b>34</b> sends any held data to the modem processor <b>44</b> through the interconnectivity bus <b>36</b> (block <b>88</b>). The process then repeats by starting over (block <b>90</b>).

As noted above, the uplink timer (i.e., the application timer) is, in an exemplary aspect, designed to be longer than the downlink timer (i.e., the modem timer) to increase the uplink/downlink synchronization whenever the downlink timer expires. While holding data for an extra time slot adds some latency, the brief amount added is readily absorbed by the application processor <b>34</b>. Likewise, this latency is considered acceptable for the power savings. For example, by making the period of the modem timer twice the period of the time slot <b>58</b>, the number of low power to active power transitions is potentially halved. Likewise, by making the period of the application timer six times the period of the time slot <b>58</b>, the chance of being able to “piggyback” onto the active power state of the interconnectivity bus <b>36</b> caused by the modem data is increased, but still frequent enough that any uplink data <b>56</b> will still be sent in a timely fashion even if there is no downlink data <b>54</b> to trigger releasing the uplink data <b>56</b>. Similar logic can be extended to synchronize traffic from multiple processors (e.g., multiple application processors or modem processors such as a second modem processor) over the data link. In an exemplary aspect, the other processors may each have timer values higher (i.e., longer) than that of the downlink timer, and the processors can exchange their data availability information so that traffic on one processor can trigger the data transfer on other processors if there is data available to transfer.

<figref idref="DRAWINGS">FIG. <b>5</b></figref> illustrates a graph <b>100</b> where the uplink data <b>56</b> follows the downlink data <b>54</b> during an active period <b>102</b> of the interconnectivity bus <b>36</b> (<figref idref="DRAWINGS">FIG. <b>2</b></figref>). As illustrated, there is only one transition <b>104</b> from low power to active power per time slot <b>58</b>. Thus, by consolidating the data into a single active period <b>102</b>, the overall time that is spent in low power may be increased, thus resulting in power savings. Additionally, power spent transitioning from a low power to active power state is reduced by the elimination of the second transition <b>62</b>.

While it is conceivable that the uplink data <b>56</b> could be sent before the downlink data <b>54</b> (i.e., the application timer is shorter than the modem timer), such is generally not considered optimal because there are usually far more downlink packets than uplink packets. If this aspect is used, the application processor <b>34</b> may buffer uplink data packets into local memory prior to initiating transfer to the modem processor <b>44</b>. These accumulated packets are controlled via an uplink accumulation timer. If there are plural channels, then a timer may be applied to each channel independently. When the application processor <b>34</b> is unable to use or does not have an uplink timer, the modem processor <b>44</b> may be able to instantiate an uplink timer, and upon expiry of the uplink timer, will poll data from the application processor <b>34</b>. This exemplary aspect is explained in greater detail below with reference to <figref idref="DRAWINGS">FIGS. <b>6</b> and <b>7</b></figref>.

In this regard, <figref idref="DRAWINGS">FIG. <b>6</b></figref> illustrates an exemplary power saving process <b>110</b>. The process <b>110</b> begins with the interconnectivity bus <b>36</b> in a low power state (block <b>112</b>). The modem timer and the application timer are started (block <b>114</b>). The timers may be software stored in the modem processor <b>44</b> and the application processor <b>34</b> or may be physical elements as desired. Data is generated by the application processor <b>34</b> and data is received from the network <b>12</b> by the modem processor <b>44</b>. The application data is held at the application processor <b>34</b> (block <b>116</b>), and the modem data is held at the modem processor <b>44</b> (block <b>118</b>) while the timers are running. As noted above, in an exemplary aspect, the time slot <b>58</b> of the interconnectivity bus <b>36</b> is one millisecond. In such an aspect, the application timer may be approximately two milliseconds, and the modem timer is three milliseconds, or at least longer than the application timer. The application timer expires (block <b>120</b>). If application data is present, the application data is released by the application processor <b>34</b> through the interconnectivity bus <b>36</b> to the modem processor <b>44</b> (block <b>122</b>).

After arrival of the application data at the modem processor <b>44</b>, the modem processor <b>44</b> releases any modem data that has been held at the modem processor <b>44</b> and resets the modem timer (block <b>124</b>). Note that the application timer can run on the modem processor <b>44</b> or the application processor <b>34</b>. Likewise, the modem timer can run on the modem processor <b>44</b> or the application processor <b>34</b>.

With continued reference to <figref idref="DRAWINGS">FIG. <b>6</b></figref>, if no application data is present at the application processor <b>34</b> when the application timer expires, the modem timer continues (i.e., another millisecond) (block <b>126</b>). At the expiration of the modem timer, the modem processor <b>44</b> sends any held data to the application processor <b>34</b> through the interconnectivity bus <b>36</b> (block <b>128</b>). The process then repeats by starting over (block <b>130</b>).

As noted above, in this exemplary aspect, the uplink timer (i.e., the application timer) is, in an exemplary aspect, designed to be shorter than the downlink timer (i.e., the modem timer). While holding data for an extra time slot <b>58</b> adds some latency, the brief amount added is readily absorbed by the application processor <b>34</b>. Likewise, this latency is considered acceptable for the power savings. For example, by making the period of the application timer twice the period of the time slot <b>58</b>, the number of low power to active power transitions is lowered. Likewise, by making the period of the modem timer six times the period of the time slot <b>58</b>, the chance of being able to “piggyback” onto the active power state of the interconnectivity bus <b>36</b> caused by the application data is increased, but still frequent enough that any downlink data <b>54</b> will still be sent in a timely fashion even if there is no uplink data <b>56</b> to trigger releasing the downlink data <b>54</b>. Similar logic can be extended to synchronize traffic from multiple processors over the data link. In an exemplary aspect, the other processors may each have timer values higher (i.e., longer) than that of the uplink timer and the processors can exchange their data availability information so that traffic on one processor can trigger the data transfer on other processors if there is data available to transfer.

<figref idref="DRAWINGS">FIG. <b>7</b></figref> illustrates a graph <b>140</b> where the uplink data <b>56</b> precedes the downlink data <b>54</b> during an active period <b>142</b> of the interconnectivity bus <b>36</b>. As illustrated, there is only one transition <b>144</b> from low power to active power per time slot <b>58</b>. Thus, by consolidating the data into a single active period <b>142</b>, the overall time that is spent in low power may be increased, thus resulting in power savings. Additionally, power spent transitioning from a low power to active power state is reduced by the elimination of the second transition <b>62</b>.

In an exemplary aspect, the modem processor <b>44</b> may override and choose the minima from all configured values of each of the configurable parameters (like downlink or uplink accumulation timers, byte threshold, number of packets threshold, size of packet threshold, or the like) or downlink accumulation expiry timer values (e.g., from among the various channels) as the effective downlink accumulation timer expiry value. Intelligent modem processors <b>44</b> may also dynamically override or alter the downlink accumulation timer value depending on the downlink traffic pattern, and/or may adjust the downlink accumulation timer to achieve a desired quality of service (QoS) for data and/or to control traffic. A change of configuration can be triggered/controlled by the application processor <b>44</b> or any other processor in the system as well, via MHI control or QMI signaling (such as, for inter process signaling).

In addition to, or in place of, downlink and uplink timers, a byte accumulation limit counter may also be used by the modem processor <b>44</b> for downlink traffic and the application processor <b>34</b> for uplink traffic. This aspect may be advantageous in situations where there is a sudden burst of data pushed by the network or application. Note that this aspect is not mutually exclusive and may be implemented as an override mechanism for either downlink or uplink timers. For example, if the downlink accumulation timer is set relatively high to conserve power, a sudden burst of data may exceed the buffer capacity of the modem processor <b>44</b>, or if allowed to accumulate in memory of the modem processor <b>44</b>, this burst of data may exceed bus bandwidth allocations on the application processor <b>34</b>. The application processor <b>34</b> can determine and configure the maximum byte accumulation limit based on its bus bandwidth budget, and/or buffer size reserved for downlink data transfer. The modem processor <b>44</b> can also choose an internal byte accumulation limit based on the size of downlink buffer, and/or interconnect link data throughput. With the byte accumulation limit counters, the modem processor <b>44</b> can initiate downlink data transfer to the application processor <b>34</b> prior to downlink accumulation timer expiry, if and when the buffered data size exceeds the byte accumulation limit counter. Since both the modem processor <b>44</b> and the application processor <b>34</b> may have independent recommendations for byte accumulation limit counter, the modem processor <b>44</b> may select the minima of these two values to be the effective byte accumulation limit. Similar parameters may be maintained in the application processor <b>34</b> to trigger the uplink data <b>56</b> transfer immediately (i.e., overriding the uplink accumulation timer).

Instead of, or in addition to the byte accumulation limit counter, a number of packets limit counter may be used. In an exemplary aspect, the packet number limit counter may be of similar design, and can be employed to add number of packet counter limits instead of byte limits to cover cases where a large number of packets are delivered by the network or an application. Again, such a packet limit counter may also be present or associated with the application processor <b>34</b> or the modem processor <b>44</b>. Note, that the accumulation timers (uplink and/or downlink) and other configuration parameters like the number of accumulated packets threshold, accumulated bytes threshold, and the like, may be a function of LTE, HSPA, GERAN, or the like.

In still another exemplary aspect, the modem processor <b>44</b> or the application processor <b>34</b> may disable downlink or uplink accumulation in cases where there is a necessity to expedite message transfer, for example control messages (like flow control) or high QoS data traffic or low latency traffic, as determined by the modem processor <b>44</b> or the application processor <b>34</b>. Latency introduced by accumulation may not be tolerable for these traffic classes.

Returning to the data accumulation based on amounts of data instead of a strict process, <figref idref="DRAWINGS">FIGS. <b>8</b> and <b>9</b></figref> illustrate two exemplary aspects. In this regard, <figref idref="DRAWINGS">FIG. <b>8</b></figref> illustrates a process <b>150</b> illustrating a byte counter process. In particular, the process <b>150</b> begins with the interconnectivity bus <b>36</b> in a low power state (block <b>152</b>). The process <b>150</b> starts a modem byte counter and an application byte counter (block <b>154</b>). Data is held at the application processor <b>34</b> (block <b>156</b>) and the modem processor <b>44</b> (block <b>158</b>). A control system determines if the modem byte counter has exceeded a predefined threshold (block <b>160</b>) based on the amount of data that has been held or accumulated at the modem processor <b>44</b>.

With continued reference to <figref idref="DRAWINGS">FIG. <b>8</b></figref>, if the answer to block <b>160</b> is yes, then data is sent from the modem processor <b>44</b> to the application processor <b>34</b> (block <b>162</b>). After receipt of the data from the modem processor <b>44</b>, the application processor <b>34</b> sends data (if any) that has accumulated at the application processor <b>34</b> to the modem processor <b>44</b> (block <b>164</b>). Having cleared the accumulated data at both the modem processor <b>44</b> and the application processor <b>34</b>, the process starts over (block <b>166</b>).

With continued reference to <figref idref="DRAWINGS">FIG. <b>8</b></figref>, if the answer to block <b>160</b> is no, the control system determines if the data at the application byte counter has exceeded a predefined threshold (block <b>168</b>). If the answer to block <b>168</b> is no, the process <b>150</b> returns to block <b>156</b> and data continues to be held until a byte counter threshold is exceeded. If, however, the answer to block <b>168</b> is yes, then the data is sent from the application processor <b>34</b> to the modem processor <b>44</b> (block <b>170</b>). After receipt of the data from the application processor <b>34</b>, the modem processor <b>44</b> sends data (if any) to the application processor <b>34</b> (block <b>172</b>). Having cleared the accumulated data at both the modem processor <b>44</b> and the application processor <b>34</b>, the process <b>150</b> starts over (block <b>166</b>).

While a byte counter may be effective in managing latency, another exemplary aspect uses a packet counter. In this regard, <figref idref="DRAWINGS">FIG. <b>9</b></figref> illustrates a process <b>180</b> illustrating a byte counter process. In particular, the process <b>180</b> begins with the interconnectivity bus <b>36</b> in a low power state (block <b>182</b>). The process <b>180</b> starts a modem packet counter and an application packet counter (block <b>184</b>). Data is held at the application processor <b>34</b> (block <b>186</b>) and the modem processor <b>44</b> (block <b>188</b>). A control system determines if the modem packet counter has exceeded a predefined threshold (block <b>190</b>) based on the number of packets held or accumulated at the modem processor <b>44</b>.

With continued reference to <figref idref="DRAWINGS">FIG. <b>9</b></figref>, if the answer to block <b>190</b> is yes, then data is sent from the modem processor <b>44</b> to the application processor <b>34</b> (block <b>192</b>). After receipt of the packets from the modem processor <b>44</b>, the application processor <b>34</b> sends data (if any) that has accumulated at the application processor <b>34</b> to the modem processor <b>44</b> (block <b>194</b>). Having cleared the accumulated packets at both the modem processor <b>44</b> and the application processor <b>34</b>, the process <b>180</b> starts over (block <b>196</b>).

With continued reference to <figref idref="DRAWINGS">FIG. <b>9</b></figref>, if the answer to block <b>190</b> is no, the control system determines if the number of packets at the application packet counter has exceeded a predefined threshold (block <b>198</b>). If the answer to block <b>198</b> is no, the process <b>180</b> returns to block <b>186</b> and data continues to be held until a packet counter threshold is exceeded. If, however, the answer to block <b>198</b> is yes, then the data is sent from the application processor <b>34</b> to the modem processor <b>44</b> (block <b>200</b>). After receipt of the packets from the application processor <b>34</b>, the modem processor <b>44</b> sends data (if any) to the application processor <b>34</b> (block <b>202</b>). Having cleared the accumulated packets at both the modem processor <b>44</b> and the application processor <b>34</b>, the process <b>180</b> starts over (block <b>196</b>).

A similar process may be used, where instead of determining if a particular number of bytes or packets have been accumulated, the control system evaluates a size of packets or whether the system is running low in memory. Likewise, it should be appreciated that certain priority data (e.g., a control signal or other data requiring low latency) may be associated with a flag or other indicator that overrides the timers and/or counters of the present disclosure.

As noted above, it should be appreciated that the aspects of the present disclosure are not mutually exclusive and can be combined. The combinations are myriad in that a timer may be used at the application processor <b>34</b> with a byte counter at the modem processor <b>44</b> (or vice versa), the modem processor <b>44</b> works with a timer and a byte counter, while the application processor <b>34</b> just has a timer, and so on. In this regard, <figref idref="DRAWINGS">FIGS. <b>10</b>-<b>12</b></figref> are provided that illustrate how the timers and data accumulation counters may inter-operate. That is, <figref idref="DRAWINGS">FIGS. <b>10</b> and <b>11</b></figref> illustrate how the downlink timer (whether in the modem processor <b>44</b> or the application processor <b>34</b>) is used as the basis for data transmission (e.g., as illustrated in <figref idref="DRAWINGS">FIGS. <b>4</b> and <b>5</b></figref>), may be combined with the data accumulation counters, and is further modified by a high priority data override. <figref idref="DRAWINGS">FIG. <b>12</b></figref> illustrates a simplified process in which the uplink timer combined with the data accumulation counters is used as the basis for data transmission (e.g., as illustrated in <figref idref="DRAWINGS">FIGS. <b>6</b> and <b>7</b></figref>), modified by the data overrides.

In this regard, <figref idref="DRAWINGS">FIGS. <b>10</b> and <b>11</b></figref> illustrate a combined process <b>210</b> that begins at start (block <b>212</b>). The process <b>210</b> continues with the arrival of downlink (DL) data (e.g., a packet) (block <b>214</b>). The control system evaluates if there is any priority data, control messages, and/or other data that requires low latency (block <b>216</b>). If the answer to block <b>216</b> is no, then the control system determines if a byte threshold has been crossed (i.e., are there more than the threshold worth of bytes in the accumulator) (block <b>218</b>). If the answer to block <b>218</b> is no, then the control system determines if a number of packets threshold has been crossed (i.e., there are more than the threshold worth of packets in the accumulator) (block <b>220</b>). If the answer to block <b>220</b> is no, then the control system determines if the system is running low in memory (block <b>222</b>). If the answer to block <b>222</b> is no, then the control system ascertains if the downlink accumulation timer is running (block <b>224</b>). If the answer to block <b>224</b> is yes, then the downlink data continues to accumulate and no data transfer is initiated over the link (block <b>226</b>).

With continued reference to <figref idref="DRAWINGS">FIG. <b>10</b></figref>, if, however, the answer to block <b>224</b> is no, the downlink timer has expired, or if any of the overrides from block <b>216</b>, <b>218</b>, <b>220</b>, or <b>222</b> has been answered affirmatively, then the process <b>210</b> starts transfer of the accumulated data (including the current packet) over the link from the modem processor <b>44</b> (also sometimes referred to as modem (<b>44</b>) in the Figures) to the application processor <b>34</b> (also sometimes referred to as AP (<b>34</b>) in the Figures) (block <b>230</b>). The control system starts or restarts the downlink accumulation timer and sets the downlink accumulation timer to running (block <b>232</b>). The control system determines if the modem processor <b>44</b> is in an uplink (UL) polling mode (block <b>234</b>). If the answer to block <b>234</b> is no, then there is no uplink transfer (block <b>236</b>). If, however, the modem processor <b>44</b> is polling the uplink device, then, based on that polling, the control system determines if there is pending uplink data from the application processor <b>34</b> (block <b>238</b>). If there is pending data (i.e., the answer to block <b>238</b> is yes), then the application processor <b>34</b> starts data transfer to the modem processor <b>44</b> (block <b>240</b>). Once the data transfer is finished, or if there was no data at block <b>238</b>, the control system restarts the uplink accumulation timer (block <b>242</b>) and the process <b>210</b> returns to start <b>212</b>.

With continued reference to <figref idref="DRAWINGS">FIG. <b>10</b></figref>, after block <b>226</b>, the control system determines if the downlink timer has expired (block <b>244</b>). If the answer to block <b>244</b> is no, the control system determines if a new packet has arrived (block <b>246</b>). If the answer to block <b>246</b> is no, then the process <b>210</b> returns to block <b>244</b>. If a new packet has arrived, the process <b>210</b> returns to the start <b>212</b>. If the answer to block <b>244</b> is yes, the downlink timer has expired, the control system knows the downlink accumulation timer has expired (block <b>248</b>). At expiration of the downlink timer, the control system determines if there is any pending accumulated downlink data (block <b>250</b>). If there is data at block <b>250</b>, then the data is transferred at block <b>230</b>. If there is no data, then the downlink accumulation timer is set to “not running” (block <b>252</b>) and the process <b>210</b> goes to <figref idref="DRAWINGS">FIG. <b>11</b></figref>, element C. It should be appreciated that blocks <b>216</b>, <b>218</b>, <b>220</b>, and <b>222</b> are optional.

With reference to <figref idref="DRAWINGS">FIG. <b>11</b></figref>, the process <b>210</b> may continue from block <b>252</b>. At this point, the uplink accumulation timer has expired (block <b>254</b>). The uplink accumulation timer will expire if there is no downlink data since the uplink timer was restarted. The control system determines if there is any pending uplink data from the application processor <b>34</b> (block <b>256</b>). If the answer to block <b>256</b> is yes, then the application processor <b>34</b> starts the data transfer over the link from the application processor <b>34</b> to the modem processor <b>44</b> (block <b>258</b>). The control system then restarts the uplink accumulation timer (block <b>260</b>). If, however, the answer to block <b>256</b> is no, there is no data, the control system sends an event to the application processor <b>34</b> indicating the modem processor <b>44</b> is expecting a doorbell/interrupt for any pending or next packet submission (block <b>262</b>). That is, since there has been no data from the application processor <b>34</b> to the modem processor <b>44</b> since the previous poll time, then the modem processor <b>44</b> may go into an interrupt mode for uplink data and the modem processor <b>44</b> would expect the application processor <b>34</b> to send an interrupt whenever there was data pending at the application processor <b>34</b>. The control system then changes the state internally to reflect the same (block <b>264</b>).

With continued reference to <figref idref="DRAWINGS">FIG. <b>11</b></figref>, the modem processor <b>44</b> receives an interrupt or other indication from the application processor <b>34</b> indicating pending data in the transfer ring (block <b>266</b>). The control system then restarts the uplink accumulation timer and changes the state to indicate the uplink polling mode (block <b>268</b>). All the uplink data is processed (block <b>270</b>) and the process <b>210</b> starts over.

In another alternate aspect, there may be situations where the buffers of the application processor <b>34</b> may be full and there is no room for data from the modem processor <b>44</b>. In such an event, the application processor <b>34</b> may so inform the modem processor <b>44</b>, and the modem processor <b>44</b> may send an event to the application processor <b>34</b> to provide an interrupt signal to the modem processor <b>44</b> when there are free buffers.

<figref idref="DRAWINGS">FIG. <b>12</b></figref> is similar to <figref idref="DRAWINGS">FIGS. <b>10</b> and <b>11</b></figref>, in that it illustrates how overrides and data counters may be used in conjunction with an accumulation timer, but a process <b>280</b> of <figref idref="DRAWINGS">FIG. <b>12</b></figref> assumes that the uplink timer is shorter than the downlink timer (e.g., analogous to the aspect illustrated in <figref idref="DRAWINGS">FIGS. <b>6</b> and <b>7</b></figref>). The process <b>280</b> begins at start (block <b>282</b>). The process <b>280</b> continues with the arrival of uplink (UL) data (e.g., a packet) (block <b>284</b>). The control system evaluates if there is any priority data, control messages, and/or other data that requires low latency (block <b>286</b>). If the answer to block <b>286</b> is no, then the control system determines if a byte threshold has been crossed (i.e., are there more than the threshold worth of bytes in the accumulator) (block <b>288</b>). If the answer to block <b>288</b> is no, then the control system determines if a number of packets threshold has been crossed (i.e., there are more than the threshold worth of packets in the accumulator) (block <b>290</b>). If the answer to block <b>290</b> is no, then the control system determines if the system is running low in memory (block <b>292</b>). If the answer to block <b>292</b> is no, then the control system ascertains if the device is in an uplink polling mode (block <b>294</b>). If the answer to block <b>294</b> is yes, the device is in the polling mode, then the application processor <b>34</b> updates the internal data structure/context array with uplink data packet information that the device can pull and update write pointers accordingly (block <b>296</b>).

With continued reference to <figref idref="DRAWINGS">FIG. <b>12</b></figref>, if, however, the answer to block <b>294</b> is no, the device is not in an uplink polling mode, or if any of the overrides from blocks <b>286</b>, <b>288</b>, <b>290</b>, or <b>292</b> has been answered affirmatively, then the application processor <b>34</b> updates the internal data structure/context array with uplink data packet information that the device can pull and update write pointers accordingly (block <b>298</b>). The application processor <b>34</b> then rings the doorbell or otherwise interrupts the device to indicate the availability of uplink data (block <b>300</b>). The application processor <b>34</b> then sets the device state to the polling state (not the doorbell/event/interrupt mode) (block <b>302</b>), and the process repeats.

It should be appreciated that similar processes may be performed where both timers are in the application processor <b>34</b> or the modem processor <b>44</b> or are split between the respective processors <b>34</b>, <b>44</b>. Likewise, once a timer has expired, data can be pulled or pushed across the interconnectivity bus <b>36</b> based on polling, setting doorbell registers, or other technique.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.