Pre-drive circuit, capacitive load drive circuit and plasma display apparatus

BACKGROUND OF THE INVENTION

The present invention relates to a pre-drive circuit and a capacitive load drive circuit and to a plasma display apparatus using the same. More particularly, the present invention relates to an improvement in the timing of a drive signal by which a sustain discharge is caused.

The plasma display apparatus has been put to practical use as a flat display and is a thin display with high luminance. <figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing the general constitution of a conventional three-electrode AC-driven plasma display apparatus. As shown schematically, the plasma display apparatus comprises a plasma display panel (PDP) <b>1</b> consisting of two substrates between which a discharge gas is enclosed, each substrate having a plurality of X electrodes (X<b>1</b>, X<b>2</b>, X<b>3</b>, . . . , Xn) and a plurality of Y electrodes (Y<b>1</b>, Y<b>2</b>, Y<b>3</b>, . . . , Yn) arranged adjacently by turns, a plurality of address electrodes (A<b>1</b>, A<b>2</b>, A<b>3</b>, . . . , Am) arranged in the direction perpendicular to the X and Y electrodes and phosphors arranged at the crossings, an address driver <b>2</b> which applies an address pulse or the like to the address electrode, an X common driver <b>3</b> which applies a sustain discharge pulse or the like to the X electrodes, a scan driver <b>4</b> which applies a scan pulse or the like sequentially to the Y electrodes, a Y common driver <b>5</b> which supplies a sustain discharge pulse or the like, to be applied to the Y electrodes, to the scan driver <b>4</b>, and a control circuit <b>6</b> which controls each part, wherein the control circuit <b>6</b> has a display data control section <b>7</b> which further includes a frame memory and a drive control circuit <b>8</b> including a scan driver control section <b>9</b> and a common driver control section <b>10</b>. The X common driver <b>3</b> and the Y common driver <b>5</b> respectively include sustain circuits which output sustain pulses, and each sustain circuit has a sustain output element. As the plasma display apparatus is widely known, a detailed description about the whole apparatus is not given here but only the X common driver <b>3</b> and the Y common driver <b>5</b> relating to the present invention are described here. The X common driver, the scan driver and the Y common driver of the plasma display apparatus have been disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 2001-282181 and Japanese Unexamined Patent Publication (Kokai) No. 2002-351388. Japanese Unexamined Patent Publication (Kokai) No. 8-335863 has disclosed a power transistor drive circuit used in such a driver and an IC formed into a single chip by integrating the drive circuit.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram showing the general constitution of the power transistor drive circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 8-335863, and the whole is provided in an IC <b>11</b> as shown by the dotted line. In the plasma display apparatus, the power transistor drive IC in <figref idref="DRAWINGS">FIG. 2</figref> is used as a pre-drive circuit for driving a sustain output element. In the power transistor drive IC <b>11</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>, a high level input voltage HIN is amplified in an input amplifier circuit <b>21</b>, converted into a voltage referred to a high level reference voltage Vr in a high level shift circuit <b>22</b>, and output as a high level output voltage HO via an output amplifier circuit <b>23</b>. On the other hand, a low level input voltage LIN is amplified in an input amplifier circuit <b>24</b> and output as a low level output voltage LO after input into an output amplifier circuit <b>26</b> via a delay circuit <b>25</b> and amplified therein. Reference numbers <b>12</b> and <b>13</b> respectively denote input terminals of the high level input voltage HIN and the low level input voltage LIN, reference number <b>16</b> and <b>19</b> respectively denote output terminals of the high level output voltage HO and the low level output voltage LO, reference number <b>15</b> denotes a supply terminal of a high level supply voltage Vc, reference number <b>17</b> denotes a supply terminal of the high level reference voltage Vr, reference number <b>18</b> denotes a supply terminal of a low level supply voltage Vd, and reference number <b>20</b> denotes a ground terminal.

In the power transistor drive IC shown in <figref idref="DRAWINGS">FIG. 2</figref>, the delay circuit <b>25</b> serves to adjust the difference tdLH (HO) in the rise times between the high level input voltage HIN and the high level output voltage HO and the difference tdLH(LO) in the rise times between the low level input voltage LIN and the low level output voltage LO so that they are equal. Moreover, the delay circuit <b>25</b> also serves to adjust the difference tdHL(HO) in the fall times between the high level input voltage HIN and the high level output voltage HO and the difference tdHL(LO) in the fall times between the low level input voltage LIN and the low level output voltage LO so that they are equal. However, it is impossible for the delay circuit <b>25</b> to make tdLH(HO) and tdLH(LO) coincide with each other perfectly, and it is inevitable that a certain difference occurs. Similarly, it is also impossible to make tdHL(HO) and tdHL(LO) coincide with each other perfectly, and it is inevitable that a certain difference occurs.

When the power transistor drive IC shown in <figref idref="DRAWINGS">FIG. 2</figref> is used as a pre-drive circuit in a plasma display apparatus, sustain output elements such as a power MOSFET and an IGBT (Insulated Gate Bipolar Transistor) are connected to the output terminals <b>16</b> and <b>19</b>. In a plasma display apparatus (PDP apparatus), a sustain pulse is generated, by turning on/off a sustain output element, and is supplied to the X electrode and the Y electrode of a plasma display panel (PDP).

<figref idref="DRAWINGS">FIG. 3</figref> shows an example of a sustain circuit in a PDP apparatus, where the power transistor drive IC in <figref idref="DRAWINGS">FIG. 2</figref> is used as a pre-drive circuit <b>11</b>A and a pre-drive circuit <b>11</b>B of the sustain output elements. In <figref idref="DRAWINGS">FIG. 3</figref>, CU and CD denote the sustain output elements, and by turning on/off these output elements, a sustain pulse is supplied to the PDP corresponding to a capacitive load. In <figref idref="DRAWINGS">FIG. 3</figref>, an input signal CUI is input as a high level input voltage of the pre-drive circuit <b>11</b>A and supplied to the output element CU as a high level output voltage. On the other hand, an input signal CDI is input as a low level input voltage of the pre-drive circuit <b>11</b>A and supplied to the output element CD as a low level output voltage.

When the output element CU is turned on, a supply voltage Vs is supplied to the PDP via a diode D<b>1</b> and the output element CU (at this time the output element CD is off). When the output element CD is turned on, a ground (GND) voltage is supplied to the PDP via the output element CD (at this time the output element CU is off). On the other hand, the supply voltage of the pre-drive circuit <b>11</b>A for driving the output element CU (high level supply voltage maintained across a capacitor C<b>1</b>) is charged across the capacitor C<b>1</b> from a power supply Ve via a diode D<b>2</b>. The supply voltage of the pre-drive circuit <b>11</b>A for driving the output element CD (low level supply voltage maintained across a capacitor C<b>2</b>) is charged directly across the capacitor C<b>2</b> from the power supply Ve. In the circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, a sustain pulse is supplied to the PDP by turning on/off the output elements CU and CD alternately.

LU and LD in <figref idref="DRAWINGS">FIG. 3</figref> are power recovery output elements and the power supplied to the PDP through the CU and CD is reduced by turning on/off the LU and the LD. In <figref idref="DRAWINGS">FIG. 3</figref>, an output signal LUI is input as a high level input voltage of the pre-drive circuit and supplied to the output element LU as a high level output voltage. An input signal LDI is input as a low level input voltage of the pre-drive circuit and supplied to the output element LD as a low level output voltage.

When the output element LU is turned on, a middle point voltage Vp of capacitors C<b>5</b> and C<b>6</b> connected in series between the supply voltage Vs and the GND is supplied to the PDP via the output element LU, a diode D<b>4</b> and a coil L<b>1</b> (at this time, the output element LD is off). On the other hand, when the output element LD is turned on, the above-mentioned middle point voltage Vp is supplied to the PDP via a coil <b>2</b>, a diode D<b>5</b> and the output element LD (at this time, the output element LU is off). The supply voltage (high level supply voltage maintained across a capacitor C<b>3</b>) of the pre-drive circuit for driving the output element LU is charged across the capacitor C<b>3</b> from the power supply Ve via a diode D<b>3</b>. On the other hand, the supply voltage (low level supply voltage maintained across a capacitor C<b>4</b>) of the pre-drive circuit for driving the output element LD is charged across the capacitor C<b>4</b> directly from the power supply Ve. In the circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, the output element LU is turned on immediately before the sustain output element CU is turned on, and the output element LD is turned on immediately before the output element CD is turned on and, thus, the power loss caused by the CU and the CD is reduced.

In the circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, a switch SW<b>1</b> is turned on during the reset period of the plasma display apparatus and serves to supply a reset voltage Vw to the PDP via the output element CU.

In the pre-drive circuit using the power transistor drive IC shown in <figref idref="DRAWINGS">FIG. 2</figref>, the delay circuit <b>25</b> adjusts the difference tdLH(HO) in the rise times between the high level input voltage HIN and the high level output voltage HO and the difference tdLH(LO) in the rise times between the low level input voltage LIN and the low level output voltage LO so that they are equal. However, the high level shift circuit in the pre-drive circuit is not same as the delay circuit which delays time by the amount corresponding to the delay time in the circuit, and it is impossible to perfectly make the two circuits coincide with each other with respect to the delay characteristics including variations in elements and the temperature characteristic. As a result, it is inevitable that a difference occurs between tdLH(HO) and tdLH(LO).

When the pre-drive circuit, in which there is a difference between tdLH(HO) and tdLH(LO), is applied to the sustain circuit in the plasma display apparatus shown in <figref idref="DRAWINGS">FIG. 3</figref>, there is the possibility that the on/off timing of the output elements CU and CD deviates from the designed value. If the deviation of the timing occurs, there is the possibility that the output elements are turned on at the same time, therefore, a through current flows from CU to CD, and an over-current may destroy the elements.

Similarly, there is the possibility that the timing with which the power recovery output elements LU and LD are turned on deviates from the designed value. Because of the deviation of the timing, there is the possibility that the power recovery current at rise (current flowing through L<b>1</b>) and the power recovery current at fall (current flowing through L<b>2</b>) become unbalanced, therefore, the value of the middle point voltage Vp of the capacitors C<b>5</b> and C<b>6</b> deviates from the middle voltage and the power recovery operation is not carried out normally, and the power consumption may increase.

Further, there is a constitution in which a withstand voltage of an output element is reduced by using sustain pulses having the same absolute value but opposite polarities. However, control signals are signals which are referred to ground. Therefore, when a drive signal of a negative voltage is output from the above-mentioned pre-drive circuit, it is necessary that the low level reference voltage of the pre-drive circuit is changed to the negative sustain voltage and a level shift circuit is provided to convert an input voltage signal to a signal referred to the negative sustain voltage. As the level shift circuit and the above pre-drive circuit are different circuits, the above-mentioned same problem occurs.

In recent years, the plasma display apparatus is required to have an increased number of sustain pulses in a frame by decreasing a period of the sustain pulse (sustain period) in order to increase brightness. However, if the sustain period is reduced, the above-mentioned problems become more important.

SUMMARY OF THE INVENTION

The object of the present invention is to realize a pre-drive circuit in which the deviation of the timing of the high level output voltage and the low level output voltage is reduced and to prevent the destruction of the elements and the increase in power consumption in a capacitive load drive circuit and a plasma display apparatus using the same.

To realize the above-mentioned object, a pre-drive circuit according to the present invention comprises a plurality of drive systems with the same constitution having an input amplifier circuit, a high level shift circuit and an output amplifier circuit.

The delay circuit <b>25</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> has a circuit constitution simpler than that of the high level shift circuit <b>22</b> and the circuit size can be reduced. In the low level voltage drive system, it is not necessary to shift the amplified input power signal to a high level one, therefore, in the conventional pre-drive circuit (power transistor drive IC), a delay circuit was used to reduce the circuit size. However, the present inventors have found that this constitution brings about the above-mentioned problem.

If the pre-drive circuit of the present invention is used, no deviation of timing is caused because a plurality of drive systems having the same constitution are provided and the high level voltage drive system and the low level voltage drive system can be made to have the same constitution by using the high level shift circuit instead of the delay circuit. Therefore, if an IC using this pre-drive circuit is used, it is possible to precisely set the rise timing and the fall timing of the gate pulse for driving the output elements CU and CD to a desired situation. Because of this, the destruction due to the over-current caused by the simultaneous turning on of the CU and CD can be avoided.

If the pre-drive circuit of the present invention is used, it is possible to precisely set the rise timing and the fall timing of the gate pulse for driving the output elements LU and LD to a desired situation. Therefore, it is possible to reduce the change in the middle voltage Vp of the capacitors C<b>5</b> and C<b>6</b> owing to the unbalance between the power recovery (current flowing through L<b>1</b>) at the rise of the sustain pulse and the power recovery (current flowing through L<b>2</b>) at the fall of the sustain pulse. Because of this, the increase in power consumption caused by the abnormal power recovery operation can be prevented.

The level shift circuit shifts the input voltage in accordance with the reference supply voltage to be supplied thereto. Therefore, the level shift circuit making up the low level voltage drive system is supplied with a corresponding reference supply voltage. In the examples in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>, the reference supply voltage of the low level voltage drive system is the ground (GND) level but in a constitution to be described later, in which the high level output voltage and the low level output voltage have the same absolute value but opposite polarities, it is also possible to supply a positive reference supply voltage to one of the drive systems, and a negative reference supply voltage to the other drive system, by using the pre-drive circuit of the present invention.

It is desirable to form the plurality of drive systems on the same semiconductor chip, that is, to integrate them into an IC. Due to this, the similarity of the circuit characteristics of the two drive systems can be enhanced.

It is desirable to provide a supply voltage terminal for supplying the drive power supply of the input amplifier circuit of the plurality of drive systems separately from a supply voltage terminal for supplying the drive power supply of the output amplifier circuit of the plurality of drive systems.

It is also possible to provide a waveform processing circuit such as a Schmitt trigger circuit between each input voltage terminal and input amplifier circuit of the plurality of drive systems. In this case, it is necessary to supply another supply voltage to the waveform processing circuit, therefore, a power supply terminal for the waveform processing circuit is provided or a constant voltage circuit is provided which generates a supply voltage for the waveform processing circuit by converting the voltage supplied to the supply voltage terminal for the input amplifier circuit.

It is desirable that a number of drive systems provided in the pre-drive circuit is two or four.

When a capacitive load drive circuit such as a sustain circuit of a plasma display apparatus is configured by using a pre-drive circuit (IC) having two drive systems, a pre-drive circuit having two drive systems, a first switch element (CU) connected to the output of the output amplifier circuit of one of the drive systems, and a second switch element (CD) connected to the output of the output amplifier circuit of the other drive system are provided, and a high level voltage is supplied to the capacitive load via the first switch element and a low level voltage is supplied to the capacitive load via the second switch element. When a power recovery circuit is provided in the capacitive load drive circuit, a second pre-drive circuit having two drive systems is further provided, and a third switch element (LU) connected to the output of the output amplifier circuit of one of the drive systems of the second pre-drive circuit and a fourth switch element (LD) connected to the output of the output amplifier circuit of the other drive system are provided, and a high level voltage is supplied to the capacitive load via the third switch element and a first coil and a low level voltage is supplied to the capacitive load via the fourth switch element and a second coil.

When a capacitive load drive circuit having a power recovery circuit is configured by using a pre-drive circuit having four drive systems, the first to fourth switch elements are each connected to the outputs of the four output amplifier circuits.

In order to adjust the timing more precisely, it is desirable to provide a delay time adjusting circuit for adjusting the input and output time of a signal at the previous or subsequent stage of the pre-drive circuit. A delay time adjusting circuit can be realized, for example, by the combination of a variable resistor which selects a resistance value to be used from among a plurality of resistance values and a capacitor. When the number of selectable resistance values is the same, the smaller the range of the selectable resistance values, the more precisely the resistance value can be adjusted. According to the present invention, a more precise adjustment can be attained because the deviation range of timing can be reduced compared to conventional cases.

It is also possible to supply a voltage other than the middle voltage between the high level voltage and the low level voltage to a terminal of the third switch which is not connected to the capacitive load.

The high level voltage and the low level voltage can be set arbitrarily and, for example, the high level voltage is set to the supply voltage and the low level voltage is set to the ground voltage, or the high level voltage is set to a positive voltage and the low level voltage is set to a negative voltage the absolute value of which is the same as that of the high level voltage.

When the low level voltage is a negative voltage, an input level shift circuit which converts a level of an input signal referred to the ground voltage into one referred to the low level voltage is provided in the previous stage of the plurality of input voltage terminals of the pre-drive circuit.

Further, when the above input level shift circuit or the waveform processing circuit is provided, these circuits are desired to be provided in the pre-drive circuit. By this, a difference of timing occurred when these circuits are separately provided from the pre-drive circuit can be reduced.

Further, when the input level shift circuit and the waveform processing circuit are provided in the pre-drive circuit, the above-mentioned constitutions are desired to be applied. For example, source voltage terminals of respective circuits should be separately provided, and the pre-drive circuit including the input level shift circuit and the waveform processing circuit should be formed in a package and, particularly, on a same semiconductor chip. In other words, they are desired to be formed in an integrated circuit.

Further, it is desired that noise is removed by providing an integrating circuit in the waveform processing circuit.

Further, a simultaneously ON avoiding circuit is desired to be provided to maintain one of outputs of two drive systems, outputting a pair of drive signals for paired drive elements, to be inactive when the other is active.

According to the present invention, it is possible to reduce the difference in the input and output delay times which occur between the high level side and the low level side of the pre-drive circuit. Moreover, by applying a capacitive load drive circuit which uses the pre-drive circuit to a plasma display apparatus, it is possible to prevent the destruction of elements and an increase in power consumption caused by the difference in the input and output delay times.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings, wherein:

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing the general constitution of a plasma display apparatus;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing a conventional pre-drive circuit (power transistor drive IC);

<figref idref="DRAWINGS">FIG. 3</figref> is a diagram showing the constitution of a sustain circuit of a conventional plasma display apparatus;

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram showing the constitution of a pre-drive circuit in a first embodiment of the present invention;

<figref idref="DRAWINGS">FIGS. 5A to 5C</figref> are diagrams illustrating the input and output delay time and the distribution of the differences according to the conventional case and the present invention;

<figref idref="DRAWINGS">FIG. 6</figref> is a diagram showing a specific constitution of a high level shift circuit of the pre-drive circuit in the first embodiment;

<figref idref="DRAWINGS">FIG. 7</figref> is a diagram showing the constitution of a sustain circuit in a second embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 8</figref> is a diagram showing the constitution of a sustain circuit in a third embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 9</figref> is a diagram showing an example of an input and output delay time adjusting circuit;

<figref idref="DRAWINGS">FIG. 10</figref> is a diagram showing the constitution of a sustain circuit in a fourth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 11</figref> is a diagram showing the constitution of a sustain circuit in a fifth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 12</figref> is a diagram showing a constitution example of an input level shift circuit;

<figref idref="DRAWINGS">FIG. 13</figref> is a diagram showing the constitution of a sustain circuit in a sixth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 14</figref> is a diagram showing the constitution of a pre-drive circuit in a seventh embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 15</figref> is a diagram showing the constitution of a sustain circuit in an eighth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 16</figref> is a diagram showing the constitution of a pre-drive circuit in a ninth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 17</figref> is a diagram showing the constitution of a pre-drive circuit in a tenth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 18</figref> is a diagram showing a specific constitution of the pre-drive circuit in the tenth embodiment;

<figref idref="DRAWINGS">FIG. 19</figref> is a diagram showing the constitution of a sustain circuit in an eleventh embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 20</figref> is a diagram showing the constitution of a sustain circuit in a twelfth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 21</figref> is a diagram showing the constitution of a sustain circuit in a thirteenth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 22</figref> is a diagram showing the constitution of a sustain circuit in a fourteenth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 23</figref> is a diagram showing the constitution of a sustain circuit in a fifteenth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 24</figref> is a diagram showing the constitution of a sustain circuit in a sixteenth embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 25</figref> is a diagram showing a specific constitution of the pre-drive circuit in the seventeenth embodiment; and

<figref idref="DRAWINGS">FIG. 26</figref> is a diagram explaining an operation of a simultaneous on avoiding circuit of the pre-drive circuit in the seventeenth embodiment;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram showing the constitution of a pre-drive circuit in a first embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, a first drive system includes a first input amplifier circuit <b>41</b>, a first high level shift circuit <b>42</b> and a first output amplifier circuit <b>43</b>, and a second drive system includes a second input amplifier circuit <b>44</b>, a second high level shift circuit <b>45</b> and a second output amplifier circuit <b>46</b>. The first and second input amplifier circuits <b>41</b> and <b>44</b>, the first and second high level shift circuits <b>42</b> and <b>45</b> and the first and second output amplifier circuits <b>43</b> and <b>46</b> are, respectively, the same circuits. As a result, it is possible to make a difference (tdLH<b>1</b>−tdLH<b>2</b>) between a difference tdLH<b>1</b> in the rise times between a first input voltage IN<b>1</b> and a first output voltage OUT<b>1</b>, and a difference tdLH<b>2</b> in the rise times between a second input voltage IN<b>2</b> and a second output voltage OUT<b>2</b> less than that of the conventional power transistor drive IC (pre-drive circuit) shown in <figref idref="DRAWINGS">FIG. 2</figref>. Similarly, it is possible to make a difference (tdHL<b>1</b>−tdHL<b>2</b>) between a difference tdHL<b>1</b> in the fall times between the IN<b>1</b> and OUT<b>1</b>, and a difference tdHL<b>2</b> in the fall times between the IN<b>2</b> and OUT<b>2</b> less than that of the conventional pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 2</figref>.

By forming the pre-drive circuit within the package shown by the dotted line, particularly within the IC (integrated circuit) <b>11</b>, it is possible to reduce the variations in the elements in the circuit and make the above-mentioned differences (tdLH<b>1</b>−tdLH<b>2</b>) and (tdHL<b>1</b>−tdHL<b>2</b>) smaller.

<figref idref="DRAWINGS">FIGS. 5A to 5C</figref> are diagrams showing the effect of the pre-drive circuit of the present invention, that is, a diagram illustrating the reduction in deviation of timing. <figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 5B</figref> show distribution examples of the input and output delay time (difference in the rise times between the input voltage and the output voltage) obtained by sampling the manufactured circuits. As shown in <figref idref="DRAWINGS">FIG. 5A</figref>, conventionally, a high level voltage drive system has a high level shift circuit and a low level voltage drive system has a delay circuit, that is, the two circuits have different constitutions, therefore, the input and output delay times vary around different values as centers. Therefore, the differences in input and output delay times between the two drive systems vary around the difference between two centers and the absolute values become larger. In contrast, according to the present invention, a high level voltage drive system and a low level voltage drive system have the same constitution, therefore, the differences vary around the same value as a center as shown in <figref idref="DRAWINGS">FIG. 5B</figref>, that is, the differences in input and output delay times between the two drive systems vary around zero, and as a result, the absolute values become smaller than conventional ones.

Moreover, when two drive systems of a pre-drive circuit are formed within the same package or in the same IC, the input and output delay times of the two drive systems having the same constitution are thought to show a similar tendency and, therefore, the difference in input and output delay times between the two drive systems becomes further smaller as shown in <figref idref="DRAWINGS">FIG. 5C</figref>. According to the present invention, as described above, it is possible to considerably reduce the difference in input and output delay times between the two drive systems.

In the conventional pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 2</figref>, the low level supply voltage is used as the supply voltage of the first and second input amplifier circuits <b>21</b> and <b>24</b>. As a result, for example, even when only a high level voltage drive system, which outputs the output voltage HO for the input voltage HIN, is used, it is necessary to input a low level supply voltage. In contrast, in the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>, the supply voltage of the input amplifier circuits <b>41</b> and <b>42</b> is supplied by providing an independent input amplifier circuit supply voltage input terminal VI<b>1</b><b>32</b>. As a result, when only a high level voltage drive system is used, for example, it is not necessary to supply a supply voltage for the second output amplifier circuit <b>46</b> and the input section and the output section can be designed independently.

<figref idref="DRAWINGS">FIG. 6</figref> is a diagram showing a specific constitution of the input amplifier circuit and the high level shift circuit in the pre-drive circuit in the first embodiment. An input voltage IN is applied to the gate of a transistor Tr<b>1</b> via a resistor R<b>2</b>. The drain of the transistor Tr<b>1</b> is connected to a high level supply voltage OV and generates a voltage signal in accordance with an input voltage at the connection point of the transistor Tr<b>1</b> and the resistor R<b>3</b>. This voltage signal is applied to the gate of a transistor Tr<b>2</b> connected to a high level reference power supply RV via the high level supply voltage OV and a resistor R<b>4</b>. Because of this, a voltage which varies, with reference to the high level reference power supply RV, is generated at the connection point of the transistor Tr<b>2</b> and the resistor R<b>4</b> and this voltage is supplied to an output amplifier circuit <b>47</b>. The high level shift circuit is widely used and any type can be used and, for example, the high level shift circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 8-335863, described above, can be used.

<figref idref="DRAWINGS">FIG. 7</figref> shows the constitution of a sustain circuit of a plasma display apparatus in a second embodiment of the present invention. As shown schematically, the sustain circuit in the second embodiment has a constitution similar to that of the conventional sustain circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, but differs in that the pre-drive circuit for driving the output elements CU, CD, LU and LD is realized by using the pre-drive circuit in the first embodiment.

As shown in <figref idref="DRAWINGS">FIG. 7</figref>, by using the pre-drive circuit in <figref idref="DRAWINGS">FIG. 4</figref> as the pre-drive circuit of the sustain circuit, it is possible to more precisely set the rise time and the fall time of the gate pulse to be supplied to the output elements CU and CD. As a result, it is possible to reduce the possibility that the output elements CU and CD are destroyed by a through current when they are turned on simultaneously. Moreover, it is possible to more precisely set the rise time and the fall time of the gate pulse to be supplied to the output elements LU and LD. As a result, it is possible to precisely set the timing with which the output elements LU and LD are turned on and to properly set the values of the power recovery current flowing through the coil L<b>1</b> and the power recovery current flowing through the coil L<b>2</b>. Therefore, it is possible to prevent the increase in power consumption caused by the deviation of timing with which the output elements LU and LD are turned on.

<figref idref="DRAWINGS">FIG. 8</figref> shows the constitution of a sustain circuit of a plasma display apparatus in a third embodiment of the present invention. As shown schematically, the sustain circuit in the third embodiment differs from the sustain circuit in the second embodiment in that input and output delay time adjusting circuits <b>47</b> to <b>50</b> are provided at the inputs of each input voltage signal CUI, CDI, LUI and LDI. The input and output delay time adjusting circuits <b>47</b> to <b>50</b> absorb the variations in the input and output delay times of the pre-drive circuit and serve to reduce the differences in the rise times or fall times between CUI and VG<b>1</b>, between CDI and VG<b>2</b>, between LUI and VG<b>3</b>, and between LDI and VG<b>4</b>.

The input and output delay time adjusting circuit can be realized, for example, by a delay circuit consisting of a variable resistor VR and a capacitor C shown in <figref idref="DRAWINGS">FIG. 9</figref>. As the constitution of the input and output delay time adjusting circuit has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2001-282181, a detailed description is not given here.

Moreover, in the pre-drive circuit used in the third embodiment, threshold voltages of the first input amplifier circuit <b>41</b> and the second input amplifier circuit <b>42</b> are set to be almost equal to an intermediate voltage VI/2 of the source voltage. By this, a change of the pulse width, which is generated by providing the input and output delay time adjusting circuit, can be reduced.

In the circuit in the third embodiment, it is possible to reduce variations in the input and output delay times before they are adjusted in the input and output delay time adjusting circuit by using the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>. As a result, it is possible to reduce the adjustable range of the input and output delay time adjusting circuit. For example, when a delay circuit shown in <figref idref="DRAWINGS">FIG. 9</figref> is used as an input and output delay time adjusting circuit, it is possible to reduce the variable range of the resistor. Therefore, when the delay time is varied by trimming the resistance value of the variable resistor VR and varying the resistance value, it is possible to further reduce the minimum adjustable amount of the delay time which can be set by the unit trimming amount. As a result, a more precise setting of the delay time is made possible.

Moreover, it is possible to reduce the number of defective parts which are judged to be out of specifications because of the variations in parts by reducing the adjustable range of the input and output delay time adjusting circuit, and the productivity can be increased.

<figref idref="DRAWINGS">FIG. 10</figref> shows the constitution of a sustain circuit of a plasma display apparatus in a fourth embodiment of the present invention. As shown schematically, the sustain circuit in the fourth embodiment differs from the sustain circuit in the third embodiment in that the reset power supply source is connected to the reference voltage side of the output element CD. As shown in <figref idref="DRAWINGS">FIG. 10</figref>, the reference voltage side (side not to be connected to PDP) of the output element CD is connected to the power supply source of the voltage Vw′ via a switch SW<b>2</b>, and to the GND via a switch SW<b>3</b>. The terminal on the side of the capacitor C<b>6</b> not to be connected to C<b>5</b> is connected to the power supply side of the output element CU via a capacitor C<b>8</b>. As a matter of course, the switch SW<b>1</b> is removed. When the reset voltage Vw is applied to the PDP, the switch SW<b>2</b> is turned on after the output element CU is turned on and the switch SW <b>3</b> is turned off. Because of this, the voltage at the terminal of the capacitor C<b>8</b> changes from the GND to Vw′, and Vw′ is superimposed on the voltage on the power supply side of the output element CU to become the reset voltage Vs+Vw′ (=Vw). This reset voltage Vs+Vw′ is applied to the PDP via the output element CU. At this time, as the reset voltage Vs+Vw′ and Vw′ are applied to both sides of the output element CD, the voltage applied across the output element CD is Vs and there is an advantage that an output element CD with a relatively small withstand voltage can be used.

The constitution, in which Vw′ is superimposed on Vs and thus the reset voltage Vs+Vw′ is generated, has been disclosed in detail in Japanese Unexamined Patent Publication (Kokai) No. 2002-351388.

The sustain circuit in the fourth embodiment can be further characterized in that the voltage Vw′ can be applied to the reference voltage side of the output element CD compared to the case where the circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 7</figref> is used as a pre-drive circuit. In the conventional pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, the reference voltage side of the output element CD is connected to the GND and the low side reference voltage of the pre-drive circuit is also connected to the GND. Moreover, when the conventional pre-drive circuit is constituted using an IC, it is connected to the GND of the input section within the IC or connected to the substrate within the IC. Therefore, in the conventional pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, it was impossible to raise the low side reference voltage higher than the GND. As a result, it was impossible to superimpose the voltage Vw′ on the reference voltage side of the output element CD.

In contrast, an output reference voltage terminal RV<b>2</b> in the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref> is not connected to the GND within the IC. Moreover, it is not connected to the substrate within the IC. Therefore, it is possible to superimpose the voltage Vw′ on the output reference voltage terminal Vw′.

Generally, the reset voltage Vw is higher than the supply voltage Vs of the sustain circuit. Therefore, in the sustain circuit shown in <figref idref="DRAWINGS">FIG. 8</figref>, as the reset voltage Vw was supplied to the PDP from the power supply side of the output element CU, it was necessary to use an element with a high rated voltage corresponding to the reset voltage as the output element CD. In contrast, in the sustain circuit in the fourth embodiment shown in <figref idref="DRAWINGS">FIG. 10</figref>, as the voltage Vw′ is supplied from the reference voltage side of the output element CD, it is possible to reduce the voltage applied across the output element CD. Therefore, it is possible to use a low-cost element whose rated voltage is low and whose chip size is small.

In the circuit shown in <figref idref="DRAWINGS">FIG. 10</figref>, a capacitor C<b>7</b>, a resistor R<b>1</b> and a diode D<b>6</b> used in <figref idref="DRAWINGS">FIG. 3</figref> are eliminated. By using the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>, it is possible to shift a level of the gate pulse for driving the power recovery output element LD to a pulse referred to the reference voltage of LD (voltage Vp). Because of this, it is possible to eliminate the capacitor C<b>7</b>, the resistor R<b>1</b> and the diode D<b>6</b>. When the conventional pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 2</figref> is used, as the low side reference voltage terminal is connected to the GND within the IC, a level shift circuit made up of the capacitor C<b>7</b>, the resistor R<b>1</b> and the diode D<b>6</b> is required. The effect that such a level shift circuit can be eliminated is obtained by the use of the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>.

<figref idref="DRAWINGS">FIG. 11</figref> shows the constitution of a sustain circuit of a plasma display apparatus in a fifth embodiment of the present invention. The sustain circuit in the fifth embodiment is another example of the sustain circuit which uses the pre-drive circuit in the first embodiment. In the sustain circuit in the fifth embodiment, two voltages Vs/2 and −Vs/2 are used as a supply voltage in the sustain circuit. In the circuit shown in <figref idref="DRAWINGS">FIG. 11</figref>, Vs/2 is supplied to the PDP by turning on CU and −Vs/2 is supplied to the PDP by turning on CD. At this time, the reference voltage of CD is −Vs/2. In the circuit shown in <figref idref="DRAWINGS">FIG. 11</figref>, input level shift circuits <b>51</b> to <b>54</b> are used in order to convert a signal to be supplied to the input terminal of the pre-drive circuit into a signal referred to the voltage −Vs/2. On the other hand, in the circuit shown in <figref idref="DRAWINGS">FIG. 11</figref>, the capacitors C<b>5</b> and C<b>6</b> used in <figref idref="DRAWINGS">FIG. 10</figref> are eliminated and the GND voltage is used as a power recovery voltage Vp<b>2</b>. During the sustain operation, a switch SW<b>5</b> is turned on and the voltage Vp becomes the GND voltage. During the reset period, the switch SW<b>5</b> is turned off and the switch SW<b>1</b> and the SW<b>4</b> are turned on. As a result, when the reset voltage Vw is supplied to the PDP via CU, the voltage Vw<b>2</b> is supplied to the reference voltage terminal of LD at the same time. By supplying the voltage Vw<b>2</b> to the reference voltage terminal of LD by using the switches SW<b>4</b> and SW<b>5</b>, it is possible to reduce the voltage applied across the output element LD and to use an element (small in chip size and low cost) with a low rated voltage as LD. The constitution, in which the rated voltage of LD is reduced by using the switches SW<b>4</b> and SW<b>5</b>, has been disclosed in Japanese Patent Application No. 2002-141845.

In the circuit in the fifth embodiment shown in <figref idref="DRAWINGS">FIG. 11</figref>, the circuit shown in <figref idref="DRAWINGS">FIG. 4</figref> as a pre-drive circuit is used. In the conventional pre-drive circuit, as the low level reference voltage is connected to the reference voltage on the input side, the reference voltage of LD cannot be made higher than the input side reference voltage. In contrast, by applying the pre-drive circuit shown in <figref idref="DRAWINGS">FIG. 4</figref>, the reference voltage of LD can be made higher than the input side reference voltage −Vs/2.

It is possible to form the input level shift circuit within the IC together with the pre-drive circuit in the first embodiment.

As shown in <figref idref="DRAWINGS">FIG. 11</figref>, in the sustain circuit in which Vs/2 and −Vs/2 are used as a sustain voltage, the capacitors C<b>5</b> and C<b>6</b> for power recovery can be eliminated. In addition, by using the switches SW<b>4</b> and SW<b>5</b>, it is possible to use an element with a small rated voltage as an LD.

<figref idref="DRAWINGS">FIG. 12</figref> is a diagram showing an example of the constitution of an input level shift circuit. As shown schematically, this circuit is a circuit in which a transistor Tr<b>3</b> is connected between an input supply voltage 5V and −Vs/2 via resistors R<b>5</b> and R<b>6</b>. As the input level shift circuit is widely known, a detailed description is not given here.

<figref idref="DRAWINGS">FIG. 13</figref> shows the constitution of a sustain circuit of a plasma display apparatus in a sixth embodiment of the present invention. The sustain circuit in the sixth embodiment differs from the sustain circuit in the fifth embodiment in that the reset voltage source is connected to the reference voltage side of the output element CD. The advantage of the constitution in which the reset voltage source is connected to the reference voltage side of the output element CD is the same as that described in the fourth embodiment.

<figref idref="DRAWINGS">FIG. 14</figref> is a diagram showing the constitution of a pre-drive circuit in a seventh embodiment of the present invention. The pre-drive circuit in the seventh embodiment is characterized by having four drive systems, four inputs and four outputs. Each drive system has an identical circuit constitution, which is the same as each drive system in the pre-drive circuit in the first embodiment. Therefore, according to the principle described in <figref idref="DRAWINGS">FIGS. 5A to 5C</figref>, it is possible to reduce the difference in the input and output delay times (difference in rise times, difference in fall times) of each circuit.

<figref idref="DRAWINGS">FIG. 15</figref> shows the constitution of a sustain circuit in a plasma display apparatus in an eighth embodiment of the present invention. As shown schematically, the sustain circuit in the eighth embodiment differs from the conventional sustain circuit shown in <figref idref="DRAWINGS">FIG. 3</figref> in that the pre-drive circuit in the seventh embodiment is used as a pre-drive circuit for driving the output elements CU, CD, LU and LD. By using the pre-drive circuit in the seventh embodiment, the output elements CU, CD, LU and LD can be driven by one pre-drive circuit. Therefore, it is possible to prevent destruction due to the deviation of timing with which the output elements CU and CD are turned on and off and an abnormal power recovery operation due to the deviation of timing with which the output elements LU and LD are turned on. Particularly, when four drive systems are build into an IC, it is possible to more precisely adjust the difference in timings with which LU and CU, and LD and CD are turned on. Therefore, the power recovery operation can be performed more precisely. Although not shown in <figref idref="DRAWINGS">FIG. 15</figref>, the input and output delay time adjusting circuits <b>47</b> to <b>50</b> are provided in the previous stage of the input terminal as shown in <figref idref="DRAWINGS">FIG. 10</figref>, it is possible to more precisely set the input and output delay time by reducing the adjustable range.

<figref idref="DRAWINGS">FIG. 16</figref> is a diagram showing the constitution of a pre-drive circuit in a ninth embodiment of the present invention. The pre-drive circuit in the ninth embodiment differs from the pre-drive circuit in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref> in that Schmitt trigger circuits <b>84</b> and <b>85</b> are provided immediately after the input terminal. There are some cases where the supply voltage of the Schmitt trigger circuits <b>84</b> and <b>85</b> must be different from that of the input amplifier circuits <b>41</b> and <b>44</b>, therefore, a constant voltage circuit <b>83</b> is provided in the pre-drive circuit in the ninth embodiment and by the use of the constant voltage circuit <b>83</b>, the supply voltage of the Schmitt trigger circuits <b>84</b> and <b>85</b> is generated from the supply voltage VI<b>1</b> of the input amplifier circuits <b>41</b> and <b>44</b>. It is also possible to input the supply voltage of the Schmitt trigger circuits <b>84</b> and <b>85</b> by providing an input terminal separately, but if the constant voltage circuit <b>83</b> is built in the pre-drive circuit as shown in <figref idref="DRAWINGS">FIG. 16</figref>, the effect that the input terminal can be eliminated is brought about. Moreover, by forming a pre-drive circuit having the built-in constant voltage circuit <b>83</b> within an IC, the circuit size can be reduced. Even when a circuit other than the Schmitt trigger circuit, such as a waveform processing circuit, the supply voltage of which is different from that of the input amplifier circuits <b>41</b> and <b>44</b>, is used, the input terminal can be eliminated and the circuit size can be reduced by providing a constant voltage circuit in the pre-drive circuit.

As shown in <figref idref="DRAWINGS">FIG. 16</figref>, by providing the Schmitt trigger circuit in the pre-drive circuit, the effect is brought about that even if noises are contained in the input voltage, the noises can be removed and the output elements to be connected to the output terminal can be driven properly.

<figref idref="DRAWINGS">FIG. 17</figref> is a diagram showing the constitution of a pre-drive circuit in a tenth embodiment of the present invention. The pre-drive circuit of the tenth embodiment is used when the low level reference voltage is negative. As shown in the figure, the pre-drive circuit of the tenth embodiment includes first and second input amplifier circuits <b>131</b> and <b>132</b>, first and second low level shift circuits <b>133</b> and <b>134</b>, first and second waveform processing circuits <b>135</b> and <b>136</b>, first and second high level shift circuits <b>137</b> and <b>138</b>, and first and second output amplifier circuits <b>139</b> and <b>140</b>. These circuits constitute a pair of drive systems of same constitution. In other words, the pre-drive circuit of the tenth embodiment is characterized in that the low level shift circuit and the waveform processing circuit are provided between the input amplifier circuit and the high level shift circuit of each drive system of the pre-drive circuit of the first embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>.

The first and second low level shift circuits <b>133</b>, <b>134</b> respectively shift the outputs of the first and second input amplifier circuits <b>131</b> and <b>132</b> to signals referred to the negative reference voltage. The waveform processing circuits <b>135</b> and <b>136</b> are connected to a negative reference voltage input terminal <b>115</b>, to which a negative reference voltage COM is input, and a negative supply voltage input terminal <b>116</b>, to which a negative source supply voltage Vc generated referred to the negative reference voltage COM is input and the waveform processing circuits process respective output signals of the first and second low level shift circuits <b>133</b> and <b>134</b>.

As the pre-drive circuit of the tenth embodiment includes the low level shift circuits and the waveform processing circuits in addition to the constitution of the first embodiment, as described with reference to <figref idref="DRAWINGS">FIGS. 5A to 5C</figref>, the difference of input and output delay time between the two drive paths can be reduced.

<figref idref="DRAWINGS">FIG. 18</figref> is a diagram showing a concrete constitution of the first input amplifier circuit <b>131</b>, the first low level shift circuit <b>133</b> and the first waveform processing circuit <b>135</b> in the tenth embodiment. The second input amplifier circuit <b>132</b>, the second low level shift circuit <b>134</b> and the second waveform processing circuit <b>136</b> also have the same constitution. As shown in the figure, the first input amplifier circuit <b>131</b> is a current-mirror circuit which is constituted by transistors Tr<b>10</b>, Tr<b>11</b> and resistors R<b>10</b>–R<b>14</b>. The first input amplifier circuit <b>131</b> generates a voltage V<b>11</b>, at a collector terminal of the transistor Tr<b>11</b>, according to a difference voltage between a base voltage of the transistor Tr<b>10</b>, which is obtained from the input signal IN via the resistor R<b>10</b>, and a voltage Vref, which is obtained by dividing a voltage VI<b>1</b> by the resistors R<b>13</b> and R<b>14</b>.

The first low level shift circuit <b>133</b> is constituted by a transistor Tr<b>12</b> and resistors R<b>15</b>–R<b>17</b>. In the first low level shift circuit <b>133</b>, the voltage V<b>11</b> output from the first input amplifier circuit <b>131</b> is supplied to a base terminal of the transistor Trl<b>2</b> via the resistor R<b>15</b>, a collector current of the transistor <b>12</b> is changed according to the voltage V<b>11</b>, and a voltage (V<b>17</b>-VCOM) generated at both ends of the resistor R<b>17</b> is also changed.

The first waveform processing circuit <b>135</b> is constituted by a capacitor C<b>17</b> and a Schmitt trigger circuit S<b>1</b>. A combined resistance of the output impedance of the transistor Trl<b>2</b> and the resistor R<b>17</b> and the capacitor C<b>17</b> form an integrating circuit. This integrating circuit decreases noise components generated at both ends of the resistor R<b>17</b>. Further, the Schmitt trigger circuit S<b>1</b> makes a hysteresis between thresholds in a change of the output when a voltage between both ends of the resistor R<b>17</b> increases and decreases. As the result, the generation of an erroneous operation due to the noises generated at both ends of the resistor R<b>17</b> can be reduced.

<figref idref="DRAWINGS">FIG. 19</figref> is a diagram showing the constitution of a sustain circuit of a plasma display apparatus in an eleventh embodiment of the present invention. The sustain circuit of the eleventh embodiment is a circuit which has the sustain voltages of Vs/2 and −Vs/2 and is realized by using the drive circuit of the tenth embodiment. As shown schematically, the sustain circuit in the eleventh embodiment has a constitution similar to that of the sustain circuit of the fifth embodiment shown in <figref idref="DRAWINGS">FIG. 11</figref>, but differs in that the input and output delay time adjusting circuits <b>47</b> to <b>50</b> and the input level shift circuits <b>51</b> to <b>54</b> are eliminated, and the pre-drive circuit of the tenth embodiment is used. As the level shift circuits are provided in the IC, the difference between the input and output delay times can be further reduced in comparison with the sustain circuit of the fifth embodiment. Other constitutions except that the input and output delay time adjusting circuit is not provided are similar to those of the sustain circuit of the fifth embodiment and, therefore, more detailed descriptions are omitted.

<figref idref="DRAWINGS">FIG. 20</figref> is a diagram showing the constitution of a sustain circuit of a plasma display apparatus in a twelfth embodiment of the present invention. The sustain circuit of the twelfth embodiment has a constitution in which input and output delay time adjusting circuits <b>47</b> to <b>50</b> are provided in the sustain circuit of the eleventh embodiment. In this constitution, threshold voltages of the input amplifier circuits <b>131</b> and <b>132</b> are set to be almost a half of the source voltage VI of the input amplifier circuit. For example, this condition is realized by setting the resistances of the resistors R<b>13</b> and R<b>14</b> in <figref idref="DRAWINGS">FIG. 18</figref> equal. By this condition, a change of pulse width generated at the input and output delay time adjusting circuits <b>47</b> to <b>50</b> can be reduced. The detailed description of this principle is made in Japanese Patent Application No. 2003-106839.

<figref idref="DRAWINGS">FIG. 21</figref> is a diagram showing the constitution of a sustain circuit of a plasma display apparatus in a thirteenth embodiment of the present invention. The sustain circuit of the thirteenth embodiment has a constitution similar to that of the sustain circuit of the twelfth embodiment, but differs in that the switch SW<b>1</b> is eliminated, and a reset voltage Vw is overlaid at a source terminal of the second switch element CD via the switch SW<b>2</b>. The switch SW <b>6</b> is turned off when the switch SW<b>2</b> is turned on. The operation of this constitution is similar to that of the sixth embodiment shown in <figref idref="DRAWINGS">FIG. 13</figref> and, therefore, more detailed descriptions are omitted.

<figref idref="DRAWINGS">FIG. 22</figref> is a diagram showing the constitution of a sustain circuit of a plasma display apparatus in a fourteenth embodiment of the present invention. The sustain circuit of the fourteenth embodiment has a constitution similar to that of the sustain circuit of the thirteenth embodiment, but differs in that the switches SW<b>4</b> and SW<b>5</b> are added. In this constitution, similar to the fifth and sixth embodiments, the voltage VW<b>2</b> is applied to the supply voltage terminal of the switch element LD in the reset period. The switch SW <b>5</b> is turned off during a period in which the switch SW<b>4</b> is turned on. As the result, the voltage applied between the drain and source of the switch element LD in the reset period can be decreased, therefore, it is possible to use an element whose rated voltage is low as the switch element LD.

<figref idref="DRAWINGS">FIG. 23</figref> is a diagram showing the constitution of a pre-drive circuit in a fifteenth embodiment of the present invention. The pre-drive circuit of the fifteenth embodiment differs from the pre-drive circuit of the tenth embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref> in that the pre-drive circuit of the fifteenth embodiment includes four inputs and four outputs although the pre-drive circuit of the tenth embodiment includes two inputs and two outputs. By this constitution, the differences between input and output delay times of the four drive systems can be reduced.

<figref idref="DRAWINGS">FIG. 24</figref> is a diagram showing the constitution of a sustain circuit of a plasma display apparatus in a sixteenth embodiment of the present invention. The sustain circuit of the sixteenth embodiment is a circuit which has the sustain voltages of Vs/2 and −Vs/2 and is realized by using the drive circuit of the fifteenth embodiment. Since pulses supplied to gates of the elements CU, CD, LU and LD are generated by circuits constituted in the same IC, the differences between input and output delay times of the four drive systems can be reduced. Other constitutions are similar to those of the eleventh embodiment, therefore, more detailed descriptions are omitted. Further, the pre-drive circuit of the fifteenth embodiment can be similarly applied to the embodiments of the twelfth to fourteenth embodiments.

<figref idref="DRAWINGS">FIG. 25</figref> is a diagram showing the constitution of a pre-drive circuit in a seventeenth embodiment of the present invention. The pre-drive circuit of the seventeenth embodiment differs from the pre-drive circuit of the tenth embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref> in that a simultaneous ON avoiding circuit <b>190</b> is provided. The simultaneous ON avoiding circuit <b>190</b> is realized by a logic circuit. The simultaneous ON avoiding circuit <b>190</b> receives outputs of the first and second waveform processing circuits <b>135</b> and <b>136</b> and processes them so that the output voltages OUT<b>1</b> and OUT<b>2</b> do not simultaneously become active. The outputs of the simultaneous ON avoiding circuit <b>190</b> are input to the first and second high level shift circuits <b>137</b> and <b>138</b>.

<figref idref="DRAWINGS">FIG. 26</figref> is a diagram for explaining an operation of the simultaneous ON avoiding circuit <b>190</b>. As shown in the left side of the figure, when the input voltage signal IN<b>1</b> and IN<b>2</b> do not become active simultaneously, namely, when one of them changes from an off-state to an on-state after the other changes from the on-state to the off-state, the simultaneous ON avoiding circuit <b>190</b> outputs the signals with no change. As shown in the right side of the figure, when the input voltage signal IN<b>1</b> and IN<b>2</b> become active simultaneously, namely, when one of them changes from the off-state to the on-state before the other changes from the on-state to the off-state, the simultaneous ON avoiding circuit <b>190</b> changes the signals so that the one changes from an off-state to an on-state after the other changes from the on-state to the off-state.

By providing the simultaneous ON avoiding circuit <b>190</b>, a state in which the switch elements CU and CD or LU and LD are simultaneously turned on can be certainly avoided when the input voltage signals IN<b>1</b> and IN<b>2</b>, which provide a condition that the elements CU and CD or LU and LD are simultaneously turned on, are input or when such condition occurs in the pre-drive circuit. According to this constitution, the increase in power consumption or destruction of the elements can be avoided and, therefore, the reliability of the circuit can be improved.