Method and circuit for driving power transistors in a half bridge configuration from control signals referenced to any potential between the line voltage and the line voltage return and integrated circuit incorporating the circuit

Method and circuit for driving half-bridge power transistor with line voltage and potential difference between line voltage loops as control signals, and integrated circuit combining the circuit

The present invention relates to a method and a circuit for driving a power transistor with a half-bridge architecture by using a line voltage and a potential difference between the line voltage loops as a control signal.

At present, inventions such as these can be applied to power MOSFFTs with half-bridge architecture, and can also be applied to other types of power transistors. The invention also includes the driver chip of the integrated circuit of the circuit.

There must be an interface circuit between the power transistor of the half-bridge architecture and its control signal, especially the power transistor can be coupled to the line voltage and the potential between the line voltage loops as the control signal. In addition, there must be a circuit with other driving functions integrated in a single driving chip.

Previously, the most commonly used situation is the control signal with the line voltage loop or the potential between the line voltage VL and the loop voltage-VL as the reference point. Fig. 1 is an example showing the control signal with the line voltage VL and the line voltage-VL as the reference point. Here, the midpoint of the line voltage and the return line voltage is the ground or Vss. In the circuit of Figure 1, so the control signal must take the ground or Vss as the reference point. The best practice is to use any voltage between VL and -VL as the reference point.

At present, the object of the present invention is to provide a method and circuit for driving a power transistor of a half-bridge architecture by using a line voltage and an arbitrary potential difference between the line voltage loops as a control signal.

A further object of the present invention is to provide an integrated circuit driver chip incorporating the driver circuit.

The above or other purposes can be accomplished by a method of driving a half-bridge power transistor with the line voltage and any potential between the line voltage loops as the reference point as the control signal, which consists of: providing a line voltage and line voltage The arbitrary voltage between the loops is the control signal of the reference point, which provides the aforementioned two voltage levels floating on the common voltage terminal, and also serves as offsetting the output level of the input circuit to the voltage level of the first shift circuit, so that the input circuit The output level is based on the common voltage level as the reference point. Provide the aforementioned common voltage level as a reference point output to a low-side drive circuit of a half-bridge architecture power circuit that operates on a low-side power circuit. The output of the aforementioned common voltage level as a reference point is also provided to the second shift circuit, so that the output level of the first shift circuit generates a signal relative to the second high voltage level instead of the common voltage level. A signal with the aforementioned second high voltage level as a reference point is also provided to the high-side drive circuit to drive the power transistor of the aforementioned half-bridge architecture high-side power transistor.

The above and other objectives of this invention can be achieved by driving a half-bridge power transistor circuit with a control signal that uses the line voltage and any potential between the line voltage loops as the reference voltage, and it is composed of an acceptable line voltage and line voltage. The arbitrary potential between the loops is a circuit for the control signal of the reference voltage, and the input circuit and the two voltage levels are floating relative to the common point. The first shift circuit receives the output of an input circuit, and makes the output level of the input circuit take the common voltage level as a reference point. An output of the aforementioned common voltage level as a reference point is output to a low-side drive circuit of a half-bridge power transistor operating on a low-side power transistor. A second shift circuit makes the output level of the first bit position circuit generate a signal relative to the second high voltage level instead of the common voltage level. A driving circuit receives a signal with reference to the aforementioned second high voltage level to drive the power transistor of the aforementioned half-bridge architecture high-side power transistor.

The above and other inventions can also be achieved by using a control signal that uses the line voltage and any potential between the line voltage loops as the reference voltage to drive a half-bridge power transistor circuit, which is composed of an acceptable line voltage and line voltage. Any potential between the voltage loops is a circuit for the control signal of the reference voltage, and the input circuit and the two voltage levels are floating relative to the common point. The first shift circuit receives the output of an input circuit, and makes the output level of the input circuit take the common voltage level as a reference point. An output of the aforementioned common voltage level as a reference point is output to a low-side drive circuit of a half-bridge architecture power circuit that operates on a low-side power circuit. A second shift circuit makes the output level of the first shift circuit generate a signal relative to the second high voltage level instead of the common voltage level. A driving circuit receives a signal with reference to the second high voltage level to drive the power transistor of the high-side power transistor of the half-bridge architecture.

The above and other inventions can be achieved by using a single integrated chip to drive a half-bridge power circuit with a control signal that uses the line voltage and any potential between the line voltage loops as the reference voltage. It consists of: providing an input circuit that can accept the control signal of the line voltage and any potential between the line voltage loops as the reference voltage, and the input circuit and the two voltage levels are floating relative to the common point. A first shift circuit is provided to receive the output of an input circuit, so that the output level of the input circuit is based on the common voltage level as a reference point. An output of the aforementioned common voltage level as a reference point is provided to a low-side driving circuit of a half-bridge power transistor operating on a low-side power transistor. A second shift circuit is provided, so that the output level of the first shift circuit generates a signal relative to the second high voltage level instead of the common voltage level. A driving circuit is provided to receive a signal with reference to the aforementioned second high voltage level to drive the power transistor of the aforementioned half-bridge architecture high-side power transistor.

This invention can be achieved by a single integrated chip using a control signal with a line voltage and any potential between the line voltage loops as the reference voltage to drive a half-bridge power transistor. Its composition is as follows:

An input circuit that can accept a control signal whose line voltage and any potential between the line voltage loops is a reference voltage, and the two voltage levels of the input circuit are floating relative to the common point.

The first shift circuit can receive the output of an input circuit, and make the output level of the input circuit take the common voltage level as a reference point.

An output of the aforementioned common voltage level as a reference point is output to a low-side drive circuit of a half-bridge power transistor operating on a low-side power transistor.

A second shift circuit makes the output level of the first shift circuit generate a signal relative to the second high voltage level instead of the common voltage level.

A driving circuit receives a signal with reference to the second high voltage level to drive the power transistor of the high-side power transistor of the half-bridge architecture.

With reference to the diagram, FIG. 1 shows a circuit diagram of an interface that is generally connected between a control signal and a half-bridge power transistor. On the body, the power transistor operates in a complementary manner in terms of known techniques. The load is connected to the output terminal. The half-bridge circuit includes a high-side transistor 10 and a low-side transistor 20. As shown in the circuit diagram, when the high-side transistor is driven on, the low-side transistor will turn off; conversely, when the low-side transistor is driven off, the high-side transistor will turn on. The half-bridge circuit can also operate in a manner that the load is connected to two transistors in series, and the two transistors can be driven at the same time. Control signals such as HIN and LIN are applied to the input terminal 30 of the control logic interface circuit 40. The production of the control logic interface circuit is a known art. For example, a control logic interface circuit may be of the type IR2110 provided by International Rectifier Corp (IRC) for this application. There may also be one or more control inputs 30, which are determined based on how the circuit is controlled in the generally known art. As shown in Figure 1, there are two control inputs.

The control logic interface circuit 40 provides a known high-side drive gate 42 and a low-side drive gate 44. The voltage sources VB, Vcc, VDD are coupled to the control logic. In addition, the power supply VL, and -VL are coupled to the main terminals of the respective electric body 10, 20. These power electronics have a common end coupled to the connection between Vs and the load. As shown in the main body, the ground terminal is connected to the voltage Vss. As shown in Figure 1 of the previous example, the control signal or signal 30 has a reference level, which is usually ground. However, many inverted control signals do not need to use the ground as a reference level. There must be an interface circuit between the control signal and the half-bridge power transistor, which can use any potential between the line voltage and its return line, or between VL and -VL as a reference point.

Figure 3 is a detailed part of the conventional components of Figure 1, especially an IR2110 drive circuit whose control input signal is referenced to Vss (ground).

FIG. 3 is a functional block diagram including the integrated circuit 40 of FIG. The logic input terminals 10, 11, and 12 are connected to the RS latches 50D and 50E via the Schemi triggers 50A, 50B, and 50C, and are also connected to the logic circuits 50F and 50G shown in the figure. The output terminals of the logic circuits 50F and 50G are coupled to the shift circuits 70 and 68, respectively. It can be seen that the output terminals of the shift circuits 70 and 68 control the high-side control output terminal and the low-side control output terminal at pins 7 (HOUT) and 1 (LOUT), respectively.

The shift circuit 68 of the low-voltage channel is output via a delay circuit 72A and an output terminal 72B of the gate circuit. The gate output terminal 72B is connected to the gate electrodes of the output drive MOSFET transistors 74A and 74B. It will be mentioned later that when logic is input to pins 11 and 12 of these transistors, pin 1 will generate a gate voltage.

FIG. 3 also includes a low voltage detection circuit 73, so that when a low voltage is detected at pin 3, the gate will not generate output to prevent the power MOSFET or IGBT at pin 1 from turning on.

The high-voltage channel shift circuit 70 has an input terminal connected to a pulse generator 76A. The low voltage detection circuit 73 is also connected to the pulse generator 76A, and when a low voltage is detected at pin 3, the high voltage output channel will be turned off.

The pulse generator 76A has two output terminals. One set (S) output is connected to the gate of MOSFET 76B, and the other reset output (R) is connected to the gate of MOSFET 76C. The setting pulse is applied to the gate of MOSFET 76B, and the reset output is applied to the gate of MOSFET 76C.

The sources of MOSFETs 76B and 76C are connected to a common point, and their drains are connected to resistors 76D and 76F, respectively.

In normal operation, the pulses applied by the pulse generator 76A to the MOSFETs 76B and 76D will generate output voltage pulses Vset and Vrst on the MOSFETs 76B and 76D and their respective resistors 76D and 76E. The voltage pulses Vset and Vrst are applied to the pulse filter 76F. The output channel of the filter 76F is connected to the R and S input terminals of the RS 76G. The second low voltage detection circuit 73H is used as the input terminal of the latch 76G to ensure that when a low voltage is detected at pin 6, no signal is generated at pin 7.

The output terminal of the RS latch 76G is used to control the switching of MOSFETs 78A and 78B. Therefore, when a high signal is applied to the input R terminal of the RS latch, the output terminal of pin 7 is closed, and when a high signal is applied to the input S terminal of the RS latch, the output terminal of pin 7 is opened.

In the circuit of FIG. 3, the input terminals HIN and LIN of the control signal are based on the ground (Vss) as the reference point. There must be a drive circuit as shown in Figure 3 so that the control signal can take any point between +VL and -VL as the reference point. Figure 2 replaces the control logic circuit 40 of Figure 1 and provides the aforementioned possibilities. The interface circuit includes an input part that can receive a control signal input terminal and is coupled to a voltage source VDDAVSS. As shown in Figure 1, the line voltage Vss is not coupled to ground. VDD and VSS are selected to allow the control signal to take any point between +VL and -VL as the reference point. The input signal enters the input logic circuit 52, which is a traditional design, and its output terminal is coupled to the pulse generator 54, which is also a traditional design. As currently known, the pulse generator 54 generates "on" and "off" outputs on two separate output lines. An "on" pulse is applied to the leading edge of the input control signal, and an "off" pulse is applied to the trailing edge of the input control signal. The block area 50 in FIG. 3 is an example of the logic circuit 52 and the pulse generator 54.

The output terminal of the pulse generator is applied to the first shift circuit 56 composed of two P-channel FETs 55 and 57 coupled to the resistor 58 or 60, respectively. An essential or parasitic diode 62 is coupled across the resistor-transistor series circuit of the transistor 55, the resistor 58, and the transistor 57, and the resistor 60. Transistor 55 and transistor 57 shift the control signal to reference the common point or -VL. Therefore, these signals provide the driving of the low-side power device 20. This shift circuit will control the signal from the reference level VDD and VSS to the reference level Vcc and the common terminal, so these signals provide a comparison of the previous shift circuits 70 and 68 in FIG. 3.

The outputs of the electric nipples 55 and 57 are coupled to the buffers 64 and 66, respectively. The buffers 64 and 66 are respectively coupled to the N-channel FETs 68 and 70 and the output logic circuit of the conventional design 72 of FIG. 3. The output of the logic circuit 72 is added to the driving circuit 74, which is also a traditional design (see FIG. 3), and provides a low-side output driving signal to the low-side power transistor.

Transistors 68 and 70 provide a second shift circuit, whereby the output terminals of buffers 64 and 66 are shifted to the high voltage reference of drive circuits 76 and 78 in the high-side power transistor 10 with reference to the VB and VS points point,. The transistors 68 and 70 move the reference level of the gate control signal from the common reference level to the VB reference level to drive the high-side power device 10. The output of the logic circuit 76 is added to a conventionally designed element 78 (see FIG. 3) to provide a high-side output signal to the power transistor 10.

As shown in the figure, each transistor 68 and 70 are respectively coupled to a traction resistor 69 or 71 to complete the level shift.

In addition, there is another coupling across to the essential diode 63 of the second shift circuit. The two N-channel FETs, the two P-channel FETs and the two diodes must be able to withstand a voltage of at least twice VL. These two diodes show the fact that both circuit blocks 50 and 75 can float on -VL with more than twice VL alone.

Mark the right part of the circuit of line XX, usually IR 2110 type components. Therefore, all the circuits in FIG. 2, including the first shift circuit 56, are preferably integrated on a single integrated chip, that is, a silicon chip. For example, the circuit in Figure 2 shows a modification of the IR2110 type component, which can be integrated on a silicon chip

Figure 4 shows part of the circuit of Figure 2 used in an integrated circuit. When the circuit in Figure 2 is made on the same silicon chip, the high-voltage and low-voltage circuits are insulated from each other in the direction of the measurement surface. FIG. 4 shows a cross-sectional view of this part of the chip, especially the coupling circuit between VB and Vs in the circuit 75 of FIG. 2. Therefore, in FIG. 4, a wafer 120 includes a P(-) substrate 121 on which an N(-) silicon epitaxial layer 122 is grown. The N(-) region 122 is divided into high-voltage and low-voltage regions by the P+ junctions 130, 131, and 132. Therefore, the junctions 130 and 131 define a high-voltage device region 140 in the epitaxial layer 122, which is separated from the low-voltage device region 141. . The area 140 and the area 141 can have any shape. Furthermore, any insulation technique can be used between the area 140 and the area 141.

Generally speaking, the driving circuit 78 of FIG. 2 is composed of P-channel and N-channel MOSFETs. There will be a detailed description in the serial number (Serial No.08/274,012, July 12, 1994) IR-1131). In addition, as described, the low-voltage control circuit of the high-voltage circuit can be composed of P-channel and N-channel MOSFETs, both of which are known techniques.

FIG. 4 shows that the high voltage area 140 forms a high voltage circuit of MOSFETs. The P+ contact regions 162 and 163 diffused to the layer 122 represent the source and drain of the P-channel MOSFETs of the driver 78 of FIG. 2. The P region 164 diffuses into the layer 122 to form a good P-type region. The N+ contact regions 160 and 161 diffused to the P-type region 164 represent the source and drain of the N-channel MOSFETs of the driver 78 of FIG. 2.

FIG. 4 includes the structure of the MOSFETs of the low-voltage control circuit system in the region 141. The N+ contact region 125 diffuses to the N-type region 141 and receives an electrode of the low-voltage power supply Ycc. The diffusion of N+ and P+ in the low-voltage control region 124 is the same as the diffusion of the high-voltage region 140 from 160 to 164. There will also be diffusion. However, all the low-voltage control regions 124 will have electrodes between Ycc (15V) and 0V, and they represent the source and drain of the low-voltage control circuit MOSFETs.

The N+ contact regions 126 and 127 diffuse to the layer 122 and receive the metal electrode at a potential between VB (615V) and Vs (600V). The P+ bus areas 130, 131, and 132 receive electrodes located at 0 and ground potential (COM). The P(-) updated surface areas 150 and 151 may surround the high voltage area 40 to provide insulation for the low voltage area 141.

Generally speaking, all silicon-surfaced components will be covered with a layer of dielectric. For example, the low temperature silicon dioxide layer 180 has a thickness of 1.5 microns. The contact with all surface electrodes penetrates this dielectric 180 and is regarded as an appropriate external puncture.

The component of FIG. 4 is also equipped with a general plastic shell 181, which is in contact with the upper surface of the complete chip of FIG. 4. Suitable plastic shells are preferably insulating materials, such as those sold under the trademarks Nitto MP~150SG, Nitta MP-180 and HysolMG15-F.

Although Figure 4 shows a cross-sectional view of the circuit coupled to VB and VS, a similar, separate architecture is used for the circuit coupling between VDD and YSS. Basically, the same architecture can be used in the VDD-VSS circuit marked VB in Figure 4. Figure 4 shows the coupling of Vs to the VSS circuit.

Here, a control signal with the line voltage VL and any potential between the line voltage product line-VL as the reference point is provided to drive the circuit of the half-bridge architecture power transistor. It is best to combine the integrated circuit of the circuit on a single chip.

Although the current invention is related to the description of a particular ontology. Many other changes, modifications and uses are obvious in the art. Therefore, the current invention is not limited to the specific disclosure herein, but is within the scope of the attached patent application.

Figure 1 is an example of an interface circuit connected between a control signal and two half-bridge power transistors.

Figure 2 is the circuit of this invention, which provides an interface circuit between the control signal and the power transistor, and allows the line voltage and any voltage between the line voltage loops as the reference point to be driven by the control signal.

FIG. 3 is a known driving circuit modified according to the aforementioned invention, and its control signal is based on the ground terminal.

Figure 4 is an integrated circuit of part of the circuit of Figure 2.