Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length

RELATED APPLICATION

0001This application is related to and claims priority from Korean Patent Application No. 2002-1774 filed Jan. 11, 2002, the disclosure of which is hereby incorporated herein by reference.

FIELD OF THE INVENTION

0002The present invention relates to integrated circuit devices and, more particularly, to synchronous dynamic random access memories (SDRAMs).

BACKGROUND OF THE INVENTION

0003To improve the operational speed of integrated circuit devices, integrated circuit memory devices have rapidly developed from fast operation mode dynamic random access memories (DRAMs), such as fast page mode DRAMs or extended data output (EDD) DRAMs, to SDRAMs and from SDRAMs to dual data rate (DDR) DRAMs. A number of DRAM manufacturing companies are currently researching the next generation of memory devices after the DDR SDRAMs. For example, the next generation may use DDR<b>2</b> SDRAMs having a 4-bit prefetch scheme instead of the conventional DDR SDRAMs having a 2-bit prefetch scheme.

0004The Joint Electronic Device Engineering Council (JEDEC) recommended that DDR<b>2</b> SDRAMs use a 4-bit prefetch scheme as well as a fixed burst length of 4-bits. In integrated circuit memory devices having a 4-bit prefetch scheme and a fixed burst length of 4-bits, 2-bits of a 4-bit input column address signal that activates a plurality of column select lines are not utilized. In other words, if 2-bits of the 4-bit column address signal are not utilized, only four column select lines may be automatically activated by the column address signal. Furthermore, in integrated circuit memory devices having a 4-bit prefetch scheme and a fixed burst length of 4-bits, the order of data is determined based on a first input column address and the type of address increase scheme used, for example, a sequential address increase scheme or an interleave address increase scheme.

0005The four column select lines that correspond to the four possible modes using 2-bits of the 4-bit column address signal, i.e., 00, 01, 10, and 11, respectively, are activated in a mode where a burst length is 4-bits, regardless of the starting column address. For example, if the 2-bits of the start column address are 00, the 2-bits of a column address corresponding to a column select line which have to be generated with the start column address 00 are 01, 10, or 11. Accordingly, if the start column address is 01, the 2-bits of a column address corresponding to a column select line which have to be generated with the start column address 01 are 10, 11, or 00.

0006As described above, if a burst length of 4-bits is used with a 4-bit prefetch scheme, the number of bits to be prefetched is four and the number of sequentially input/output data, i.e., the burst length, is 4-bits. Accordingly, since these lengths are the same, a mode where the burst length is 4-bits may be realized in an integrated circuit memory device using the 4-bit prefetch scheme. However, if the burst length is 8-bits not all the column select lines may be selected using 2-bits of the column address as discussed above. To provide the possibility of eight column select lines, 3-bits are considered if a sequential address increase scheme is used. However, 3-bits do not have to be considered if an interleave address increase scheme is used.

0007Conventional integrated circuit memory devices having a 2-bit prefetch scheme and a burst length of 4-bits typically include an address counter. The address counter generates addresses corresponding to column select lines that will be generated for the next cycle using 2-bits of the 4-bit column address signal. Therefore, it may be difficult for the integrated circuit memory device using a 4-bit prefetch scheme and a burst length of 8-bits to support a sequential address increase scheme, because as discussed above, 3-bits are typically considered. Accordingly, JEDEC recommends that the burst length of 4-bits be fixed in a DDR<b>2</b> SDRAM.

0008An integrated circuit memory device using the 4-bit prefetch scheme is likely to have an address counter which generates addresses corresponding to column select lines that will be generated for next cycle. However, this 4-bit prefetch scheme may be complicated. Furthermore, if the clock cycles are reduced, the internal margin of the integrated circuit device may become short, limiting the operational frequency of the integrated circuit device.

0009The demand for a burst length of 8-bits has increased because the speed of the integrated circuit memory device can be increased accordingly. If the number of bits to be prefetched is increased to increase the speed of the integrated circuit memory device, the number of internal data input/output (I/O) lines is also typically increased. Some conventional SDRAMs may operate in a mode where the burst length is 8-bits and a nibble sequential address increase scheme is used to meet the demand for the burst length of 8-bits. However, it may be complicated to realize general SDRAMs for supporting the burst length of 8-bits. This may also present difficulties in supporting the sequential address increase scheme, which is generally used in SDRAMs using a prefetch scheme.

0010SDRAMs using the prefetch scheme typically use the sequential address increase scheme or the interleave address increase scheme. However, SDRAMs using the nibble sequential address increase scheme typically do not support a normal sequential address increase scheme.

0011Accordingly, integrated circuit devices that support a burst length of 8-bits or twice the number of bits to be prefetched, for example, 4-bits, that can support both sequential and interleave address increase schemes may be desirable.

SUMMARY OF THE INVENTION

0012Embodiments of the present invention provide an integrated circuit device including a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation.

0013In some embodiments of the present invention, the DDR integrated circuit memory device is configured to support a sequential address increase scheme and an interleave address increase scheme. In certain embodiments the prefetch N is 4 and the burst length 2N is 8. In further embodiments, the prefetch N is 2 and the burst length 2N is 4.

0014In further embodiments of the present invention, the DDR integrated circuit memory device further includes a pre-decoder and a memory cell array. The pre-decoder receives a 3-bit column address signal and generates a plurality of pre-decoding signals. The memory cell array includes at least one memory cell array block for storing the 2N burst length of data. The pre-decoding signals activate a column select line that designates the position of the 2N burst length of data in memory cell array block of the memory cell array.

0015In still further embodiments of the present invention, the at least one memory cell array block includes first to fourth memory cell blocks. The DDR integrated circuit memory device may further include a data position controller that is configured to determine the position of the 2N burst length of data in the first through fourth memory cell array blocks based on a first bit and a second bit of the 3-bit column address signal.

0016In some embodiments of the present invention, the pre-decoder further includes a logic circuit that activates at least one logic signal in response to a mode control signal. The mode control signal may include a burst length control signal that indicates the 2N burst length, wherein a logic high indicates that the 2N burst length is a 4-bit burst length and a logic low indicates the 2N burst length is an 8-bit burst length, a sequential mode signal that indicates use or the sequential address increase scheme when the sequential mode signal is a logic high, and an interleave mode signal that indicates use of the interleave address increase scheme when the interleave mode signal is a logic high.

0017In further embodiments of the present invention, the at least one logic signal is responsive to the 3-bit column address signal. In certain embodiments of the present invention the least one logic signal includes first through eighth logic signals, the burst length control signal is a logic low and the sequential mode signal is a logic high. Each of the first through eighth logic signals are responsive to a first bit, a second bit and a third bit of the 3-bit column address signal.

0018In still further embodiments, the at least one logic signal may include first through eighth logic signals, the burst length control signal is a logic high and the interleave mode signal is a logic high. The first logic signal and the fifth logic signal are responsive to a third bit of the 3-bit column address signal.

0019In some embodiments of the present invention, the at least one logic signal includes first through eighth logic signals. The logic circuit may be further configured to activate one of the first through eighth logic signals and to combine the activated logic signal with the next three sequential logic signals to form a first group of four logic signals. The logic circuit may be further configured to form a second group of four logic signals including the remaining four of the first through eighth logic signals not combined with the activated signal to form the first group. The first group of logic signals may be activated during a first cycle of the clock in response to a first control signal and wherein the second group of logic signals may be activated during a second cycle of the clock in response to a second control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

0020<figref idref="DRAWINGS">FIG. 1</figref> is a timing diagram illustrating the operation of synchronous dynamic random access memories (SDRAMs) according to embodiments of the present invention;

0021<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating integrated circuit memory devices according to embodiments of the present invention;

0022<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram illustrating a portion of a column address pre-decoder shown in <figref idref="DRAWINGS">FIG. 2</figref> according to embodiments of the present invention;

0023<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating operations of a pre-decoder shown in <figref idref="DRAWINGS">FIG. 3</figref> according to embodiments of the present invention;

0024<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating operations of a data position controller shown in <figref idref="DRAWINGS">FIG. 2</figref> according to embodiments of the present invention; and

0025<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating the location of data using to various address schemes according to embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT INVENTION

0026The present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other layer or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout.

0027Embodiments of the present invention will be described below with respect to <figref idref="DRAWINGS">FIGS. 1 through 6</figref>. Embodiments of the present invention provide an integrated circuit device including a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. In some embodiments of the present invention, the integrated circuit device can support both the existing sequential and interleave address increase schemes. Integrated circuit devices according to embodiments of the present invention provide the above by including a 012 pre-decoder <b>500</b> that outputs first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) using 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of a column address CA to control column select lines for selecting columns where data will be input to and output from. Four of the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) output from the 012 pre-decoder <b>500</b> are activated during the first cycle based on the start column address and the other four pre-decoding signals are activated during the second cycle after the first through eighth pre-decoding signals (DCA<b>012</b><i>, i=0–7) are inverted. Accordingly, an integrated circuit memory device according to embodiments of the present invention may not include a complicated circuit such as a counter for generating a column address in the integrated circuit memory device. Furthermore, since it is possible to control the order of how the data is input and/or output using 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA, the order can also be used when the burst length is 4-bits.

0028Referring now to <figref idref="DRAWINGS">FIG. 1</figref>, operations of synchronous dynamic random access memories (SDRAMs) according to embodiments of the present invention will be discussed. Embodiments of the SDRAM illustrated in <figref idref="DRAWINGS">FIG. 1</figref> utilizes an N to 2N prefetch-to-burst length ratio, for example, a 4-bit prefetch scheme and a burst length is 8-bits. Accordingly, 8-bits of data D<b>0</b> through D<b>7</b> are sequentially input and/or output (I/O) via a data pin DQ of an integrated circuit memory device. It will be understood that integrated circuit devices according to embodiments of the present invention may include one or more data pins DQ without departing from the teachings of the present invention.

0029An address for a memory cell is selected for the data input into the integrated circuit substrate via data I/O pin DQ. A single memory cell address is selected for all 8-bits of data D<b>0</b> through D<b>7</b>. Once the address is selected, a command is issued to input data. As illustrated in the timing diagram of <figref idref="DRAWINGS">FIG. 1</figref>, the 8-bits of data D<b>0</b> through D<b>7</b> are input on the rising and falling edges of a data strobe signal DQS. The data strobe signal DQS initiates the input of data and adjusts the synchronization of data with respect to the clock signal CLK. The data strobe signal DQS is synchronized with the clock signal CLK, i.e. has the same cycle and waveform as the clock CLK, when data is being input (read) into the integrated circuit memory device via data pin DQ, but has a predetermined level when data is not being input into the integrated circuit device.

0030For example, data may be sequentially input into the integrated circuit device. In other words, D<b>0</b> may be input first and D<b>7</b> may be input last (or eighth). Using a 4-bit prefetch scheme, the first four bits of data D<b>0</b>, D<b>1</b>, D<b>2</b> and D<b>3</b> are serially input into the integrated circuit device and converted into parallel data. The serial to parallel conversion is performed while the data is being synchronized with a rising edge of a next clock CLK after the fourth data bit D<b>3</b> is input into the integrated circuit memory device. The parallel converted data is input into four memory cell array blocks <b>100</b>_i (i=1–4) simultaneously. The whole memory cell array of the SDRAM using the 4-bit prefetch scheme may be divided into four memory cell array blocks <b>100</b>_i (i=1–4).

0031The last four data bits D<b>4</b>, D<b>5</b>, D<b>6</b> and D<b>7</b> are input sequentially into the integrated circuit device and converted into parallel data while being synchronized with a rising edge of the next clock after the eighth data bit D<b>7</b> is input. The parallel data may also be input into the four memory cell array blocks <b>100</b>_i (i=1–4) simultaneously.

0032The data may be output (written) from the integrated circuit device utilizing a method similar to the method described above with respect to inputting the data bits D<b>0</b> through D<b>7</b>. In other words, four data bits are sensed at a time in parallel from the four memory cell array blocks <b>100</b>_i (i=1–4) simultaneously and converted into serial data. The serial data is output via the data pin DQ to, for example, a device outside the integrated circuit memory device.

0033Now referring to <figref idref="DRAWINGS">FIG. 2</figref>, a block diagram illustrating an integrated circuit memory device according to embodiments of the present invention will be discussed. As illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, the integrated circuit memory device includes a memory cell array <b>100</b>, a buffer <b>200</b>, a decoder <b>300</b>, a serial to parallel converter <b>410</b>, a parallel to serial converter <b>420</b>, a data position controller <b>430</b>, and a sense amplifier <b>440</b>.

0034The memory cell array <b>100</b> may be divided into a plurality of memory cell array blocks. As illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, in certain embodiments, the memory cell array <b>100</b> is divided into four memory cell array blocks <b>100</b>_i (i=1, 2, 3, 4). The serial to parallel converter <b>410</b> changes the serial data sequentially input into the integrated circuit device into parallel data. In other words, for every N data input serially there is a corresponding N parallel data. The parallel to serial converter <b>420</b> converts the N parallel data output from the memory cell array <b>100</b> back into N serial data.

0035In certain embodiments of the present invention, an integrated circuit memory device having a burst length of 8-bits sequentially inputs and/or outputs 8-bits of serial data via one data pin DQi. The serial to parallel converter <b>410</b> converts 4-bits of serial data sequentially received via the data pin DQi into parallel data, and the parallel to serial converter <b>420</b> converts 4-bits of parallel data to 4-bits of serial data and sequentially outputs the serial data via the data pin DQi.

0036The data position controller <b>430</b> positions the 4-bits of data based on the use of a sequential address increase scheme or an interleave address increase scheme. In other words, the data position controller <b>430</b> determines the positions of the 4-bits of data in the four memory cell array blocks <b>100</b>_i (i=1, 2, 3, 4).

0037The decoder <b>300</b> translates an address that designates a memory cell for the data to be input to and/or output from in the memory cell array <b>100</b>. The decoder <b>300</b> includes a row address pre-decoder <b>310</b>, a row decoder <b>320</b>, a column address pre-decoder <b>330</b>, and first through fourth column decoders <b>340</b>_i (i=1, 2, 3, 4).

0038The row address pre-decoder <b>310</b> pre-translates a row address RA that is input into the integrated circuit memory device. Here, the row address RA consists of a plurality of bits, and a predetermined number of bits can be consecutively pre-translated for a predetermined number of times. The row decoder <b>320</b> translates a signal that is output from the row address pre-decoder <b>310</b>, selects one row (word line) from each of the memory cell array blocks <b>100</b>_i (i=1, 2, 3, 4), and activates the selected row.

0039The column address pre-decoder <b>330</b> pre-translates a column address CA that is input into the integrated circuit memory device. The column address pre-decoder <b>330</b> classifies a plurality of bits of a column address CA into a plurality of groups, each of which includes a predetermined number of bits, and decodes the bits to generate a pre-decoding signal DCA. The column address pre-decoder <b>330</b> includes a 012 pre-decoder (not shown in <figref idref="DRAWINGS">FIG. 2</figref>) that is described further below with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

0040The first through fourth column decoders <b>340</b>_i (I=1, 2, 3, 4) receive the pre-decoding signal DCA from the column address pre-decoder <b>330</b>, decode the pre-decoding signal DCA, and activate one column select line. The sense amplifier <b>440</b> amplifies the data output from the memory cell array <b>100</b>. The sense amplifier <b>440</b> also controls the positions of the 4-bits of parallel data output from the memory cell array <b>100</b>, i.e., the order of the 4-bits of parallel data. The function of the sense amplifier <b>400</b> is similar to a function of the data position controller <b>430</b> that controls the order of the input data, therefore, further description of the sense amplifier will be omitted.

0041The buffer <b>200</b> receives a signal from, for example, a device outside of the memory device, and converts the signal into an internal signal. The buffer <b>200</b> may also convert an internal signal into an external signal. In certain embodiments, the buffer <b>200</b> latches the signal. As illustrated, the buffer <b>200</b> includes an address buffer <b>210</b>, a row address buffer <b>220</b>, a column address buffer <b>230</b>, a command buffer <b>240</b>, a clock buffer <b>250</b>, a data buffer <b>260</b>, and a data strobe signal buffer <b>270</b>.

0042The address buffer <b>210</b> stores an address signal that is input via an address pin. The row address buffer <b>220</b> and the column address buffer <b>230</b> stores a row address signal and a column address signal, respectively, in response to a predetermined command to output the row address RA and the column address CA. The clock buffer <b>250</b> stores a clock CLK that is input via a clock pin, and the data strobe signal buffer <b>270</b> stores a data strobe signal DQS. The data buffer <b>260</b> stores data that is input/output via each data pin DQi.

0043Referring now to <figref idref="DRAWINGS">FIG. 3</figref>, a circuit diagram illustrating a portion of the column address pre-decoder <b>330</b> illustrated in <figref idref="DRAWINGS">FIG. 2</figref> will be discussed. The circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, which is included in the column address pre-decoder <b>330</b> of <figref idref="DRAWINGS">FIG. 2</figref>, receives and pre-decodes 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA. The circuit shown in <figref idref="DRAWINGS">FIG. 3</figref> is a 012 pre-decoder <b>500</b>. The 012 pre-decoder <b>500</b> pre-translates the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA to generate first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7). The first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) are input to the first through fourth column decoders <b>340</b>_i (i=1, 2, 3, 4) with other pre-decoding signals, which activates a plurality of column select lines that designate the columns where the 8-bits of parallel data will be input to and/or output from.

0044As illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, The 012 pre-decoder <b>500</b> includes a decoding unit <b>510</b>, a logic circuit <b>520</b>, a grouping unit <b>530</b>, and a pre-decoding signal generator <b>540</b>. The decoding unit <b>510</b> translates 3-bits CAi (i=0–2) of the column address CA to generate first through eighth output signals DSi (i=0–7), only one of which is activated. If the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA are 000, 001, 010, 100, 011, 101, 110 or 111, the 012 decoder <b>500</b> activates a first output signal DS<b>0</b>, a second output signal DS<b>1</b>, a third output signal DS<b>2</b>, a fourth output signal DS<b>3</b>, a fifth output signal DS<b>4</b>, a sixth output signal DS<b>5</b>, a seventh output signal DS<b>6</b> or an eighth output signal DS<b>7</b>, respectively.

0045To perform the above function the decoding unit <b>510</b> may include a plurality of inverters and/or a plurality of AND gates. In embodiments of the present invention illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, each of the AND gates is realized by a 3-input NAND gate and an inverter. The first bit CA<b>0</b> of the column address CA or an inverted signal of the first bit CA<b>0</b>, the second bit CA<b>1</b> of the column address signal CA or an inverted signal of the second bit CA<b>1</b>, and the third bit CA<b>2</b> of the column address signal CA or an inverted signal of the third bit CA<b>2</b> are input to each of the NAND gates of the decoding unit <b>510</b>.

0046The logic circuit <b>520</b> receives the first through eighth output signals DSi (i=0–7) from the decoding unit <b>510</b> and outputs first through eighth logic signals LSi (i=0–7), only one of which is activated according to a predetermined mode control signal. The mode control signal includes a burst length control signal BL<b>4</b> representing the burst length of the integrated circuit memory device, a sequential mode signal SEQUENTIAL representing a sequential address increase scheme, and an interleave mode signal INTERLEAVE representing an interleave address increase scheme. The burst length control signal BL<b>4</b> is logic high level (1) when the burst length of the integrated circuit is set to 4-bits. The sequential mode signal SEQUENTIAL is set to a logic high level when the sequential address increase scheme is used and the interleave mode signal INTERLEAVE is set to a logic high level when the interleave address increase scheme is used.

0047In certain embodiments of the present invention, the burst length of the integrated circuit memory device is 8-bits and the sequential address increase scheme is used. In these embodiments, signals of the first through eighth logic signals LSi (i=0–7) corresponding to the activated signals of the first through eighth signals DSi (i=0–7) output from the decoder <b>510</b> are activated. In other words, one of the first through eighth logic signals LSi (i=0–7) corresponding to the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA is activated. If the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> are 000, respectively, the first logic signal LS<b>0</b> is activated. If the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> are 001, respectively, the second logic signal LS<b>1</b> is activated and so on. In particular, 010 corresponds to logic signal LS<b>2</b>, 100 corresponds to logic signal LS<b>3</b>, 011 corresponds to logic signal LS<b>4</b>, <b>101</b> corresponds to logic signal LS<b>5</b>, 110 corresponds to logic signal LS<b>6</b> and 111 corresponds to logic signal LS<b>7</b>.

0048In further embodiments of the present invention, the burst length of the integrated circuit memory device is 4-bits and the interleave address increase scheme is used. In these embodiments, the first logic signal LS<b>0</b> or the fifth logic signal LS<b>4</b> is activated according to the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA. In other words, the first logic signal LS<b>0</b> is activated if the third bit CA<b>2</b> is <b>0</b> and the fifth logic signal LS<b>4</b> is activated if the third bit CA<b>2</b> is 1. Accordingly, the first 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA are not considered in these embodiments.

0049To perform the above function, the logic circuit <b>520</b> may include a plurality of 2-input AND gates, a plurality of NOR gates, and a plurality of inverters as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. The grouping unit <b>530</b> combines four hard-wired sequential signals of the first through eighth logic signals LSi (i=0–7) output from the logic circuit <b>520</b> into a group or plurality of groups. In other words, the activated logic signal is combined with the three sequential logic signals directly following the activated logic signal into a first group, four signals of the group being activated at the same time.

0050For example, if the first logic signal LS<b>0</b> is set to a logic high, signals GS<b>0</b> through GS<b>3</b> corresponding to the first through fourth logic signals LS<b>0</b> through LS<b>3</b> are combined into a first group and activated in a logic low (0) at the same time. Signals GS<b>4</b> through GS<b>7</b> corresponding to the remaining logic signals, i.e., the fifth through eighth logic signals LS<b>4</b> through LS<b>7</b>, are combined into a second group and not activated in a logic high. By way of further example, if the second logic signal LS<b>1</b> is activated, the signals GS<b>1</b> through GS<b>4</b> corresponding to the second through fifth logic signals LS<b>1</b> through LS<b>4</b> are combined into a first group and activated to a logic low at the same time. The other signals GS<b>5</b> through GS<b>7</b> and GS<b>0</b> are combined into a second group and output. Signals belonging to the first group that are activated and signals belonging to the second group that are not activated are determined according to the logic signals that are activated by the above method.

0051To generate the signals belonging to the first and second groups, the grouping unit <b>530</b> may include a plurality of 4-input NOR gates, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. As illustrated, the 4-input NOR gates correspond to the signals GSi (i=0–7), respectively. The 4-input NOR gates receive four sequential logic signals, perform a NOR operation on the four sequential logic signals, and output a signal belonging to the first group or the second group. The logic signal received by the 4-input Nor gates depends on a value of K. Each of the 4-input NOR gates receives a K^th logic signal. If the value of K is a natural number from 4 to 8, each of the 4-input NOR gates receives a K logic signal, a K−1 logic signal, a K−2 logic signal, and a K−3 logic signal. If, on the other hand, the value of K is a natural number from 1 to 3, the 4-input NOR gates receive a K logic signal, a K+7 logic signal, a K+6 logic signal, and a K+5 logic signal. Accordingly, depending on the embodiment, K may be a natural number between 1 and 8.

0052For example, if K is 4, the 4-input NOR gate performs a NOR operation for the fourth logic signal LS<b>3</b> (K), the third logic signal LS<b>2</b> (K−1), the second logic signal LS<b>1</b> (K−2) and the first logic signal LS<b>0</b> (K−3) and outputs the fourth logic signal GS<b>3</b> corresponding to K, i.e., 4. If K is between 5 and 8, the 4-input NOR gate performs the same operations as when K is 4. If, on the other hand, K is 1, the 4-input NOR gate performs a NOR operation for the first logic signal LS<b>0</b> (K), the eighth logic signal LS<b>7</b> (K+7), the seventh logic signal LS<b>6</b> (K+6), and the sixth logic signal LS<b>5</b> (K+5) and outputs the signal GS<b>0</b> corresponding to K, i.e., 1. If K is 2 or 3, the 4-input NOR gate performs the same operations as when K is 1.

0053The pre-decoding signal generator <b>540</b> includes a first switch group <b>541</b> and a second switch group <b>542</b> which are turned on and/or off in response to a first control signal CSLEP<b>0</b> and a second control signal CSLEP<b>1</b>, respectively. Switches belonging to the first switch group <b>541</b> are turned on in response to the first control signal CSLEP<b>0</b> and output the signals GS<b>0</b> through GS<b>7</b> belonging to the first and second groups as the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7). Therefore, if the first control signal CSLEP<b>0</b> is activated, signals of the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) corresponding to the first group are activated in logic high and signals corresponding to the second group are not activated and remain at a logic low.

0054Switches belonging to the second switch group <b>542</b> are turned on in response to the second control signal CSLEP<b>1</b> and output the inverted signals of the signals GS<b>0</b> through GS<b>7</b> belonging to the first and second groups as the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7). Therefore, if the second control signal CSLEP<b>1</b> is activated, signals of the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) corresponding to the first group are not activated and remain at a logic low and signals corresponding to the second group are activated to a logic high.

0055To latch the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7), the pre-decoding signal generator <b>540</b> may further include a latch <b>543</b> which inputs the signal output from an first inverter into a second inverter. The first and second control signals CSLEP<b>0</b> and CSLEP<b>1</b> are generated for a first cycle of the clock CLK and a second cycle of the clock CLK, respectively. During the first cycle of the clock CLK, 4-bits of the 8-bits of parallel data that is first converted into parallel data are input and/or output. During the second cycle of the clock CLK, the other 4-bits of parallel data are input and/or output. In certain embodiments of the present invention, there is about a two CLK cycle difference between the first cycle and the second cycle.

0056For example, if signals GS<b>0</b> through GS<b>3</b> of the signals GS<b>0</b> through GS<b>7</b> output from the grouping unit <b>530</b> belong to the first group, the first through fourth pre-decoding signals DCA<b>012</b><i>(i=0–3) are activated to a logic “high” for the first cycle of the clock CLK. The remaining signals GS<b>4</b> through GS<b>7</b>, thus, belong to the second group and are not activated and remain at a logic low level.

0057The signals GS<b>0</b> through GS<b>7</b> are inverted and output from the grouping unit <b>530</b>, i.e., the signals belonging to the first and second groups. The signals that belong to the first group are not activated and the signals that belong to the second group are activated. The inverted signals belonging to the first and second groups are output as the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) in response to the second control signal CSLEP<b>1</b> that is activated for the second cycle of the clock CLK. Thus, the fifth through eighth pre-decoding signals DCA<b>012</b><i>(i=4–7) are activated for the second cycle of the clock CLK. In other words, the fifth through eighth pre-decoding signals DCA<b>012</b><i>(i=4–7) are activated to a logic “high” for the second cycle of the clock CLK according to the signals belonging to the second group.

0058Referring now to <figref idref="DRAWINGS">FIGS. 2 and 3</figref>, the process of selecting a column that data will be input to or output from, according to the first through eighth pre-decoding signals DCA<b>012</b><i>(i=1–7) will be described. The first and fifth pre-decoding signals DCA<b>012</b><<b>0</b>>, DCA<b>012</b><<b>4</b>> are input to a first column decoder <b>340</b>_<b>1</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The second and sixth pre-decoding signals DCA<b>012</b><<b>1</b>>, DCA<b>012</b><<b>5</b>> are input to a second column decoder <b>340</b>_<b>2</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The third and seventh pre-decoding signals DCA<b>012</b><<b>2</b>>, DCA<b>012</b><<b>6</b>> are input to a third column decoder <b>340</b>_<b>3</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The fourth and eighth pre-decoding signals DCA<b>012</b><<b>3</b>>, DCA<b>012</b><<b>7</b>> are input to a fourth column decoder <b>340</b>_<b>4</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The first through fourth column decoders <b>340</b>_<b>1</b> through <b>340</b>-<b>4</b> are not shown in detail and receive other pre-decoding signals, respectively.

0059The first through fourth column decoders <b>340</b>_i (i=0–4) activate column select lines CSLi, CSLj, CSLk, and CSLl, respectively, each of which designates one column in a corresponding one of the memory cell array blocks <b>100</b>_i (i=1–4), according to each of the received pre-decoding signals DCA. In particular, the first column decoder <b>340</b>_<b>1</b> activates one column select line CSLi in the first memory cell array block <b>100</b>_<b>1</b>. The second column decoder <b>340</b>_<b>2</b> activates one column select line CSLj in the second memory cell array block <b>100</b>_<b>2</b>. The third column decoder <b>340</b>_<b>3</b> activates one column select line CSLk in the third memory cell array block <b>100</b>_<b>3</b>. The fourth column decoder <b>340</b>_<b>4</b> activates one column select line CSLl in the fourth memory cell array block <b>100</b>_<b>4</b>.

0060The data position controller <b>430</b> controls which data is input into and/or output from each of columns that are designated by the activated column select lines CSLi, CSLj, CSLk, and CSLl. The data position controller <b>430</b> will be discussed further below.

0061Referring now to tables 1 and 2 set out below. Table 1 illustrates various signals discussed above with respect to <figref idref="DRAWINGS">FIG. 3</figref>. In particular, the values of the following signals are illustrated: CA<b>2</b>, CA<b>1</b>, CA<b>0</b>, DS<b>0</b> through DS<b>7</b>, LS<b>0</b> through LS<b>7</b>, CS<b>0</b> through CS<b>7</b> and DCA<b>012</b><<b>0</b>:<b>7</b>>. Table 1 illustrates the values of these signals when the integrated circuit device has a bit length of 8-bits and uses a sequential address increase scheme. In other words, Table 1 illustrates the signal values when BL<b>4</b>=0, INTERLEAVE=0 and SEQUENTIAL=1.

0062<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="182pt" align="left" /><colspec colname="1" colwidth="77pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="1" rowsep="1">TABLE 1</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>DCA012<0:7></entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="8"><colspec colname="1" colwidth="28pt" align="center" /><colspec colname="2" colwidth="21pt" align="center" /><colspec colname="3" colwidth="21pt" align="center" /><colspec colname="4" colwidth="42pt" align="center" /><colspec colname="5" colwidth="35pt" align="center" /><colspec colname="6" colwidth="35pt" align="center" /><colspec colname="7" colwidth="42pt" align="center" /><colspec colname="8" colwidth="35pt" align="center" /><tbody valign="top"><row><entry>CA2</entry><entry>CA1</entry><entry>CA0</entry><entry>DS0–DS7</entry><entry>LS0–LS7</entry><entry>GS0–GS7</entry><entry>CSLEP0</entry><entry>CSLEP1</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row><row><entry>0</entry><entry>0</entry><entry>0</entry><entry>10000000</entry><entry>10000000</entry><entry>00001111</entry><entry>11110000</entry><entry>00001111</entry></row><row><entry>0</entry><entry>0</entry><entry>1</entry><entry>01000000</entry><entry>01000000</entry><entry>10000111</entry><entry>01111000</entry><entry>10000111</entry></row><row><entry>0</entry><entry>1</entry><entry>0</entry><entry>00100000</entry><entry>00100000</entry><entry>11000011</entry><entry>00111100</entry><entry>11000011</entry></row><row><entry>0</entry><entry>1</entry><entry>1</entry><entry>00010000</entry><entry>00010000</entry><entry>11100001</entry><entry>00011110</entry><entry>11100001</entry></row><row><entry>1</entry><entry>0</entry><entry>0</entry><entry>00001000</entry><entry>00001000</entry><entry>11110000</entry><entry>00001111</entry><entry>11110000</entry></row><row><entry>1</entry><entry>0</entry><entry>1</entry><entry>00000100</entry><entry>00000100</entry><entry>01111000</entry><entry>10000111</entry><entry>01111000</entry></row><row><entry>1</entry><entry>1</entry><entry>0</entry><entry>00000010</entry><entry>00000010</entry><entry>00111100</entry><entry>11000011</entry><entry>00111100</entry></row><row><entry>1</entry><entry>1</entry><entry>1</entry><entry>00000001</entry><entry>00000001</entry><entry>00011110</entry><entry>11100001</entry><entry>00011110</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0063Furthermore, Table 2 illustrates the values of the signals set out above when the integrated circuit device either has a bit length of 4-bits and uses an sequential address increase scheme, i.e., BL<b>4</b>=1 and SEQUENTIAL=1 or uses a interleave address increase scheme, i.e., when INTERLEAVE=1.

0064<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="182pt" align="left" /><colspec colname="1" colwidth="77pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="1" rowsep="1">TABLE 2</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>DCA012<0:7></entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="8"><colspec colname="1" colwidth="28pt" align="center" /><colspec colname="2" colwidth="21pt" align="center" /><colspec colname="3" colwidth="21pt" align="center" /><colspec colname="4" colwidth="42pt" align="center" /><colspec colname="5" colwidth="35pt" align="center" /><colspec colname="6" colwidth="35pt" align="center" /><colspec colname="7" colwidth="42pt" align="center" /><colspec colname="8" colwidth="35pt" align="center" /><tbody valign="top"><row><entry>CA2</entry><entry>CA1</entry><entry>CA0</entry><entry>DS0–DS7</entry><entry>LS0–LS7</entry><entry>GS0–GS7</entry><entry>CSLEP0</entry><entry>CSLEP1</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row><row><entry>0</entry><entry>0</entry><entry>0</entry><entry>10000000</entry><entry>10000000</entry><entry>00001111</entry><entry>11110000</entry><entry>00001111</entry></row><row><entry>0</entry><entry>0</entry><entry>1</entry><entry>01000000</entry><entry>10000000</entry><entry>00001111</entry><entry>11110000</entry><entry>00001111</entry></row><row><entry>0</entry><entry>1</entry><entry>0</entry><entry>00100000</entry><entry>10000000</entry><entry>00001111</entry><entry>11110000</entry><entry>00001111</entry></row><row><entry>0</entry><entry>1</entry><entry>1</entry><entry>00010000</entry><entry>10000000</entry><entry>00001111</entry><entry>11110000</entry><entry>00001111</entry></row><row><entry>1</entry><entry>0</entry><entry>0</entry><entry>00001000</entry><entry>00001000</entry><entry>11110000</entry><entry>00001111</entry><entry>11110000</entry></row><row><entry>1</entry><entry>0</entry><entry>1</entry><entry>00000100</entry><entry>00001000</entry><entry>11110000</entry><entry>00001111</entry><entry>11110000</entry></row><row><entry>1</entry><entry>1</entry><entry>0</entry><entry>00000010</entry><entry>00001000</entry><entry>11110000</entry><entry>00001111</entry><entry>11110000</entry></row><row><entry>1</entry><entry>1</entry><entry>1</entry><entry>00001000</entry><entry>00001000</entry><entry>11110000</entry><entry>00001111</entry><entry>11110000</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0065Referring now to <figref idref="DRAWINGS">FIG. 4</figref>, a diagram illustrating the operation of the 012 pre-decoder <b>500</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> according to embodiments of the present invention will be discussed. As illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the 012 pre-decoder <b>500</b> receives 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA. The 3-bits of the column address CA form eight combinations that range from 000 to 111. The example illustrated in <figref idref="DRAWINGS">FIG. 4</figref> assumes that the 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA that are input with a read/write command before 8-bits of serial data are input, i.e., a selected address, are “001” and that a the sequential address increase scheme is used.

0066Referring to both <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, if 001 is input as 3-bits of the column address CA, the decoding unit <b>510</b> translates 001 and activates the second output signal DS<b>1</b>. As discussed above, in embodiments of the present invention having an 8-bit integrated circuit memory device and operating in sequential mode, the burst length control signal BL<b>4</b> and the interleave mode signal INTERLEAVE are set to a logic low, and the sequential mode signal SEQUENTIAL is set to a logic high. Accordingly, the logic circuit <b>520</b> that is controlled by the burst length signal BL<b>4</b>, the interleave signal INTERLEAVE, and the sequential mode signal SEQUENTIAL, activates the second logic signal LS<b>1</b> corresponding to the second output signal DS<b>1</b>.

0067If the second logic LS<b>1</b> is activated, the grouping unit <b>530</b> groups the signal GS<b>1</b> corresponding to the second logic signal LS<b>1</b> and three signals GS<b>2</b>, GS<b>3</b>, and GS<b>4</b> following the signal GS<b>1</b> as the first group and activates the signals GS<b>1</b> through GS<b>4</b>.

0068During the first cycle, the second through fifth pre-decoding signals DCA<b>012</b><i>(i=1–4) corresponding to the signals GS<b>1</b> through GS<b>4</b> that belong to the first group are activated on high level 1 under control of the first control signal CSLPE<b>0</b> and pre-decoding signals DCA<b>012</b><i>(i=0, 5, 6, 7) corresponding to the signals GS<b>5</b> through GS<b>7</b> and GS<b>0</b> that belong to the second group are not activated at a low level 0. Each of the second through fifth pre-decoding signals DCA<b>012</b><i>(i=1–4) correspond to 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA that are 001, 010, 011 or 100. Each of the first and sixth through eighth pre-decoding signals DCA<b>012</b><i>(i=0, 5, 6, 7), correspond to 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of the column address CA that are 000, 101, 110, or 111.

0069During the second cycle, the first and sixth through eighth pre-decoding signals DCA<b>012</b><i>(i=0, 5, 6, 7) that were not activated during the first cycle are activated on high level “1” due to the inversion of the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7). During this cycle, the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) are inverted by inverting the signals GS<b>1</b> through GS<b>4</b> belonging to the first group and the signals GS<b>5</b> through GS<b>7</b> and GS<b>0</b> belonging to the second group.

0070Referring now to <figref idref="DRAWINGS">FIG. 5</figref>, a diagram illustrating operations of the data position controller <b>430</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> will be discussed. A process according to certain embodiments of the present invention for controlling the positions of 4-bits of data D<b>0</b> through D<b>3</b> that are sequentially input via one data pin DQ will be described.

0071If the burst length is 8-bits, the data position controller <b>430</b> can control the positions of 4-bits of parallel data D<b>0</b> through D<b>3</b> using only 2 bits CA<b>1</b> and CA<b>0</b> of the column address CA as when the burst length is 4-bits.

0072In certain embodiments of the present invention, data is input from, for example, a device outside the memory device, i.e., data is written to the memory device. For example, as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, four sequential serial data bits D<b>0</b> through D<b>3</b> are converted into parallel data bits by the serial to parallel convertor. The data position controller <b>430</b> controls the position of the parallel data D<b>0</b> through D<b>3</b> in one of four memory cell array blocks <b>100</b>_i (i=1–4). To input and/or output data, one input and/or output (I/O) line Qi (i=1–3) corresponding to each of the four memory cell array blocks <b>100</b>_i (i=1–4) is included. In other words, first through fourth I/O lines Q<b>0</b> through Q<b>3</b> are connected to first through fourth memory cell array blocks <b>100</b>_<b>1</b> through <b>100</b>_<b>4</b>, respectively.

0073Referring now to <figref idref="DRAWINGS">FIG. 6</figref>, a diagram illustrating the positions of data according to address increase schemes according to embodiments of the present invention will be discussed. As discussed above, address increase schemes may include, for example, a sequential address increase scheme and/or an interleave address increase scheme.

0074As illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, if 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA are 00, the first through fourth data D<b>0</b> through D<b>3</b> are input to the first through fourth I/O lines Q<b>0</b> through Q<b>3</b>, respectively, in either the sequential address increase scheme or the interleave address increase scheme.

0075As further illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, if 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA are 01, the first through fourth data D<b>0</b> through D<b>3</b> are input to the second through third and first I/O lines Q<b>1</b> through Q<b>2</b> and Q<b>0</b>, respectively, in the sequential address increase scheme. However, the first through fourth data D<b>0</b> through D<b>3</b> are input to the second, first, fourth, and third I/O lines Q<b>1</b>, Q<b>0</b>, Q<b>3</b>, and Q<b>2</b>, respectively, in the interleave address increase scheme.

0076As further illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, if 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA are 10, the first through fourth data D<b>0</b> through D<b>3</b> are input to the third, fourth, first, and second I/O lines Q<b>2</b>, Q<b>3</b>, Q<b>0</b>, and Q<b>1</b>, respectively, in either the sequential address increase scheme or the interleave address increase scheme.

0077As further illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, if 2 bits CA<b>1</b> and CA<b>0</b> of the column address CA are 11, the first through fourth data D<b>0</b> through D<b>3</b> are input to the fourth, first, second, and third I/O lines Q<b>3</b>, Q<b>0</b>, Q<b>1</b>, and Q<b>2</b>, respectively, in the sequential address increase scheme. However, the first through fourth data D<b>0</b> through D<b>3</b> are input to the fourth, third, second, and first I/O lines Q<b>3</b>, Q<b>2</b>, Q<b>1</b>, and Q<b>0</b>, respectively, in the interleave address increase scheme.

0078The operation of the integrated circuit memory device with respect to the other 4-bits of parallel data D<b>4</b> through D<b>7</b> is similar to the operation described above with respect to first 4-bits of parallel data D<b>0</b> through D<b>3</b> with reference to <figref idref="DRAWINGS">FIGS. 5 and 6</figref>, therefore, further description of these operations will be omitted. Furthermore, data that is output from the memory cell array blocks is output similar to the operation described above with respect to inputting data into the memory cell array blocks, therefore, further description of this operation will also be omitted. It will be understood that the sense amplifier <b>440</b> illustrated in <figref idref="DRAWINGS">FIG. 2</figref> controls the positions of output data.

0079As briefly described above with respect to <figref idref="DRAWINGS">FIGS. 1 through 6</figref>, embodiments of the present invention provide an integrated circuit device including a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. In some embodiments of the present invention, the integrated circuit device can support both the existing sequential and interleave address increase schemes. Integrated circuit devices according to embodiments of the present invention include a 012 pre-decoder <b>500</b> that outputs first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) using 3-bits CA<b>2</b>, CA<b>1</b>, and CA<b>0</b> of a column address CA to control column select lines for selecting columns where data will be input to and output from. Four of the first through eighth pre-decoding signals DCA<b>012</b><i>(i=0–7) output from the 012 pre-decoder <b>500</b> are activated during the first cycle based on the start column address and the other four pre-decoding signals are activated during the second cycle after the first through eighth pre-decoding signals (DCA<b>012</b><i>, i=0–7) are inverted. Accordingly, an integrated circuit memory device according to embodiments of the present invention may not include a complicated circuit such as a counter for generating a column address in the integrated circuit memory device. Furthermore, since it is possible to control the order of how the data is input and/or output using 2-bits CA<b>1</b> and CA<b>0</b> of the column address CA, the order can also be used when the burst length is 4-bits.

0080In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.