Integrated circuit memory device supporting n bit prefetch scheme and 2n burst length

Integrated circuit memory device supporting N-bit prefetch and design and 2N data cluster length

Related applications

This application is related to and claims priority from Korean Patent Application No. 2002-1774 filed on January 11, 2002, the disclosure of which is incorporated herein by reference.

Technical field

The present invention describes an integrated circuit device; more specifically, the present invention describes a synchronous dynamic random access memory (SDRAM).

Prior art

In order to improve the operating speed of the integrated circuit device, the integrated circuit memory device has rapidly moved from the dynamic random access memory (DRAM) of the fast operation mode (such as the fast page mode dynamic random access memory (DRAM), or extended The sexual data output (EDO) dynamic random access memory (DRAM)) developed into SDRAM, and then from SDRAM to double data rate (DDR) DRAM. Several DRAM manufacturing companies are currently studying the next generation of memory devices following this DDR SDRAM. For example, this new generation can use DDR2 SDRAM based on a 4-bit prefetch design instead of DDR SDRAM based on a 2-bit prefetch design.

The Electronic Component Engineering Design and Development Joint Committee (JEDEC) recommended that the DDR2 SDRAM utilize a 4-bit prefetch design and a "4-bit" fixed-length data cluster. An integrated circuit memory device based on a 4-bit prefetch design and a "4-bit" fixed-length data cluster does not use 2-bit input row address signals of 2 to activate multiple row selection lines. Bits. In other words, if two bits in the 4-bit row address signal are not used, the row address signal can automatically activate only four row selection lines. In addition, integrated circuit memory devices based on a 4-bit prefetch design and a "4-bit fixed-length data cluster are designed based on a first input row address and the address used (such as A sequential address increase design or an interleaved address increase design) to determine the data item order.

Start with a "4-bit" data bundle length mode corresponding to each of the four possible modes (using the two bits in the 4-bit row address signal--that is, 00, 01, 10, and 11) The four line selection lines on irrespective of the address of the starting line. For example, if the two bits of the starting row address are 00, the bits corresponding to one of the row addresses on a selection line and the two corresponding to the starting row address of 00 must be 01, 10. Or 11. If so, if the starting row address is 01, the bits corresponding to one of the row addresses on a selection line must be 10, 11, or 00.

As mentioned above, if a "4-bit" data cluster length is used with the same 4-bit prefetch design, the total number of bits to be prefetched is four, and the total number of sequential input / output data (That is, the data bundle length) is 4 bits. If so, because the lengths are the same, a 4-bit data pattern can be implemented in an integrated circuit memory device using the 4-bit prefetch design. However, if the data cluster is 8 bits long, it is not possible to select all of the row selection lines using the 2 bits of the row address as discussed above. In order to make eight row selection lines possible, three bits are considered when using a sequential address to increase the design. However, if an interleaved address is used to increase the design, 3 bits need not be considered.

Traditional integrated circuit memory devices based on a 2-bit prefetch design and a "4-bit" data bundle length typically include a bit counter. The address counter generates addresses, where the addresses correspond to "use two bits in the 4-bit row address signal to generate row selection lines for the next cycle". Therefore, as far as integrated circuit memory devices that utilize a 4-bit prefetch design and an "8-bit" data bundle length, supporting a sequential address increase design can be difficult, as discussed above, It typically considers 3 bits. If so, JEDEC recommends fixing the data bundle length of a DDR2 SDRAM to 4 bits.

An integrated circuit memory device using the 4-bit prefetch design may have an address counter that generates addresses, where the addresses correspond to "row selection lines generated for the next cycle". However, this 4-bit prefetch design can be complicated. In addition, if such clock cycles are reduced, the internal margins of the integrated circuit device will become shorter, thereby limiting the operating frequency of the integrated circuit device.

The demand for "8-bit" data bundle lengths is increasing because it can relatively increase the speed of the integrated circuit memory device. If the total number of bits to be prefetched is increased to increase the speed of the integrated circuit memory device, the total number of internal data input / output (I / O) lines is also typically increased. Some traditional SDRAMs can operate in an "8-bit" data cluster length mode, and use half-byte sequential addressing to increase the design to meet the requirements of the "8-bit" data cluster length. However, implementing a general SDRAM to support the 8-bit data bundle length can be complicated. It also causes difficulties when supporting the sequential address increase design (where the sequential address increase design is usually used on an SDARM using a prefetch design).

SDRAMs utilizing the prefetch design typically use the sequential address increase design or the interleaved address increase design. However, SDRAMs utilizing this nibble sequential address increase design typically do not support a regular sequential address increase design.

If yes, when an integrated circuit device supporting "8-bit" data cluster length or "2x the total number of bits to be prefetched (for example, 4 bits)" can support both sequential and interleaved address increase designs It is preferable.

Summary of the Invention

A specific embodiment of the present invention provides an integrated circuit device including a double data transmission rate (DDR) integrated circuit memory device, wherein the DDR integrated circuit memory device is assembled to support an "N-2N" prefetch-data Plex length operation mode.

In some embodiments of the present invention, the DDR integrated circuit memory device is assembled to support a sequential address increase design and an interleaved address increase design. In some embodiments, the prefetch N is 4 and the data bundle length 2N is 8. In other specific embodiments, the prefetch N is 2 and the data bundle length 2N is 4.

In other embodiments of the present invention, the DDR integrated circuit memory device further includes a pre-decoder and a memory cell array. The pre-decoder receives a 3-bit row address signal and generates a plurality of pre-decoded signals. The memory cell array includes at least one memory cell array block for storing data of the data cluster length "2N". The pre-decoded signals activate a row of selection lines and specify the position of the data cluster length "2N" in the memory cell array block of the memory cell array.

In another embodiment of the present invention, the at least one memory cell array block includes first to fourth memory cell blocks. The DDR integrated circuit memory device may further include a data position controller, which is assembled to determine the first to fourth bits according to a first bit and a second bit of the 3-bit row address signal. The position of the data of the data cluster length "2N" in the memory cell array block.

In some embodiments of the present invention, the pre-decoder also includes a logic circuit that activates at least one logic signal in response to a mode control signal. The mode control signal may include a data cluster length control signal indicating the length of the "2N" data cluster, wherein a logic "high" indicates that the 2N data cluster length is a 4-bit data cluster length; a logic "low" indication The 2N data cluster length is an 8-bit data cluster length; when a sequential mode signal is a logic "high", the sequential mode signal indicates "use the sequential address to increase the design"; and when an interlace mode signal When it is a logic "high", the interleaving mode signal indicates "use the interleaving address to increase the design".

In other embodiments of the present invention, the at least one logic signal responds to a 3-bit row address signal. In some specific embodiments of the present invention, the at least one logic signal includes first to eighth logic signals, the data cluster length control signal is a logic "low, and the sequential mode signal is a logic "high. Each of the eight logic signals responds to a first bit, a second bit, and a third bit of the 3-bit row address signal.

In other specific embodiments, the at least one logic signal may include first to eighth logic signals. The data bundle length control signal is a logic "high", and the interlace mode signal is a logic "high". The first logic signal and the fifth logic signal respond to a third bit of the 3-bit row address signal.

In some specific embodiments of the present invention, the at least one logic signal includes first to eighth logic signals. The logic circuit can be further assembled to activate one of the eight logic signals, and combine the activated logic signal with the next three sequential logic signals to form a four-logic logic. The first group of signals. The logic circuit can be further assembled to form a second group containing four logic signals, wherein the second group includes the first to eighth logic signals and the remaining four are not connected with the activated The signals are combined to form the first group of logic signals. The logic signal of the first group can be activated in a first cycle of the clock in response to a first control signal; and the logic signal of the second group can be activated in a second cycle of the clock to In response to a second control signal.

Implementation

The invention will now be explained in more detail with reference to these accompanying drawings, which illustrate several specific embodiments of the invention. However, the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, but rather these specific embodiments are provided in order to provide a complete and complete disclosure of the invention. Invention, and the concept of the present invention is completely passed on to those skilled in the art. In these drawings, when an element is referred to as being "connected or "coupled to another element, the element can be directly connected or coupled to the other level, or there may be other intervening elements. In contrast, when an element is referred to as being "directly connected or "directly coupled to another element, there are no intervening elements. In all the drawings, the same reference number means the same element.

Specific embodiments of the present invention will be described below with reference to FIGS. 1 to 6. A specific embodiment of the present invention provides an integrated circuit device including a double data transmission rate (DDR) integrated circuit memory device, wherein the DDR integrated circuit memory device is assembled to support an "N-2N" prefetch-data Plex length operation mode. In some embodiments of the present invention, the integrated circuit device can support the current sequential and interleaved address increase designs. The integrated circuit device according to a specific embodiment of the present invention has the aforementioned functions by including a 012 pre-decoder 500, wherein the pre-decoder 500 uses three bits CA2, CA1, and CAO of a row address CA to output first The eighth pre-decoded signal DCA012 <i> (i = 0-7) is used to control a row selection line for selecting rows of data input and output. In the first cycle, start the four pre-decoded signals among the first to eighth pre-decoded signals DCA012 <i> (i = 0-7) output by the 012 pre-decoder 500 according to the starting row address; And after inverting the first to eighth pre-decoded signals (DCA012 <i>, i = 0-7), the remaining four pre-decoded signals are activated in the second cycle. If so, an integrated circuit memory device according to a specific embodiment of the present invention may not include a complicated circuit (such as a counter for generating a row of addresses in the integrated circuit memory device). In addition, because it may use the two bits CA1 and CA0 of the row address CA to control the order of the data input and / or output, the order can also be used when the data cluster length is 4 bits.

Referring now to FIG. 1, the operation of a synchronous dynamic random access memory (SDRAM) according to an embodiment of the present invention will be discussed. The specific embodiment of the SDRAM illustrated in FIG. 1 utilizes a ratio of N to 2N for prefetch and data cluster length, such as a 4-bit prefetch design and an "8-bit" data cluster length. If so, 8 bits DO ~ D7 of the data are sequentially input and / or output (I / O) through a data pin DQ of an integrated circuit memory device. It should be understood that the integrated circuit device according to a specific embodiment of the present invention may include one or more data pins DQ without departing from the scope of the present invention.

An address of a memory unit is selected for the data input into the integrated circuit substrate via the data I / O pin DQ. Select a single memory cell address for the 8 bits DO ~ D7 of the data. Once the address is selected, an "input data" command is issued as illustrated in the timing diagram of Fig. 1. Enter the 8 bits of the data on the rising and falling edges of a data flash control signal DQS. D0 ~ D7. The data flash control signal DQS initiates data input and synchronizes data with the clock signal CLK adjustment data. When data is being input (or read) into the integrated circuit memory device via the data pin DQ, the data flash control signal DQS is synchronized with the clock signal CLK, even if the DQS and the CLK have the same period And waveform; however, when data is not being input into the integrated circuit device, the data interrogation signal DQS has a predetermined level.

For example, data can be sequentially input into the integrated circuit device. In other words, you can enter D0 first and then D7 (or the eighth bit). A 4-bit prefetch design is used to sequentially input the first four bits D0, D1, D2, and D3 of the data into the integrated circuit device and convert them into parallel data. The sequence-parallel conversion is performed when the fourth data bit D3 is input into the integrated circuit memory device and the data is synchronized with a rising edge of the next clock CLK. The converted parallel data is simultaneously input into four memory cell array blocks 100_i (i = 1-4). The entire memory cell array 1J of the SDRAM using the 4-bit prefetch design can be divided into four memory cell array blocks 100i (i = 1-4).

The last four data bits D4, DS, D6, and D7 are sequentially input into the integrated circuit device, and when the eighth data bit D7 is input, and the data is synchronized with a rising edge of the next clock Data bits D4, DS, D6, and D7 are converted into parallel data. The parallel data can also be input into the four memory cell array blocks 100_i (i = 1-4) at the same time.

The data can be output (written) from the integrated circuit device using a method similar to the input of the data bits D0 to D7 described above. In other words, four data bits are sensed in parallel at a time from the four memory cell array blocks 100_i (i = 1-4) at the same time, and the four data bits are converted into sequence data. The serial data is output to a device outside the integrated circuit memory device via the data pin DQ.

Referring now to FIG. 2, a block diagram illustrating an integrated circuit memory device according to an embodiment of the present invention will be discussed. As illustrated in FIG. 2, the integrated circuit memory device includes a memory cell array 100, a buffer 200, a decoder 300, a serial-parallel converter 410, a parallel-serial converter 420, and a data A position controller 430 and a sense amplifier 440.

The memory cell array 100 may be divided into a plurality of memory cell array blocks. As illustrated in FIG. 2, some embodiments divide the memory cell array 100 into four memory cell array blocks 100 - i (i = 1, 2, 3, 4). The sequence-parallel converter 410 sequentially converts sequence data input into the integrated circuit device into parallel data. In other words, every time N data are input sequentially, there will be a corresponding N parallel data. The parallel-sequence converter 420 converts the N-parallel data output from the memory cell array 100 back to the N-sequence data.

In some specific embodiments of the present invention, an integrated circuit memory device having a data cluster length equal to 8 bits sequentially inputs and / or outputs 8 bits of sequence data through a data pin DQi. The sequence-parallel converter 410 converts 4 bits of sequence data received sequentially through the data pin DQi into parallel data; and the parallel-sequence converter 420 converts 4-bit parallel data into 4-bit Sequence data, and sequentially output the sequence data via the data pin DQi.

The data position controller 430 places four bits of the data according to a sequential address addition design or an interleaved address addition design. In other words, the data position controller 430 determines the positions of the four bits of the data in the four memory cell array blocks 100_i (i = 1, 2, 3, 4).

The decoder 300 translates an address that specifies a memory cell to the data to be input and / or output in the memory cell array 100. The decoder 300 includes a column address pre-decoder 310, a column decoder 320, a row address pre-decoder 330, and first to fourth row decoders 340_i (i = 1, 2, 3, 4).

The column address pre-decoder 310 translates a column address RA input into the integrated circuit memory device in advance. Here, the column address RA is composed of a plurality of bits, and a predetermined number of bits can be continuously translated in advance according to a predetermined number of times. The column decoder 320 translates a signal output from the column address pre-decoder 310; selects a column (character line) from each of the memory cell array blocks 100_i (i = 1, 2, 3, 4). ; And start the selected column.

The row address pre-decoder 330 translates a row address CA input into the integrated circuit memory device in advance. The row address pre-decoder 330 divides a plurality of bit classes of a row address CA into a plurality of groups (where each group includes a predetermined number of bits), and decodes the bits to generate a pre-decode Signal DCA. The row address pre-decoder 330 includes a 012 pre-decoder (not shown in FIG. 2), which will be further described below with reference to FIG. 3.

The first to fourth line decoders 340_i (i = 1, 2, 3, 4) receive the pre-decoded signal DCA in their own pre-decoder 330; decode the pre-decoded signal DCA; and start one Select the line. The sense amplifier 440 amplifies data output from the memory cell array 100. The sense amplifier 440 also controls the position of the four bits of the parallel data output by the memory cell array 100, that is, the order of the four bits of the parallel data. The function of the sense amplifier 400 is similar to that of the data position controller 430 that controls the sequence of input data, so it will not be described further.

The buffer 200 receives a signal from, for example, a device external to the memory device, and converts the signal into an internal signal. The buffer 200 can also convert an internal signal into an external signal. In some embodiments, the buffer 200 latches the signal. As illustrated, the buffer 200 includes a bit buffer 210, a column of address buffer 220, a row of address buffer 230, a command buffer 240, a clock buffer 250, a data buffer 260, and a data Flash control signal buffer 270.

The address buffer 210 stores an address signal input through an address pin. The column address buffer 220 and the row address buffer 230 respectively store a column address signal and a row address signal in response to a predetermined command of "outputting the column address RA and the row address CA". The clock buffer 250 stores a clock CLK input through a clock pin; and the data flash control signal buffer 270 stores a data flash control signal DQS. The data buffer 260 stores data input / output through each data pin DQi.

Referring now to FIG. 3, a circuit diagram illustrating a portion of the row address pre-decoder 330 exemplified in FIG. 2 will be discussed. The circuit shown in FIG. 3 (contained in the row address pre-decoder 330 of FIG. 2) receives and pre-decodes the three bits CA2, CA1, and CA0 of the row address CA. The circuit shown in FIG. 3 is a 012 pre-decoder 500. The 012 pre-decoder 500 translates the three bits CA2, CA1, and CA0 of the row address CA in advance to generate the first to eighth pre-decoded signals. DCA012 <i> (i = 0-7). The first to eighth pre-decoded signals DCA012 <i> (i = 0-7) are input to the first to fourth line decoders 340_i (i = 1, 2, 3, 4) (or the first to eighth pre-decoded signals DCA012 <i> (i = 0-7), together with other pre-decoded signals are input to the first to fourth line decoders 340_i (i = 1, 2, 3, 4)), to activate a plurality of row selection lines that specify the 8 bits of the parallel data to input and / or output the parallel data.

As illustrated in FIG. 3, the 012 pre-decoder 500 includes a decoding unit 510, a logic circuit 520, a grouping unit 530, and a pre-decoding signal generator 540. The decoding unit 510 translates the three bits CAi (i = 0-2) of the row address CA to generate the first to eighth output signals DSi (i = 0-7), where only one of the output signals is activated . If the three bits CA2, CA1, and CA0 of the row address CA are 000, 001, 010, 100, 011, 101, 110, or 111, the 012 decoder 500 starts a first output signal DS0, a first Two output signals DS1, a third output signal DS2, a fourth output signal DS3, a fifth output signal DS4, a sixth output signal D55, a seventh output signal DS6, or an eighth output signal DS7.

In order to perform the above functions, the decoding unit 510 may include a plurality of inverters and / or a plurality of intersection gates. In the specific embodiment of the present invention illustrated in FIG. 3, each of the intersection gates is implemented by a 3-input reverse gate and an inverter. A first bit CA0 of the row address CA or a reverse signal of the first bit CA0, a second bit CA1 of the row address signal CA or a reverse signal of the second bit CA1, And the third bit CA2 of the row address signal CA or an inverted signal of the third bit CA2 is input to each of the AND gates of the decoding unit 510.

The logic circuit 520 receives the first to eighth output signals DSi (i = 0-7) and the first to eighth logic signals LSi (i = 0-7) from the decoding unit 510, and according to a predetermined pattern, Control signal and only enable one of the logic signals. The mode control signal includes a data cluster length control signal BL4 representing the data cluster length of the integrated circuit memory device; a sequential mode signal SEQUENTIAL representing a sequential address increase design; and an interlace representing a staggered address increase design Mode signal INTERLEAVE. When the data cluster length of the integrated circuit is set to 4 bits, the data cluster length control signal BL4 is at a logic "high" level (1). When the design is added using the sequential address, the sequential mode signal SEQUENTIAL is set to a logical "high" level; and when the design is added using the interleaved address, the interlace mode signal INTERLEAVE is set to a logical "high" level .

In some specific embodiments of the present invention, the data cluster length of the integrated circuit memory device is 8 bits, and the sequential address is used to increase the design. In some specific embodiments, the first to eighth logic signals LSi (i = 0-7) corresponding to the first to eighth signals DSi (i = 0- 7) The signal on the activated signal. In other words, one of the first to eighth logic signals LSi (i = 0-7) is activated corresponding to the logic signals on the three bits CA2, CA1 and CA0 of the row address CA. If the three bits CA2, CA1 and CA0 are respectively 000, the first logic signal LS0 is activated; if the three bits CA2, CA1 and CA0 are respectively 001, the second logic signal is activated LS1; ... wait. In particular, 010 corresponds to logic signal LS2; 100 corresponds to logic signal LS3; 011 corresponds to logic signal LS4; 101 corresponds to logic signal LS5; 110 corresponds to logic signal LS6; and 111 corresponds to logic signal LS7.

In other embodiments of the present invention, the data cluster length of the integrated circuit memory device is 4 bits, and the interleaving address is used to increase the design. In these specific embodiments, the first logic signal LS0 or the fifth logic signal LS4 is activated according to the three bits CA2, CA1 and CA0 of the row address CA. In other words, if the third bit CA2 is 0, the first logic signal LS0 is activated; and if the third bit CA2 is 1, the fifth logic signal LS4 is activated. If so, the first two bits CA1 and CA0 of the row address CA are not considered in these specific embodiments.

In order to perform the above functions, the logic circuit 520 may include a plurality of 2-input intersection gates, a plurality of reverse OR gates, and a plurality of inverters (as illustrated in FIG. 3). The grouping unit 530 combines the four hard-line sequential signals of the first to eighth logic signals LSi (i = 0-7) output by the logic circuit 520 into a group or a plurality of groups. In other words, the activated logic signal is combined with the three sequential logic signals directly following it to form a first group, in which four signals of the group are simultaneously activated.

For example, if the first logic signal LSO is set to a logic "high, the signals GS0 to GS3 corresponding to the first to fourth logic signals LS0 to LS3 are combined into a first group, and A logic "low" (0) simultaneously activates the signals GS0 ~ GS3. The signals GS4 ~ GS7 corresponding to the remaining logic signals (ie, the fifth to eighth logic signals LS4 ~ LS7) are combined into a second group, and the signals GS4 ~ GS7 are not started with a logic "high" . For another example, if the second logic signal LS1 is activated, the signals GS1 to GS4 corresponding to the second to fifth logic signals LS1 to LS4 are combined into a first group, and the signals GS1 to GS4 are simultaneously activated. Into a logical "low". The remaining signals GS5 ~ GS7 and GS0 are combined into a second group, and GS5 ~ GS7 and GS0 are output. According to the logic signals activated by the above method, "a signal belonging to the first group is activated" and "a signal belonging to the second group is not activated".

In order to generate signals belonging to the first and second groups, the grouping unit 530 may include a plurality of 4-input inverting OR gates (as illustrated in FIG. 3). As exemplified, the 4-input reverse OR gates correspond to the signals GSi (i = 0-7), respectively. The 4-input inverse OR gates receive four sequential logic signals; perform an inverse OR operation on the four sequential logic signals; and output a signal belonging to the first group or the second group. The signal received by the 4-input reverse OR gates depends on a K value. Each of the 4-input negative OR gates receives a Kth logic signal. If the K value is a natural number between 4 and 8, each of the 4-input inverse OR gates receives a K logic signal, a K-1 logic signal, a K-2 logic signal, and a K- 3 logic signals. On the other hand, if the K value is a natural number between 1 and 3, then each of these 4-input invertors receives a K logic signal, a K + 7 logic signal, a K + 6 logic signal, And a K + 5 logic signal. If so, K may be a natural number between 1 and 8 according to this embodiment.

For example, if K is equal to 4, the 4-input inverse OR gate turns on the fourth logic signal LS3 (K), the third logic signal LS2 (K-1), the second logic signal LS1 (K-2), And the first logic signal LS0 (K-3) performs an inverse OR operation, and outputs the fourth logic signal GS3 corresponding to K (ie, 4). If K is between 5 ~ 8, the 4-input anti-OR gate performs the same operation when K is equal to 4. On the other hand, if K is equal to 1, then the 4-input reverse OR gate turns on the first logic signal LS0 (K), the eighth logic signal LS7 (K + 7), and the seventh logic signal LS6 (K + 6 ), And the sixth logic signal LS5 (K + 5) performs an inverse OR operation, and outputs the signal GS0 corresponding to K (ie, 1). If K is equal to 2 or 3, the 4-input reverse OR gate performs the same operation as when K is equal to 1.

The pre-decoding signal generator 540 includes a first switching group 541 and a second switching group 542. The first switching group 541 and the second switching group 542 are turned on and / or off to respond to a first A control signal CSLEP0 and a second control signal CSLEP1. Turn on the switching belonging to the first switching group 541 to respond to the first control signal CSLEP0, and output the signals GS0 ~ GS7 belonging to the first and second groups (such as the first to eighth pre-decoded The signal DCA012 <i> (i = 0-7) is the same). Therefore, if the first control signal CSLEP0 is activated, the first to eighth pre-decoded signals DCA012 <i> (i = 0-7) corresponding to the first group are activated with logic "high. And the signals corresponding to the second group are not activated, and the signals are kept at a logic "low.

Turn on the switching belonging to the second switching group 542 in response to the second control signal CSLEP1, and output the reverse signals of the signals GS0 ~ GS7 belonging to the first and second groups (such as the first to the first Eight pre-decoded signals are the same as DCA012 <i> (i = 0-7). Therefore, if the second control signal CSLEP1 is activated, the signals corresponding to the first group among the first to eighth pre-decoded signals DCA012 <i> (i = 0-7) are not activated, and The signals are kept at a logic "low" and the signals corresponding to the second group are activated to a logic "high".

In order to latch the first to eighth pre-decoded signals DCA012 <i> (i = 0-7), the pre-decoded signal generator 540 may further include an input of a signal output by a first inverter. A latch 543 of a second inverter. The first and second control signals CSLEP0 and CSLEP1 are generated at a first period and a second period of the clock CLK, respectively. In the first cycle of the clock CLK, 4 bits of the 8-bit parallel data that is first converted into parallel data are input and / or output. In the second cycle of the clock CLK, the remaining 4 bits of the parallel data are input and / or output. In some specific embodiments of the present invention, there are about two CLKs in the first cycle and the second cycle. Cycle difference.

For example, when GS0 ~ GS3 of the signals GS0 ~ GS7 output from the grouping unit 530 belong to the first group, the first to fourth decoded signals are pre-decoded in the first cycle of the clock CLK. DCA012 <i> (i = 0-3) is activated to a logic "high". If so, the signals GS4 ~ GS7 remaining in the second group are not activated, and the signals are kept at a logic "low" level.

The signals GS0 ~ GS7 are inverted, and the signals GS0 ~ GS7 (that is, the signals belonging to the first and second groups) are output from the grouping unit 530. Do not activate signals belonging to the first group; and activate signals belonging to the second group. Output the reverse signals belonging to the first and second groups (such as the first to eighth pre-decoded signals DCA012 <i> (i = 0-7)) in response to the clock CLK The second control signal CSLEP1 is activated in two cycles. If so, the fifth to eighth pre-decode signals DCA012 <i> (i = 4-7) are activated in the second cycle of the clock CLK. In other words, the fifth to eighth pre-decoded signals DCA012 <i> (i = 4-7) are activated to a logic "high according to the signals belonging to the second group and the second period of the clock CLK.

Referring now to FIGS. 2 and 3, a description will be given of a process of selecting a row in which data is input or output based on the first to eighth pre-decoded signals DCA012 <i> (i = 0-7). The first and fifth pre-decoded signals DCA012 <0> and DCA012 <4> are input to a first row decoder 340_1 of FIG. 2. The second and sixth pre-decoded signals DCA012 <1> and DCA012 <5> are input to a second row decoder 340_2 of FIG. 2. The third and seventh pre-decoded signals DCA012 <2> and DCA012 <6> are input to a third row decoder 340_3 of FIG. 2. The fourth and eighth pre-decoded signals DCA012 <3> and DCA012 <7> are input to a fourth row decoder 340_4 of FIG. 2. The first to fourth line decoders 340_1 to 340_4 are not specified in detail, and the first to fourth line decoders 340_1 to 340_4 respectively receive the remaining pre-decoded signals.

The first to fourth row decoders 340_i (i = 0-4) respectively activate row selection lines CSLi, CSLj, CSLk, and CSL1. Each of the row selection lines specifies a row in the corresponding memory cell array block according to each of the pre-decoded signals DCA received by the memory cell array block 100_i (i = 0-4). . In particular, the first row decoder 340_1 activates a row selection line CSLi in the first memory cell array block 100_1. The second row decoder 340_2 activates a row selection line CSLj in the second memory cell array block 100_2. The third row decoder 340_3 activates a row selection line CSLk in the third memory cell array block 100_3. The fourth row decoder 340_4 activates a row selection line CSL1 in the fourth memory cell array block 100_4.

The data position controller 430 controls which data inputs and / or outputs each row specified by the activated row selection lines CSLi, CSLj, CSLk, and CSL1. The data position controller 430 will be discussed further below.

Reference is now made to Tables 1 and 2 stated below. Table 1 illustrates the signals discussed above with respect to FIG. 3. In particular, the values of the following signals are illustrated by examples: CA2, CA1, CA0, DS0 ~ DS7, LS0 ~ LS7, CS0 ~ CS7, and DCA012 <0: 7>. Table 1 illustrates the values of these signals when the bit length of the integrated circuit device is 8 bits and the design is increased by using a sequential address. In other words, Table 1 illustrates the values of these signals when BL4 = 0, INTERLEAVE = 0, and SEQUENTIAL = 1.

<img file="TW200301901A_D0001.tif" />

In addition, Table 2 exemplifies the above cases when the bit length of the integrated circuit device is 4 bits and the design is added by a sequential address (ie, BL4 = 1 and SEQUENTIAL = 1), or The value of the signal stated when the bit length of the integrated circuit device is 4 bits and the design is increased by using an interleaved address (ie, BL4 = 1 and INTERLEAVE = 1).

<img file="TW200301901A_D0002.tif" />

Referring now to FIG. 47, an exemplary operation diagram of the 012 pre-decoder 500 shown in FIG. 3 according to a specific embodiment of the present invention will be discussed. As exemplified in FIG. 4, the 012 pre-decoder 500 receives the three bits CA2, CA1, and CA0 of the row address CA. The three bits of the row address CA form eight combinations, ranging from 000 to 111. The example illustrated in FIG. 4 assumes that "three bits entered by a read and write command in the row address CA before the eight bits of the sequence data (ie, a selected address) are input CA2, CA1, and CA0 are "001" and "add design using a sequential address".

Referring now to FIGS. 3 and 4, if 001 is input as the three bits of the row address CA, the decoding unit 510 translates 001 and activates the second output signal DS1. As discussed above, in the embodiment of the present invention having an 8-bit integrated circuit memory device and operating in sequential mode, the data bundle length control signal BL4 and the interleaving mode signal INTERLEAVE are set to a logic "low ", And set the sequential mode signal SEQUENTIAL to a logic" high ". If so, the logic circuit 520 controlled by the data bundle length signal BL4, the interleave signal INTERLEAVE, and the sequential mode signal SEQUENTIAL activates the second logic signal LS1 corresponding to the second output signal DS1.

If the second logic LS1 is started, the grouping unit 530 classifies the signal GS1 corresponding to the second logic signal LS1 and three signals GS2, GS3, and GS4 connected to the signal GS1 into the first group. Group, and activate these signals GS1 ~ GS4.

In the first cycle, under the control of the first control signal CSLPE0, the second to fifth pre-decoding on the corresponding signals GS1 to GS4 (belonging to the first group) are started at "high" level 1. Signal DCA012 &lt;i&gt; (i = 1-4); and do not start with a "low" level 0 corresponding to the pre-decoded signals DCA012 on these signals GS5 ~ GS7 and GS0 (belonging to the second group) &lt;I&gt; (i = 0, 5, 6, 7). Each of the second to fifth pre-decoded signals DCA012 &lt;i&gt; 0 = 1-4) corresponds to the three bits CA2, CA1, and CA0 of the row address CA, that is, 001, 010, 011, or 100. Each of the first and sixth to eighth pre-decoded signals DCA012 &lt;i&gt; (i = 0, 5, 6, 7) corresponds to three bits CA2 of the row address CA2. On CA1 and CA0, that is 000, 101, 110, or 111.

In the second period, since the first to eighth pre-decoded signals DCA012 &lt;i&gt; (i = 0-7) are inverted, starting with a high level "1" is equivalent to the first period not being started. The first and sixth to eighth pre-decoded signals DCA012 &lt;i&gt; (i = 0, 5, 6, 7). In this cycle, the signals "GS1 ~ GS4 belonging to the first group" and "signals GS5 ~ GS7 and GS0 belonging to the second group" are inverted to decode the first to eighth pre-decoded signals. DCA012 &lt;i&gt; (i = 0-7) reverses.

Referring now to FIG. 5, an exemplary operation diagram of the data position controller 430 shown in FIG. 2 will be discussed. A description will be given of a process for controlling the positions of four bits D0 to D3 of data sequentially inputted via a data pin DQ according to some specific embodiments of the present invention.

If the length of the data cluster is 8 bits, the data position controller 430 may only use the two bits CA1 and CA0 in the row address CA to control the positions of the four bits D0 to D3 of the parallel data. This data cluster is the same when the length is 4 bits.

In some embodiments of the present invention, data is input from, for example, a device external to the memory device, that is, data is written into the memory device. For example, as illustrated in FIG. 5, the sequence-parallel converter converts four sequential sequence data bits D0 ~ D3 into parallel data. The data position controller 430 controls the positions of the parallel data D0 to D3 in the four memory cell array blocks 100_i (i = 1-4). In order to input and / or output data, it includes an input and / or output (I / O) line Qi (i = 1) corresponding to each of the memory cell array blocks 100_i (i = 1-4). -3). In other words, the first to fourth I / O lines Q0 to Q3 are respectively connected to the first to fourth memory cell array regions 100_1 to 100_4.

Referring now to FIG. 6, a diagram illustrating the locations of the data for the address addition design according to a specific embodiment of the present invention will be discussed. As discussed above, the address increase design may include, for example, a sequential address increase design and / or an interleaved address increase design.

As illustrated in FIG. 6, if the two bits CA1 and CA0 of the row address CA are 00, the sequential address addition design or the interleaved address addition design is used to add these first to The fourth data D0 ~ D3 are input into the first to fourth I / O lines Q0 ~ Q3, respectively.

As further illustrated in FIG. 6, if the two bits CA1 and CA0 of the row address CA are 01, the sequential address addition design is used to input the first to fourth data D0 to D3 respectively. These second to third and first I / O lines (Q1 ~ Q2 and Q0). However, with the interleaved address increase design, the first to fourth data D0 to D3 are input to the second, first, fourth, and third I / O lines (Q1, Q0, Q3, and Q2), respectively. .

As further illustrated in FIG. 6, if the two bits CA1 and CA0 of the row address CA are 10, the sequential address addition design or the interleaved address addition design will The fourth data D0 ~ D3 are input into the third, fourth, first and second I / O lines (Q2, Q3, Q0 and Q1), respectively.

As further illustrated in FIG. 6, if the two bits CA1 and CA0 of the row address CA are 11, the sequential address increase design is used to input the first to fourth data D0 to D3 respectively. Among the fourth, first, second and third I / O lines (Q3, Q0, Q1 and Q2). However, with the interleaved address increase design, the first to fourth data D0 to D3 are input to the fourth, third, second, and first I / O lines (Q3, Q2, Q1, and Q0), respectively. .

The operation of the integrated circuit memory device with respect to the remaining four bits D4 to D7 in the parallel data is similar to the operation of the first four bits D0 to D3 in the parallel data described above with reference to FIGS. 5 and 6. , So it will not be described separately. In addition, the operation of outputting data output from the memory cell array blocks is similar to the operation of inputting data into the memory cell array blocks described above, and therefore will not be described further. It should be understood that the inductive amplifier 440 illustrated in FIG. 2 controls the position of the (output) data.

As briefly described above with reference to FIGS. 1-6, specific embodiments of the present invention provide an integrated circuit device including a double data rate (DDR) integrated circuit memory device, wherein the DDR integrated circuit memory device Assembled to support "N-2N" prefetch-data bundle length operation mode. In some embodiments of the present invention, the integrated circuit device can support the current sequential and interleaved address increase designs. The integrated circuit device according to a specific embodiment of the present invention includes a 012 pre-decoder 500, wherein the pre-decoder 500 uses the three bits CA2, CA1, and CA0 of a row address CA to output the first to eighth pre-decoded signals DCA012 &lt;I&gt; (i = 0-7), to control the row selection line used to select rows for data input and output. In the first cycle, start the four pre-decoded signals among the first to eighth pre-decoded signals DCA012 &lt;i&gt; (i = 0-7) output by the 012 pre-decoder 500 according to the starting row address; And after inverting the first to eighth pre-decoded signals (DCA012 &lt;i&gt;, i = 0-7), the remaining four pre-decoded signals are activated in the second cycle. If so, an integrated circuit memory device according to a specific embodiment of the present invention may not include a complicated circuit (such as a counter for generating a row of addresses in the integrated circuit memory device). In addition, because it may use the two bits CA1 and CA0 of the row address CA to control the order of the data input and / or output, the order can also be used when the data cluster length is 4 bits.

The typical and preferred embodiments of the present invention have been disclosed in these illustrations and patent specifications. Although special conditions are used, they are only used in a general and descriptive sense, not for limitation. The scope of the present invention is set forth in the scope of patent applications.

<p>500 012 pre-decoder / 012 decoder</p><p>100 Memory cell array</p><p>200 buffer</p><p>300 decoder</p><p>410 Serial-to-parallel converter</p><p>420 Parallel-sequence converter</p><p>430 Data position controller</p><p>440 Sense amplifier</p><p>310 Column Address Predecoder</p><p>320 Column decoder 330 Row address pre-decoder 340_i (i = 1, 2, 3, 4) Row decoder 210 Address buffer 220 Column address buffer 230 Row address buffer 240 Command buffer 250 Clock buffer 260 data buffer 270 data flash control signal buffer 510 decoding unit 520 logic circuit 530 grouping unit 540 pre-decoding signal generator 541 first switch group 542 second switch group 543 latch 100_i (i = 1 , 2, 3, 4) Memory cell array block</p>

FIG. 1 is a timing diagram illustrating an operation of a synchronous dynamic random access memory (SDRAM) according to a specific embodiment of the present invention;

2 is a block diagram illustrating an integrated circuit memory device according to a specific embodiment of the present invention;

3 is a circuit diagram illustrating a part of a row address pre-decoder shown in FIG. 2 according to a specific embodiment of the present invention;

FIG. 4 is an exemplary operation diagram of a pre-decoder shown in FIG. 3 according to a specific embodiment of the present invention; FIG.

FIG. 5 is a diagram illustrating the operation of the data position controller shown in FIG. 2 according to a specific embodiment of the present invention; and

FIG. 6 is a diagram illustrating data locations used in various address designs according to specific embodiments of the present invention.