Integration of area efficient antennas for phased array or wafer scale array antenna applications

TECHNICAL FIELD

0001The field generally relates to antenna package structures and, in particular, to antenna package structures and techniques to implement large phased array antenna systems or 3D wafer scale antenna array systems for millimeter-wave and Terahertz (sub millimeter-wave) operating frequencies.

BACKGROUND

0002In general, RF (radio frequency) systems typically utilize some type of antenna structure for wireless communication. For frequencies up to 60 GHz, an antenna structure is designed separately from a radio frequency integrated circuit (RFIC) package, and then connected to the RFIC package. In particular, with this technique, an antenna structure, whether a single antenna or an antenna array, can be connected to the RFIC package using cables with connectors or using bonding wires.

0003For millimeter-wave frequencies in a range of 60 GHz to 94 GHz, an antenna can be implemented in an antenna-in-package that includes and RFIC die, and one or more antenna structures and associated antenna feed lines, wherein the antenna structure is attached to the RFIC die. This technique eliminates the need to use a bonding wire as the antenna feed line, thereby resulting in reduced power loss and reduced antenna impedance mismatch due to the extra inductance from the bonding wire. With this design, the antenna-in-package is an RFIC package, as the antenna-in-package includes not only the antenna structure, but also all the low frequency components, such as power plane, base band signal lines, control lines, DC power supply line, etc. The antenna-in-package is attached to an application board typically through BGA balls.

0004For operating frequencies above 94 GHz, however, it is not trivial to design and manufacture antenna-in-package structures due to the lack of availability of proper antenna substrates and the limitations of currently available processing technologies that do not afford the requisite manufacturing resolutions for such high-frequency applications. Furthermore, a standard interface between the antenna package and the RFIC die (typically a flip-chip connection) produces more than 1 dB signal attenuation at 94 GHz, minimizing the advantages of antenna-in-package designs.

SUMMARY

0005In general, embodiments of the invention include package structures for integrally packaging antennas with semiconductor RFIC chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. In one embodiment, a package structure includes an RF IC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

0006Other embodiments of invention will be described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0007<figref idref="DRAWINGS">FIG. 1</figref> is a schematic side view of a wireless communications package structure according to an embodiment of the invention.

0008<figref idref="DRAWINGS">FIG. 2</figref> is a schematic side view of a wireless communications package structure according to another embodiment of the invention.

0009<figref idref="DRAWINGS">FIG. 3A</figref> is a schematic side view of a wireless communications package structure according to yet another embodiment of the invention.

0010<figref idref="DRAWINGS">FIG. 3B</figref> is a schematic top view of the wireless communications package structure of <figref idref="DRAWINGS">FIG. 3A</figref>, according to an embodiment of the invention.

0011<figref idref="DRAWINGS">FIG. 4</figref> is a schematic side view of a wireless communications package structure according to another embodiment of the invention.

DETAILED DESCRIPTION

0012Embodiments of the invention will now be discussed in further detail with regard to structures and methods for integrally packaging antenna structures with semiconductor RFIC chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. The exemplary antenna package structures and techniques described herein are compatible with wafer-level 3D integration to enable the implementation of large phased array antenna systems or 3D wafer scale array antenna systems for millimeter-wave or terahertz operating frequencies.

0013It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are not drawn to scale, and that one or more layers, structures, and regions of a type commonly used in integrated antenna and chip packages may not be explicitly shown in a given drawing. This does not imply that the layers, structures and regions not explicitly shown are omitted from the actual integrated chip packages. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings.

0014<figref idref="DRAWINGS">FIG. 1</figref> is a schematic side view of a wireless communications package structure according to an embodiment of the invention. In particular, <figref idref="DRAWINGS">FIG. 1</figref> schematically illustrates a wireless communications device <b>100</b> comprising an antenna package <b>110</b>, a RFIC chip <b>120</b>, and an application board <b>130</b>. The antenna package <b>110</b> comprises a glass substrate <b>112</b>, a planar antenna <b>114</b> formed on one side of the glass substrate <b>112</b>, and a ground plane <b>116</b> and contact pad <b>116</b>A formed on an opposite side of the glass substrate <b>112</b>. An antenna feed line <b>118</b> is formed through the glass substrate <b>112</b> providing an electrical connection between the contact pad <b>116</b>A and a feed point of the planar antenna <b>114</b>. The contact pad <b>116</b>A is formed to be electrically isolated from the ground plane <b>116</b>. The antenna package <b>110</b> is bonded to the RFIC chip <b>120</b> using a layer of adhesive material <b>140</b>. In one embodiment, the layer of adhesive material <b>140</b> has a thickness in a range of about 1 μm to about 20 μm.

0015In general, the RFIC chip <b>120</b> comprises integrated circuitry <b>122</b>, a BEOL (back end of line) structure <b>124</b>, an insulating layer <b>126</b>, and a plurality of metallic joint structures <b>128</b> and <b>129</b> (or micro vias). In one embodiment of the invention, the RFIC chip <b>120</b> is formed using a bulk SOI (silicon on insulator) substrate having a buried oxide (BOX) layer disposed between two layers of silicon wherein one layer of silicon (front side surface) comprises a thin silicon layer in which active devices are formed, and wherein the other layer of silicon (back side surface or substrate) is a relatively thick silicon layer that can be utilized for various purposes as is known in the art.

0016In the embodiment of <figref idref="DRAWINGS">FIG. 1</figref>, the integrated circuitry <b>122</b> comprises a plurality of active circuit devices and other electronic components that are formed in the front side (active surface) of the RFIC chip <b>120</b>. In particular, for an SOI substrate embodiment, the integrated circuitry <b>122</b> is formed in the thin silicon layer on the front side of the SOI substrate. The integrated circuitry <b>120</b> includes active devices and other components that are configured to implement, e.g., a receiver, a transmitter, or a transceiver circuit, and other active or passive circuit elements that are commonly used to implement a wireless communications system, an imager, or millimeter-wave/terahertz sensors.

0017Furthermore, for an SOI substrate embodiment, the insulating layer <b>126</b> in <figref idref="DRAWINGS">FIG. 1</figref> corresponds to the BOX layer of the SOI substrate. The insulating layer <b>126</b> may be formed of a silicon oxide material, such as SiO₂(dielectric constant of 3.9) or other types of insulating or dielectric materials that are suitable for the given application. In one embodiment, the insulating layer <b>126</b> is formed of SiO₂with a thickness of about 10 nm to about 4 μm. In the illustrative embodiment of <figref idref="DRAWINGS">FIG. 1</figref>, it is assumed that the backside silicon layer of the SOI substrate is completely removed (via a grinding process and/or an etching/thinning process) before bonding the antenna package <b>110</b> to the backside of the RFIC chip <b>120</b> via the layer of adhesive material <b>140</b>.

0018The BEOL structure <b>124</b> is formed on the front side of the RFIC chip <b>120</b> to provide electrical connections between components of the integrated circuitry <b>122</b>. In general, the BEOL structure <b>124</b> comprises multiple layers of metallization patterns <b>124</b>A and insulating (dielectric) material <b>124</b>B, as well as a plurality of bonding pads <b>124</b>C. In one embodiment, the BEOL structure <b>124</b> has a total thickness of about 5 μm to about 20 μm. The BEOL structure <b>124</b> can be built using well known semiconductor processing technologies and materials that are suitable for the given application.

0019The metallization patterns <b>124</b>A comprise inter-level contact pads, interconnect wires, and vias, which are used to form electrical connections between components of the integrated circuitry <b>122</b>. The insulating material <b>124</b>B may be formed of layers of silicon oxide material, or other suitable dielectric materials with a dielectric constant in a range of about 2 to about 3.9, for example. The metallic joint structures <b>128</b> and <b>129</b> are metallic elements (micro via elements) that are formed (separate from, and subsequent to, the BEOL processing) to provide electrical connections between components of the antenna package <b>110</b> and metallization patterns <b>124</b>A of the BEOL structure <b>124</b>.

0020Furthermore, the bonding pads <b>124</b>C of the BEOL structure <b>124</b> include, for example, ground pads, DC power supply pads, I/O (input/output) signal pads, control signal pads, etc. The application board <b>130</b> comprises a plurality of bonding pads <b>132</b> that are formed in alignment with corresponding ones of the bonding pads <b>124</b>C of the RFIC chip <b>120</b>. In the embodiment of <figref idref="DRAWINGS">FIG. 1</figref>, the RFIC chip <b>120</b> is flip-chip mounted to the application board <b>130</b> using an array <b>150</b> of controlled collapse chip connections (C4), or other known techniques. It is to be understood that some of the C4 connections may be non-electrical connections that merely serve to physically bond the RFIC chip <b>120</b> to the application board <b>130</b>, while other C4 connections may serve as bonding connections, as well as electrical interface connections between the application board <b>130</b> and the RFIC chip <b>120</b>.

0021For instance, in the embodiment of <figref idref="DRAWINGS">FIG. 1</figref>, a C4 connection <b>152</b> is utilized in conjunction with the metallic joint <b>128</b>, a portion of the BEOL metallization pattern, and the contact pads <b>124</b>A and <b>124</b>C, to form a ground connection between the ground plane <b>116</b> of the antenna package <b>110</b> and a ground contact <b>132</b> on the application board <b>130</b>. On the other hand, a C4 connection <b>154</b> (and others) may simply be used to flip-chip bond the RFIC chip <b>120</b> to the application board <b>130</b>, such that no wiring is connected to the associated bonding pads <b>124</b>C and <b>132</b> and, thus, the C4 connection does not serve as an electrical connection. Moreover, other C4 connections <b>150</b> (not specifically shown in <figref idref="DRAWINGS">FIG. 1</figref>) provide supply voltage connections, I/O connections, control signal connections, etc., between the RFIC chip <b>120</b> and associated contact pads <b>132</b> on the application board <b>130</b>.

0022In other embodiments of the invention, the RFIC chip <b>120</b> can be electrically connected to the application board <b>130</b> using wire bonds, as is readily understood by one of ordinary skill in the art. For example, in one embodiment, the RFIC chip <b>120</b> can be designed with a larger footprint (e.g., larger width) than the footprint of the antenna package <b>110</b>, such that the contact pads <b>124</b>C of the BEOL structure <b>124</b> could be formed on the peripheral/perimeter region of the backside surface of the RFIC chip <b>120</b>, which is not covered by the antenna package <b>110</b>. In this embodiment, the front side of the RFIC chip <b>120</b> could be bonded to the application board <b>130</b> using an adhesive material or some other standard bonding techniques, and wire bonds would be formed to make electrical connections between the bonding pads <b>132</b> on the application board and the bonding pads <b>124</b>C that are exposed on the perimeter region of the backside surface of the RFIC chip <b>120</b>. In other embodiments, an electrical interface can be implemented using a combination of C4 connections and wire bonds, as is readily understood by one of ordinary skill in the art.

0023As is readily understood by one of ordinary skill in the art, the application board <b>130</b> can be formed of one or more substrates comprising one or more levels of metallization patterns and via structures to route the I/O signals, control signals, and power supply signals to and from the RFIC chip <b>120</b> as needed. The application board <b>130</b> can be formed of standard FR4 material with copper metallization, or other suitable materials commonly used to construct a standard PCB (printed circuit board), for example.

0024In the embodiment of <figref idref="DRAWINGS">FIG. 1</figref>, the antenna package <b>110</b> is a structure that can be separately fabricated and then bonded to the RFIC chip <b>120</b>. The antenna package <b>110</b> can be fabricated from a metallized glass substrate, wherein the planar antenna <b>114</b> and ground plane <b>116</b> and contact pad <b>116</b>A are formed by patterning metal layers on opposing side of the glass substrate <b>112</b>. The metallic patterns can be formed of copper or gold, or other types of metallic material suitable for the given application. The glass substrate <b>112</b> can be formed of a glass material that is suitable for the given application. In one embodiment, the glass substrate <b>112</b> is formed of a glass material having a dielectric constant ε of about 4.0. The antenna feed line <b>118</b> can be a TGV (through-glass-via) that is formed by etching or drilling a hole through the glass substrate <b>112</b>, and then filling the through hole, or electroplating the walls of the through hole, with a metallic material such as copper.

0025The planar antenna <b>114</b> can be implemented using any suitable planar antenna structure that provides broadside radiation R as shown in <figref idref="DRAWINGS">FIG. 1</figref>. In one embodiment of the invention, the planar antenna <b>114</b> comprises a planar patch radiating element having a resonant length in a range from about one-quarter wavelength to about one-half wavelength. The contact point of the antenna feed line <b>118</b> to the planar antenna <b>114</b> is selected so that the antenna impedance is matched to 50 Ohms, which is standard for most RF transceivers.

0026Depending on the type of planar antenna used, the ground plane <b>116</b> operates as an antenna ground plane (e.g., for microstrip-type antenna structures) as well as a reflector element to reflect radiation away from the RFIC chip <b>120</b>. In other embodiments in which the planar antenna <b>114</b> can operate as a radiating element without the need for an antenna ground plane, the ground plane <b>116</b> serves to reflect radiation away from the RFIC chip <b>120</b>.

0027The operating frequency and other performance characteristics of the antenna package <b>110</b> will vary based on, e.g., the dimensions of the planar antenna <b>114</b> and the glass substrate <b>112</b>, and the dielectric constant of the glass material used to form the glass substrate <b>112</b>. For example, for a planar patch antenna, a length of the patch antenna will determine an operating frequency and other performance characteristics of the antenna. Typically, the length of a planar patch antenna is in a range of about ¼-wavelength to about ½-wavelength. For a phased array antenna application (e.g., <figref idref="DRAWINGS">FIG. 2</figref>) with multiple patch antennas for example, the distance (pitch) between each patch antenna in the phased array is equal to about λ/2.

0028Moreover, the distance between the planar antenna <b>114</b> and the ground plane <b>116</b> (i.e., the thickness of the glass substrate <b>112</b>) can be varied to trade-off antenna bandwidth and efficiency. The antenna bandwidth can be improved by increasing the distance between the planar patch antenna <b>114</b> and ground plane <b>116</b>, at the cost of decreased antenna efficiency. In one embodiment, the glass substrate <b>112</b> can have a thickness in a range from about 50 μm to about 750 μm, which provides a 12% target bandwidth an over an operating frequency range from about 10 GHz to about 150 GHz.

0029With regard to the antenna feed line <b>118</b>, the minimum width of the TGV is limited by the aspect ratio that can be achieved with the etching or drilling process used to form a through hole in the glass substrate <b>112</b>. Typically an aspect ratio of 2 or 10 to 1 can be achieved. Therefore, for a glass substrate with a thickness of 50 μm, a minimum width of 25 μm to 5 μm can be achieved.

0030With regard to the thickness of the metallization, the metal thickness can be derived by computing the skin depth given by:

0031<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><mrow><mi>δ</mi><mo>=</mo><msqrt><mfrac><mrow><mn>2</mn><mo>⁢</mo><mi>ρ</mi></mrow><mrow><mn>2</mn><mo>⁢</mo><mi>π</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mi>f</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mi>μ</mi></mrow></mfrac></msqrt></mrow><mo>,</mo></mrow></math></maths><img file="US10103450B2_D0001.tif" /><br /> where ρ is the metal conductivity and μ is the permittivity. For copper at 60 GHz, the skin depth is 0.27 μm. To minimize ohmic losses, the metallization should have a thickness of at least 5 skin depths. Therefore, for a 60 GHz operating frequency, the thickness of the copper metallization should be at least 1.35 μm.

0032In one embodiment of the invention, the wireless communications device <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> is fabricated as follows. As noted above, the antenna package <b>110</b> and RFIC chip <b>120</b> are fabricated separately, and then bonded together using adhesive material. The RFIC chip <b>120</b> is fabricated using standard CMOS or other semiconductor processing technologies. For example, starting with an SOI substrate, FEOL (front end of line) processing techniques are utilized to form the integrated circuitry <b>122</b> on the front side silicon layer of the SOI substrate, followed by BEOL processing techniques to form the BEOL structure <b>124</b>.

0033The SOI substrate is then bonded face down to a handler substrate (e.g., glass carrier) using a polyimide adhesive, for example. Then, a backside etching or grinding process is performed to remove the backside bulk silicon layer from the SOI substrate. With this process, the bulk silicon layer is completely removed down to the BOX layer (e.g., the insulating layer <b>126</b> in <figref idref="DRAWINGS">FIG. 1</figref>). Following the backside etch, a process is performed to form the metallic joints <b>128</b> and <b>129</b> with the etched SOI substrate still attached to the handler substrate.

0034In particular, in one embodiment of the invention, the metallic joints <b>128</b> and <b>129</b> are formed as follows. Initially, a layer of photoresist material is deposited on the BOX layer and patterned to form openings in the photoresist in regions of the backside surface where via holes are to be etched and subsequently filled with metallic material (e.g., copper) to form the metallic joints <b>128</b>, <b>129</b>. The patterned photoresist layer is then used as a mask to perform an anisotropic etch process to etch the BOX layer (insulating layer <b>126</b>) and the BEOL insulating material <b>124</b>B down to contact pads that are formed as part of the BEOL metallization <b>124</b>A.

0035Following the etch process, the photoresist pattern is removed using standard techniques, and a thin conformal seed layer is deposited to line the etched via holes. The thin conformal seed layer can be a thin copper layer. Following deposition of the seed layer, a photoresist material is deposited and patterned to form a second photoresist pattern that exposes the via holes lined with the seed layer. A copper fill process is then performed to fill the exposed via holes with copper material using the seed layer as a nucleating layer for the deposition process. In one embodiment, the copper fill process can be implemented using an electroplating process wherein the seed layer serves as an anode/cathode for the electroplating process. With this process, the second photoresist pattern covers the backside region of the SOT substrate so that copper is only deposited in the via holes exposed by the second photoresist pattern.

0036Following the copper fill process, the second photoresist pattern is removed, resulting in the completed RFIC chip <b>120</b> with exposed portions of the metallic joints <b>128</b> and <b>129</b> on the backside of the RFIC chip <b>120</b>. As this stage of fabrication, the front side of the RFIC chip <b>120</b> remains attached to the handler substrate. Then, the separately formed antenna package <b>110</b> is bonded to the etched backside of the RFIC chip <b>120</b>, wherein copper bonding process is performed to bond the exposed surfaces of the metallic joints <b>128</b>, <b>129</b> to desired contact points of the metallization (e.g., ground plane <b>116</b>, contact pad <b>116</b>A, <figref idref="DRAWINGS">FIG. 1</figref>) on the bottom surface of the glass substrate <b>112</b>.

0037Furthermore, as part of this bonding step, a layer of adhesive material (e.g., adhesive layer <b>140</b>, <figref idref="DRAWINGS">FIG. 1</figref>) is formed on the bottom surface of the glass substrate <b>112</b>, which further serves to bond the antenna package <b>110</b> to the backside of the RFIC chip <b>120</b>. In one embodiment, the layer of adhesive material includes a polyimide layer with a thickness of 2-3 μm, for example.

0038After the antenna package <b>110</b> is bonded to the backside of the RFIC chip <b>120</b>, the handler substrate is removed from the front side of the RFIC chip <b>120</b> using a standard release process. For example, a laser release process can be performed by irradiating the adhesive layer (which bonds the handler substrate to the RFIC chip <b>120</b>) through the handler (glass) substrate, to thereby laser ablate the adhesive layer and release the handler substrate from the front side of the RFIC chip <b>120</b>. A cleaning process is then performed to remove any remaining residue from the front side of the RFIC chip <b>120</b>. Thereafter, the RFIC chip <b>120</b> (with the antenna package <b>110</b> mounted on the backside thereof) is bonded to the application board <b>130</b> using, e.g., C4 connections, as discussed above. Again, in other embodiments as discussed above, wire bond connections can be utilized (either alone or in combination with C4 connections) to provide electrical connections between the RFIC chip <b>120</b> and the application board <b>130</b>.

0039The embodiment of <figref idref="DRAWINGS">FIG. 1</figref> illustrates an antenna package <b>110</b> with a single glass substrate <b>112</b> and one antenna structure for an SOI implementation. In other embodiments of the invention, antenna structures that utilize multiple stacked glass substrates can be implemented as well. For example, such antenna structures include stacked patch antennas, L-probe fed patch antennas, grid antennas, dipole antennas, etc. By way of specific example, in a stacked patch antenna implementation, an antenna package comprises a first glass substrate and a second glass substrate bonded together to form stacked structure, wherein the first glass substrate comprises a first patch radiator element, and wherein the second glass substrate comprises a second patch radiator element. The second patch radiator element can be fed by an antenna feed line (such as shown in <figref idref="DRAWINGS">FIG. 1</figref>), whereas the first patch radiator element (disposed over the second patch radiator element) can be capacitively feed by the second patch radiator element.

0040Moreover, in other embodiments of the invention, an antenna package can be fabricated with multiple antenna radiating elements to provide a phased array antenna system. For example, <figref idref="DRAWINGS">FIG. 2</figref> is a schematic side view of a wireless communications package structure according to another embodiment of the invention, which provides a phased-array antenna structure for an SOI implementation. In particular, <figref idref="DRAWINGS">FIG. 2</figref> schematically illustrates a wireless communications device <b>200</b> comprising multiple package structures <b>202</b>A, <b>202</b>B, and <b>202</b>C bonded to an application board <b>130</b> using an array of C4 connections <b>150</b>.

0041In the embodiment of <figref idref="DRAWINGS">FIG. 2</figref>, each package structure <b>202</b>A, <b>202</b>B, and <b>202</b>C comprises a respective antenna package <b>110</b>A, <b>110</b>B, and <b>110</b>C, bonded to a backside of a respective RFIC chip <b>120</b>A, <b>120</b>B and <b>120</b>C. Each package structure <b>202</b>A, <b>202</b>B, and <b>202</b>C is conceptually similar in design to the package structure (antenna package <b>110</b> and RFIC chip <b>120</b>) discussed above with reference to <figref idref="DRAWINGS">FIG. 1</figref>. However, in the embodiment of <figref idref="DRAWINGS">FIG. 2</figref>, each package structure <b>202</b>A, <b>202</b>B, and <b>202</b>C is a separate package that is bonded to the application board <b>130</b> so as to maintain antenna elements <b>114</b>-<b>1</b>, <b>114</b>-<b>2</b>, <b>114</b>-<b>3</b> and <b>114</b>-<b>4</b> at half-wavelength spacing. The embodiment of <figref idref="DRAWINGS">FIG. 2</figref> is useful for a large antenna array SOI implementation by allowing the tiling of separate chips with half wavelength spacing. While some package structures (e.g., <b>202</b>A and <b>202</b>C) are formed with one antenna element (e.g., <b>114</b>-<b>1</b> and <b>114</b>-<b>4</b>), other package structures (e.g., <b>202</b>B) are formed with multiple antenna elements (e.g., <b>114</b>-<b>2</b> and <b>114</b>-<b>3</b>). Each package structure <b>202</b>A, <b>202</b>B and <b>202</b>C can be fabricated using the techniques discussed above with reference to the exemplary embodiment of <figref idref="DRAWINGS">FIG. 1</figref>.

0042<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> schematically illustrate a communications package structure according to yet another embodiment of the invention. In particular, <figref idref="DRAWINGS">FIG. 3B</figref> is a schematic top view of a wireless communications device <b>300</b>, while <figref idref="DRAWINGS">FIG. 3A</figref> is a schematic side view of the wireless communications device <b>300</b> taken along line <b>3</b>A-<b>3</b>A in <figref idref="DRAWINGS">FIG. 3B</figref>. The embodiment of the wireless communications device <b>300</b> in <figref idref="DRAWINGS">FIGS. 3A</figref>/<b>3</b>B is similar to the embodiment of the wireless communications device <b>200</b> of <figref idref="DRAWINGS">FIG. 2</figref>, except that the embodiment of <figref idref="DRAWINGS">FIGS. 3A</figref>/<b>3</b>B provides a 3D SOI wafer scale implementation, at millimeter-wave frequencies, for a very large phased-array antenna application.

0043In particular, as shown in <figref idref="DRAWINGS">FIGS. 3A</figref>/<b>3</b>B, an antenna package <b>310</b> comprises an array of planar antennas (e.g., antennas <b>114</b>-<b>1</b>, <b>114</b>-<b>2</b>, <b>114</b>-<b>3</b>, <b>114</b>-<b>4</b> . . . , <b>114</b>-<i>n</i>) that are formed on one side of a single glass wafer <b>312</b>. The wafer scale antenna package <b>310</b> is bonded to a backside surface of an SOI wafer <b>320</b> comprising active RFIC integrated circuitry and BEOL structures, as needed, to operate the array of antennas <b>114</b>-<b>1</b>, <b>114</b>-<b>2</b>, <b>114</b>-<b>3</b>, <b>114</b>-<b>4</b> . . . , <b>114</b>-<i>n </i>as a phased-array antenna system, using techniques known to those of ordinary skill in the art.

0044<figref idref="DRAWINGS">FIG. 4</figref> is a schematic side view of a wireless communications package structure according to another embodiment of the invention. In particular, <figref idref="DRAWINGS">FIG. 4</figref> schematically illustrates a wireless communications device <b>400</b> which is similar to the wireless communications device <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>, except that in the exemplary embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the antenna package <b>110</b> is bonded to a front side surface of an RFIC chip <b>420</b>.

0045In particular, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, the RFIC chip <b>420</b> comprises integrated circuitry <b>422</b>, a BEOL structure <b>424</b>, and a bulk silicon layer <b>426</b>. Although not specifically shown, in an SOI embodiment, the silicon substrate <b>426</b> may comprise a BOX layer, wherein the integrated circuitry <b>422</b> is formed in a thin layer of silicon on top of the BOX layer. The BEOL structure <b>424</b>, which is formed on the front side of the RFIC chip <b>420</b>, comprises multiple layers of metallization patterns <b>424</b>A embedded in insulating (dielectric) material <b>424</b>B, to provide electrical connections between components of the integrated circuitry <b>422</b>.

0046In the embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the antenna package <b>110</b> is bonded to the front side of the RFIC chip <b>420</b> using the adhesive layer <b>140</b>, whereas the backside of the RFIC chip <b>420</b> is bonded to the application board <b>130</b> using an array of C4 connections <b>150</b>. As further depicted in <figref idref="DRAWINGS">FIG. 4</figref>, the bulk silicon layer <b>426</b> comprises a plurality of TSVs (through-silicon-vias) <b>428</b> to provide electrical connections between certain points of the metallization pattern <b>424</b>A and bonding pads <b>430</b> formed on bottom surface of the bulk silicon layer <b>426</b> (i.e., on the backside of the RFIC chip <b>420</b>). The through-silicon-vias <b>428</b> can be fabricated using well known techniques. In other embodiments of the invention, wire bonds can be utilized either alone, or in combination with C4 connections, to provide electrical connections between the RFIC chip <b>420</b> and the application board <b>130</b>.

0047In another embodiment of the invention, similar to the embodiments discussed above with reference to <figref idref="DRAWINGS">FIGS. 2 and 3A</figref>/<b>3</b>B, a large phased array antenna system or wafer scale antenna array can be designed based on the package structure of <figref idref="DRAWINGS">FIG. 4</figref>. In such embodiments, the RFIC chips <b>120</b>A, <b>120</b>B and <b>120</b>C (<figref idref="DRAWINGS">FIG. 2</figref>) and RFIC chip <b>320</b> (<figref idref="DRAWINGS">FIGS. 3A</figref>/<b>3</b>B) would be replaced with an RFIC chip having a structure similar to that depicted in <figref idref="DRAWINGS">FIG. 4</figref>, wherein multiple RFIC chips or an RFIC wafer would be backside mounted to the application board <b>130</b>, with antenna packages or an antenna wafer bonded to the front side of the RFIC chip(s).

0048Those of ordinary skill in the art will readily appreciate the various advantages associated with integrated chip/antenna package structures according to embodiments of the invention. For instance, the use of the low-loss glass substrates to form antenna package structures enables the realization of high-efficient antenna designs that are compatible for use with high-resistivity bulk, SOI, or SOG (silicon on glass) Si technologies, while using standard bonding techniques to form the package structures. These standard processing techniques enable antennas to be integrally packaged with IC chips such as transceiver chips, thereby providing compact designs with very low loss between the transceiver and the antenna. The use of semiconductor fabrication technologies (as compared to PCB technology) allow the design of higher-precision metallization geometries compatible with millimeter wave and terahertz operating frequencies.

0049Moreover, various types of antenna designs can be implemented as discussed above for single antenna or phased-array antenna applications. The embodiments discussed herein are compatible with wafer scale level fabrication and integration, thereby enabling ease of manufacture of large phase array antenna structures. Moreover, multiple wafer level integration can be tiled (e.g., <figref idref="DRAWINGS">FIG. 2</figref>) to readily increase a number of antenna for use in phase-array antenna applications using a multitude of different chips integrated on a given carrier or application board to implement a phase-array antenna.

0050It is to be further understood that the antenna package structures illustrated herein can extended or varied depending on the application, e.g., antenna structure. <b>110</b> routing requirements, power and ground plane requirements, etc. Those of ordinary skill in the art readily understand that the antenna performance parameters such as antenna radiation efficiency and bandwidth and operating resonant frequency will vary depending on the dielectric constant, loss tangent, and thickness of the dielectric/insulating materials that form the substrate layers. Moreover, the size and structure of the various radiating elements of the antennas shown in drawings will determine the resonant frequency of the antenna, as is well understood to those of ordinary skill in the art.

0051Although embodiments have been described herein with reference to the accompanying drawings for purposes of illustration, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected herein by one skilled in the art without departing from the scope of the invention.