Pulse signal output circuit, shift register, semiconductor device, display module and electric device

Pulse signal output circuit, shift register, semiconductor device, display module and electronic device

Pulse signal output circuit, shift register, semiconductor device, display module and electric device

The disclosed invention relates to a pulse signal output circuit and a shift register.

Transistors formed on a flat plate such as a glass substrate and typically used in liquid crystal display devices generally include semiconductor materials such as amorphous silicon or polycrystalline silicon. Although transistors including amorphous silicon have low field-effect mobility, they can be formed on larger glass substrates. In contrast, although transistors including polysilicon have high field-effect mobility, they require crystallization procedures such as laser annealing, and are not always suitable for larger glass substrates.

On the other hand, transistors including oxide semiconductors as semiconductor materials have attracted attention. For example, Patent Documents 1 and 2 disclose a technique by which zinc oxide or In-Ga-Zn-O-based oxide semiconductor is used as a semiconductor material to form a transistor and be used as a switching element of an image display device.

A transistor including an oxide semiconductor in the channel region has higher field-effect mobility than a transistor including amorphous silicon. In addition, it can be 300 °C or more The oxide semiconductor film is formed by sputtering or the like at a low temperature, and its manufacturing process is simpler than that of a transistor including polysilicon.

These transistors including oxide semiconductors are expected to be used as switching elements included in pixel portions and driving circuits of display devices such as liquid crystal displays, electroluminescent displays, and electronic paper. For example, Non-Patent Document 1 discloses a technique whereby the pixel portion and driving circuit of the display device include a transistor including an oxide semiconductor.

Please note that all transistors including oxide semiconductors are n-channel transistors. Therefore, if the driving circuit includes a transistor including an oxide semiconductor, the driving circuit only includes an n-channel transistor.

references

Patent Documents

[Patent Document 1] Japanese Published Patent Application No. 2007-123861

[Patent Document 2] Japanese Published Patent Application No. 2007-096055

Non-patent literature

[Non-Patent Document 1] T. Osada et al., "Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT" ", Proc. SID '09 Digest, 2009, pages 184-187.

The driving circuit used in the display device and the like includes, for example, a shift register having a pulse signal output circuit. If the shift register includes transistors with the same conductivity type, the shift register may have problems such as unstable operation question.

In view of the above-mentioned problems, an object of an embodiment of the present invention is to provide a pulse signal output circuit that can operate stably, and a shift register including the pulse signal output circuit.

An embodiment of the present invention is a pulse signal output circuit, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. Transistor, Ninth Transistor, and Tenth Transistor. The first terminal of the first transistor, the first terminal of the second transistor, and the first output terminal are electrically connected to each other. The first terminal of the third transistor, the first terminal of the fourth transistor, and the second output terminal are electrically connected to each other. The first terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor are electrically connected to each other. The gate terminal of the first transistor, the gate terminal of the third transistor, and the second terminal of the seventh transistor are electrically connected to each other. The gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the first terminal of the ninth transistor are electrically connected to each other. The second terminal of the eighth transistor and the first terminal of the tenth transistor are electrically connected to each other. The ratio W/L of the channel width W of the first transistor to the channel length L and the ratio W/L of the channel width W of the third transistor to the channel length L are larger than the channel width W of the sixth transistor relative to the channel. The ratio of length L is W/L. The ratio W/L of the channel width W to the channel length L of the fifth transistor is greater than the ratio W/L of the channel width W to the channel length L of the sixth transistor. The ratio W/L of the channel width W of the fifth transistor to the channel length L is equal to the channel width W of the seventh transistor. The ratio W/L to the channel length L. The ratio W/L of the channel width W to the channel length L of the third transistor is greater than the ratio W/L of the channel width W to the channel length L of the fourth transistor.

In the above-mentioned pulse signal output circuit, sometimes the first clock signal is input to the second terminal of the first transistor and the second terminal of the third transistor; the second clock signal is input to the gate terminal of the eighth transistor; The three-clock signal is input to the gate terminal of the tenth transistor; the first potential is supplied to the second terminal of the second transistor, the second terminal of the fourth transistor, the second terminal of the sixth transistor, and the ninth transistor The second terminal of the crystal; the second potential higher than the first potential is supplied to the second terminal of the fifth transistor, the gate terminal of the seventh transistor, and the second terminal of the tenth transistor; the first pulse signal input The gate terminal of the fifth transistor and the gate terminal of the ninth transistor; and the second pulse signal is output from the first output terminal or the second output terminal.

In addition, capacitors are sometimes arranged, which are electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, the first terminal of the eighth transistor, and the ninth transistor. The first terminal of the transistor.

In the above-mentioned pulse signal output circuit, the eleventh transistor is sometimes configured; the first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, the gate terminal of the fourth transistor, and the sixth transistor. The gate terminal of the crystal, the first terminal of the eighth transistor, and the first terminal of the ninth transistor; the second terminal of the eleventh transistor is electrically connected to the second terminal and the ninth transistor of the eighth transistor The first terminal and the capacitor; and the channel width W of the eighth transistor and the channel width W of the tenth transistor are each smaller than the channel width W of the eleventh transistor.

In the above-mentioned pulse signal output circuit, sometimes the second potential is supplied to the second terminal of the eleventh transistor; and the third pulse signal is input to the gate terminal of the eleventh transistor.

The shift register may include a plurality of the above-mentioned pulse signal output circuits. Specifically, sometimes the n-stage shift register includes two pulse signal output circuits that are not equipped with an eleventh transistor, and n (n: natural number) pulse signal output circuits that are each equipped with an eleventh transistor; and The channel width W of the eighth transistor in the pulse signal output circuit without the eleventh transistor is greater than the channel width W of the eighth transistor in the pulse signal output circuit with the eleventh transistor, or the eleventh transistor is not configured The channel width W of the tenth transistor in the pulse signal output circuit of the crystal is greater than the channel width W of the tenth transistor in the pulse signal output circuit of the eleventh transistor.

The oxide semiconductor is preferably used for any transistor included in the pulse signal output circuit or the shift register. The shift register may include a complex pulse signal output circuit.

Please note that in the above-mentioned pulse signal output circuit, sometimes the transistor includes an oxide semiconductor; however, the disclosed invention is not limited to this. A material having an off-state current characteristic equivalent to that of an oxide semiconductor can be used, for example, a wide gap material such as silicon carbide (specifically, for example, a semiconductor material with an energy gap Eg greater than 3 eV).

Please note that in this manual, words such as "above" or "below" do not necessarily mean that a component is placed "directly above" or "directly below" another component. For example, the expression "gate electrode on the gate insulating layer" does not exclude the fact that another component is placed between the gate insulating layer and the gate electrode.

In addition, in this manual, etc., terms such as "electrode" and "wiring" do not limit the function of the component. For example, "electrodes" can be used as part of "wiring", and "wiring" can be used as part of "electrodes". Terms such as "electrode" and "wiring" can also mean a combination of plural "electrodes" and "wiring", for example.

When, for example, a transistor of opposite polarity is used or the direction of current flow changes during circuit operation, the functions of "source" and "drain" can be interchanged. Therefore, in this manual, the terms "source" and "drain" are interchangeable.

Please note that in this specification and the like, the term "electrical connection" includes the condition that components are connected to each other via a target having any electrical function. Here, there is no particular limitation on the target having any electrical function, as long as the electrical signal can be transmitted and received between the components connected to each other via the target.

Examples of "objects with any electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and elements with various functions, in addition to electrodes and wiring.

A pulse signal output circuit that can operate stably, and a shift register including the pulse signal output circuit can be provided.

<p>11, 12, 13, 14 signal line</p><p>15Wiring</p><p>21, 22, 23, 24, 25Input terminal</p><p>26, 27Output terminal</p><p>31, 32Power cord</p><p>Period 51, 52, 53, 54, 55, 56</p><p>101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 410, 420, 430, 440, 510transistor</p><p>200Pulse signal generating circuit</p><p>201, 205First input signal generating circuit</p><p>202, 203, 206Second input signal generating circuit</p><p>204Virtual pulse signal generating circuit</p><p>400, 505, 4001, 4006Substrate</p><p>401, 511Gate electrode layer</p><p>402,507Gate insulation layer</p><p>403Oxide semiconductor layer</p><p>405a, 515asource electrode layer</p><p>405b, 515bDrain electrode layer</p><p>407, 427, 437, 516Insulation layer</p><p>409,506Protective insulation layer</p><p>436a, 436bwiring layer</p><p>530Oxide semiconductor film</p><p>531Oxide semiconductor layer</p><p>2700E-Book Reader</p><p>2701, 2703, 2800, 2801, 3002, 9601Shell</p><p>2705, 2707, 3003, 3023, 3055, 3057, 9603Display</p><p>2711Hinge</p><p>2721Power switch</p><p>2723Operation keys</p><p>2725, 2803, 2805Speaker</p><p>2802Display Panel</p><p>2804Microphone</p><p>2806Pointing device</p><p>2807Camera lens</p><p>2808External connection terminal</p><p>2810Solar Cell</p><p>2811External memory slot</p><p>3001, 3021, 3051Main body</p><p>3004Keyboard</p><p>3022Touch Pen</p><p>3024Operation button</p><p>3025External interface</p><p>3053Eyepiece</p><p>3054Operation switch</p><p>3056Battery</p><p>4002Pixel</p><p>4003Signal line drive circuit</p><p>4004Scan line drive circuit</p><p>4005Sealant</p><p>4018, 4018a, 4018bFlexible Printed Circuit (FPC)</p><p>9600TV</p><p>9605Support</p>

Figures 1A to 1C show configuration examples of the pulse signal output circuit and the shift register.

Figure 2 is a timing diagram of the shift register.

Figures 3A to 3C show the operation of the pulse signal output circuit.

Figures 4A to 4C show the operation of the pulse signal output circuit.

Figures 5A to 5C show configuration examples of the pulse signal output circuit and the shift register.

Figure 6 is a timing diagram of the shift register.

Figures 7A to 7C show the operation of the pulse signal output circuit.

Figures 8A and 8B show the operation of the pulse signal output circuit.

Figures 9A to 9C show configuration examples of the pulse signal output circuit and the shift register.

10A to 10D each show an example of the structure of a transistor.

11A to 11E show examples of manufacturing methods of transistors.

12A to 12C each show a mode of the semiconductor device.

13A to 13F each show electronic devices.

Figure 14 is a timing diagram of the shift register.

Hereinafter, examples of embodiments of the present invention will be described with reference to the drawings. Please note that the present invention is not limited to the following description. Those familiar with the art will easily understand that the modes and details of the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

Please note that the position, size, range, etc. of each component depicted in the drawings, etc. are sometimes not represented correctly for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, scope, etc. disclosed in the drawings.

Please note that in this manual, etc., use such as "First", "No. The ordinal number of "two" and "third" to avoid confusion between components, rather than limiting the number.

[Example 1]

In this embodiment, configuration examples of the pulse signal output circuit and the shift register including the pulse signal output circuit will be described with reference to FIGS. 1A to 1C, FIGS. 2, 3A to 3C, and FIGS. 4A to 4C.

&lt;circuit configuration&gt;

First, a configuration example of the pulse signal output circuit and the shift register including the pulse signal output circuit will be described with reference to FIGS. 1A to 1C.

The shift register described in this embodiment includes first to nth pulse signal output circuits 10_₁To 10__n(n is a natural number greater than or equal to 2) and the first to fourth signal lines 11 to 14 for transmitting clock signals (detailed in Figure 1A). The first clock signal CLK1 is supplied to the first signal line 11. The second clock signal CLK2 is supplied to the second signal line 12. The third clock signal CLK3 is supplied to the third signal line 13. The fourth clock signal CLK4 is supplied to the fourth signal line 14.

The clock signal is a signal that alternates between the H-level signal (high potential) and the L-level signal (low potential) at regular intervals. Here, the first to fourth clock signals CLK1 to CLK4 are sequentially delayed by 1/4 cycle. In this embodiment, the pulse signal output circuit is controlled by using the clock signal.

First to nth pulse signal output circuit 10_₁To 10__nEach of It includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (detailed in Fig. 1B).

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth signal lines 11-14. For example, the first pulse signal output circuit 10_₁The first input terminal 21 is electrically connected to the first signal line 11, and the first pulse signal output circuit 10_₁The second input terminal 22 is electrically connected to the second signal line 12 and the first pulse signal output circuit 10_₁The third input terminal 23 is electrically connected to the third signal line 13. In addition, the second pulse signal output circuit 10_₂The first input terminal 21 is electrically connected to the second signal line 12, and the second pulse signal output circuit 10_₂The second input terminal 22 is electrically connected to the third signal line 13, and the second pulse signal output circuit 10_₂The third input terminal 23 is electrically connected to the fourth signal line 14. Please note that it is described here that the second to fourth signal lines 12 to 14 are connected to the nth pulse signal output circuit 10__nThe situation. However, connect the n-th pulse signal output circuit 10__nThe signal line varies with the value of n. Therefore, it should be noted that the configuration described in the text is only an example.

In the m-th pulse signal output circuit of the shift register described in this embodiment (m is a natural number greater than or equal to 2), the fourth input terminal 24 in the m-th pulse signal output circuit is electrically connected to the ( m-1) The first output terminal 26 in the pulse signal output circuit. The fifth input terminal 25 of the mth pulse signal output circuit is electrically connected to the first output terminal 26 of the (m+2)th pulse signal output circuit. The first input terminal 26 in the mth pulse signal output circuit is electrically connected to the fourth in the (m+1)th pulse signal output circuit Input terminal 24. The second output terminal 27 in the m-th pulse signal output circuit outputs a signal to OUT(m).

For example, the third pulse signal output circuit 10_₃The fourth input terminal 24 is electrically connected to the second pulse signal output circuit 10_₂In the first output terminal 26. The third pulse signal output circuit 10_₃The fifth input terminal 25 is electrically connected to the fifth pulse signal output circuit 10_₅In the first output terminal 26. The third pulse signal output circuit 10_₃The first input terminal 26 is electrically connected to the fourth pulse signal output circuit 10_₄The fourth input terminal 24 and the first pulse signal output circuit 10_₁In the fifth input terminal 25.

In addition, the first start pulse (SP1) is input from the fifth wiring 15 to the first pulse signal output circuit 10_₁In the fourth input terminal 24. The pulse output from the previous stage is input to the kth pulse signal output circuit 10__k(k is a natural number greater than or equal to 2 and less than or equal to n) in the fourth input terminal 24. The second start pulse (SP2) is input to the (n-1)th pulse signal output circuit 10__n-1In the fifth input terminal 25. The third start pulse (SP3) is input to the m-th pulse signal output circuit 10__mIn the fifth input terminal 25. The second start pulse (SP2) and the third start pulse (SP3) can be input from the outside or generated inside the circuit.

Next, the first to nth pulse signal output circuits 10_ will be explained.₁To 10__nThe specific configuration.

First to nth pulse signal output circuit 10_₁To 10__nEach of them includes a pulse signal generating circuit 200 including first to fourth transistors 101 to 104; a first input signal generating circuit 201 including fifth to seventh transistors 105 to 107; and includes eighth to tenth A transistor 108 to 111 The second input signal generating circuit 202 (detailed in Figure 1C). In addition, in addition to the first to fifth input terminals 21 to 25, signals are supplied from the first power line 31 and the second power line 32 to the first to eleventh transistors 101 to 111.

A specific example of the configuration of the pulse signal generating circuit is as follows.

The first terminal of the first transistor 101 (hereinafter, "first terminal" means one of the source terminal and the drain terminal), the first terminal of the second transistor 102, and the first output terminal 26 are electrically connected to each other . Similarly, the first terminal of the third transistor 103, the first terminal of the fourth transistor 104, and the second output terminal 27 are electrically connected to each other. The gate terminal of the first transistor 101, the gate terminal of the third transistor 103, and the output terminal of the first input signal generating circuit are electrically connected to each other. The gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generating circuit are electrically connected to each other.

The second terminal of the first transistor 101 (hereinafter, "the second terminal" refers to the other of the source terminal and the drain terminal) and the second terminal of the third transistor are electrically connected to each other, and the first clock signal CLK1 inputs the nodes connected to each other. The second terminal of the first transistor 101 and the second terminal of the third transistor are used as the first input terminal 21 of the pulse signal output circuit. The second terminal of the second transistor 102 is supplied with a first potential (for example, a low potential Vss) via the first power line 31. The second terminal of the fourth transistor 104 is supplied with the first potential via the first power line 31.

A specific example of the configuration of the first input signal generating circuit is as follows.

The first terminal of the fifth transistor 105, the first terminal of the sixth transistor 106 The terminal and the first terminal of the seventh transistor 107 are electrically connected to each other. In addition, the second terminal of the seventh transistor 107 serves as the output terminal of the first input signal generating circuit. The gate terminal of the fifth transistor 105 serves as the first input terminal of the first input signal generating circuit and also serves as the fourth input terminal 24 of the pulse signal output circuit.

The second potential is supplied to the second terminal of the fifth transistor 105 through the second power line 32. The first potential is supplied to the second terminal of the sixth transistor 106 via the first power line 31. The pulse signal from the previous stage (in the first pulse signal output circuit, the pulse signal is the start pulse signal) is input to the gate terminal of the fifth transistor 105. The output signal of the second input signal generating circuit is input to the gate terminal of the sixth transistor 106. The gate terminal of the sixth transistor 106 serves as the second input terminal of the first input signal generating circuit. The second potential is supplied to the gate terminal of the seventh transistor 107 through the second power line 32.

Although the seventh transistor 107 is configured in this embodiment, a configuration without the seventh transistor 107 can be used. Based on the seventh transistor 107, it is possible to suppress the increase in the potential of the first terminal of the fifth transistor 105 caused by the start-up operation. That is, it is possible to prevent a high voltage from being applied to the region between the gate and the source (or between the gate and the drain) of the fifth transistor 105; therefore, the deterioration of the fifth transistor 105 can be suppressed.

A specific example of the configuration of the second input signal generating circuit is as follows.

The second terminal of the tenth transistor 110 and the first terminal of the eighth transistor 108 are electrically connected to each other. The second terminal of the eighth transistor, the second terminal of the eleventh transistor, and the first terminal of the ninth transistor are electrically connected to each other, And as the output terminal of the second input signal generating circuit.

The second potential is supplied to the first terminal of the eleventh transistor 111 and the first terminal of the tenth transistor 110 via the second power line 32. The first potential is supplied to the second terminal of the ninth transistor 109 via the first power line 31. The pulse signal from the subsequent pole of the next stage is input to the gate terminal of the eleventh transistor 111. The gate terminal of the eleventh transistor 111 serves as the first input terminal of the second input signal generating circuit and also serves as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal CLK2 is input to the gate terminal of the eighth transistor 108. The gate terminal of the eighth transistor 108 serves as the second input terminal of the second input signal generating circuit and also serves as the second input terminal 22 of the pulse signal output circuit. The pulse signal from the previous stage (in the first pulse signal output circuit, the pulse signal is the starting pulse signal) is input to the gate terminal of the ninth transistor 109. The gate terminal of the ninth transistor 109 serves as the third input terminal of the second input signal generating circuit and also serves as the fourth input terminal 24 of the pulse signal output circuit. The third clock signal CLK3 is input to the gate terminal of the tenth transistor 110. The gate terminal of the tenth transistor 110 serves as the fourth input terminal of the second input signal generating circuit and also serves as the third input terminal 23 of the pulse signal output circuit.

Please note that the components of the pulse signal output circuit (for example, the configuration examples of the pulse signal generation circuit, the first input signal generation circuit, and the second input signal generation circuit) are only examples, and the disclosed invention is not limited thereto.

In the following description of this embodiment, the gate terminal of the first transistor 101, the gate terminal of the third transistor 103, and the output terminal of the first input signal generating circuit in the pulse signal output circuit of FIG. 1C are connected to each other. Festival The point is called node A. In addition, the node at which the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generating circuit are connected to each other is called node B.

A capacitor that advantageously executes the start-up program operation can be arranged between the node A and the first output terminal 26. In addition, a capacitor electrically connected to node B can be configured to maintain the potential of node B.

In FIG. 1C, the ratio W/L of the channel width W of the first transistor 101 to the channel length L and the ratio W/L of the channel width W of the third transistor 103 to the channel length L are preferably larger than those of the first transistor. The ratio of the channel width W of the six transistor 106 to the channel length L is W/L.

In FIG. 1C, the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W/L of the channel width W to the channel length L of the sixth transistor 106. The ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is preferably equal to the ratio W/L of the channel width W to the channel length L of the seventh transistor 107. On the other hand, the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W/L of the channel width W to the channel length L of the seventh transistor 107.

In FIG. 1C, the ratio W/L of the channel width W to the channel length L of the third transistor 103 is preferably greater than the ratio W/L of the channel width W to the channel length L of the fourth transistor 104.

In FIG. 1C, the channel width W of the eighth transistor 108 and the channel width W of the tenth transistor 110 are preferably smaller than the channel width W of the eleventh transistor 111.

An oxide semiconductor is preferably used for the first to eleventh transistors 101 to 111. The use of oxide semiconductors can reduce the off-state current of the transistor. In addition, compared to using amorphous silicon, the on-state current and field effect mobility can be increased. In addition, the deterioration of the transistor can be suppressed. Therefore, it embodies a low-power electronic circuit that can operate at high speed and with higher accuracy. Please note that since it is described in detail in the following embodiments, the description of the transistor including the oxide semiconductor is omitted here.

&lt;job&gt;

Next, referring to FIG. 2, FIGS. 3A to 3C, FIGS. 4A to 4C, and FIG. 14, the operation of the shift register in FIGS. 1A to 1C will be described. Specifically, operations in each of the first to sixth periods 51 to 56 in the timing chart of FIG. 2 will be described with reference to FIGS. 3A to 3C and FIGS. 4A to 4C. In the timing chart, CLK1 to CLK4 represent clock signals; SP1 represents the first start pulse; OUT1 to OUT4 represent signals from the first to fourth pulse signal output circuits 10_₁To 10_₄The output of the second output terminal; node A and node B represent the potentials of node A and node B; and SROUT1 to SROUT4 represent signals from the first to fourth pulse signal output circuits 10_₁To 10_₄The output of the first output terminal.

Please note that in the following description, the first to eleventh transistors 101 to 111 are all n-channel transistors. In addition, in FIGS. 3A to 3C and FIGS. 4A to 4C, the solid line indicates that the transistor is in a conducting state (open), and the dotted line indicates that the transistor is in a non-conducting state (closed) .

Typically, the first pulse signal output circuit 10_₁Of homework. The first pulse signal output circuit 10_₁The configuration is as above. In addition, the relationship between the input signal and the supplied potential is also as described above. Please note that in the following description, V_DDUsed to supply all high potentials (also called H-level, H-level signals, etc.) to input terminals and power lines, and Vss is used to use all low potentials supplied to input terminals and power lines (also known as L Level, L level signal, etc.).

In the first period 51, SP1 is at the H level, so that a high potential is supplied to the gate terminal of the fifth transistor 105 and the gate terminal of the ninth transistor 109, which serves as the first pulse signal output circuit 10_₁In the fourth input terminal 24. Therefore, the fifth transistor 105 and the ninth transistor 109 are turned on. In the first period 51, CLK3 is also at the H level, so that the tenth transistor 110 is also turned on. In addition, since a high potential is supplied to the gate terminal of the seventh transistor 107, the seventh transistor 107 is also turned on (detailed in FIG. 3A).

When the fifth transistor 105 and the seventh transistor 107 are turned on, the potential of the node A increases. When the ninth transistor 109 is turned on, the potential of the node B decreases. The potential of the second terminal of the fifth transistor 105 is V_DD. Therefore, the potential of the first terminal of the fifth transistor 105 becomes V_DD-V_th105This is the potential obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the second terminal. The potential of the gate terminal of the seventh transistor 107 is V_DD. Therefore, if the threshold voltage of the seventh transistor 107 is V_th107Is greater than or equal to V_th105, The potential of node A becomes V_DD-V_th107, Thereby turning off the seventh transistor 107. On the other hand, if V_th107Below V_th105, The potential of node A increases to V_DD-V_th105At the same time, the seventh transistor 107 remains on. Hereinafter, the symbol (the highest potential) of node A in the first period 51 is determined by V_AHExpress.

When the potential of node A becomes V_AHAt this time, the first transistor 101 and the third transistor 103 are turned on. Here, since CLK1 is at the L level, the L level signal is output from the first output terminal 26 and the second output terminal 27.

In the second period 52, the potential of CLK1 changes from the L level to the H level. As the first transistor 101 and the third transistor 103 are turned on, the potential of the first output terminal 26 and the potential of the second output terminal 27 increase. In addition, a capacitance is generated between the gate terminal and the source terminal (or drain terminal) of the first transistor 101; based on this capacitance, the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Similarly, a capacitance is generated between the gate terminal of the third transistor 103 and the source terminal (or drain terminal); based on this capacitance, its gate terminal and the source terminal (or drain terminal) are capacitively coupled. Therefore, as the potential of the first output terminal 26 and the potential of the second output terminal 27 increase (start program operation), the potential of the node A in the floating state increases. The potential of node A finally becomes higher than V_DD+V_th101, And each of the potential of the first output terminal 26 and the potential of the second output terminal 27 becomes V_DD(H level) (Detailed Figure 2 and Figure 3B).

In the second period 52, the ninth transistor 109 is in the on state; therefore, the node B maintains the L level. Therefore, the potential change of the node B caused by the capacitive coupling can be suppressed, which occurs when the potential of the first output terminal 26 changes from the L level to the H level, so that failures due to potential changes can be avoided.

As mentioned above, in the second period 52, if the potential of the second output terminal 27 At the H level, the gate voltage (Vgs) of the third transistor 103 needs to be sufficiently high to turn on the third transistor 103 to ensure that the potential of the second output terminal 27 is increased to V_DD(H level). If the Vgs of the third transistor 103 is low, the drain current of the third transistor 103 is small, so that it takes a very long time to increase the potential of the second output terminal 27 to V in a specific period (here in the second period)_DD(H level). Therefore, the rise of the waveform of the second output terminal 27 becomes gradual, which causes a malfunction.

Please note that the Vgs of the third transistor 103 in the second period 52 depends on the potential of the node A in the first period 51. Therefore, in order to increase the Vgs of the third transistor 103, the electricity of the node A in the first period 51 should be as high as possible (considering the circuit design, the maximum value is V_DD-V_th105Or V_DD-V_th107). The same situation is also suitable for the Vgs of the first output terminal 26 and the first transistor 101.

Therefore, the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W/L of the channel width W to the channel length L. When the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is greater than the ratio W/L of the channel width W to the channel length L of the sixth transistor 106, the node A in the first period 51 Potential can be increased to V in a shorter time_DD-V_th105Or V_DD-V_th107. Please note that during the first period 51, the sixth transistor 106 is turned off. When the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 is greater than the ratio W/L of the channel width W to the channel length L of the sixth transistor 106, the leakage current in the sixth transistor 106 (I_off) Can be small, so the potential of node A can be increased in a shorter time Add to V_DD-V_th105。

When the channel length L becomes shorter due to the miniaturization of the transistor, sometimes the threshold voltage shifts and the sixth transistor 106 acts as a normally-on transistor. Even under these conditions, when the ratio W/L of the channel width W to the channel length L of the sixth transistor 106 is smaller than the ratio W/L of the channel width W to the channel length L of the fifth transistor 105, the first The turn-on resistance of the sixth transistor 106 may be greater than the turn-on resistance of the fifth transistor 105. Therefore, the potential of node A can be close to V_DD-V_th105Or V_DD-V_th107Of potential.

The ratio W/L of the channel width W to the channel length L of the fifth transistor is preferably almost equal to the ratio W/L of the channel width W to the channel length L of the seventh transistor 107. If it is understood that the two targets have the same value, considering the slight difference due to manufacturing errors or changes, the expression "almost equal" can be used. When the ratio W/L of the channel width W to the channel length L of the fifth transistor 105 and the ratio W/L of the channel width W to the channel length L of the seventh transistor 107 are equal to each other, the difference between the fifth transistor 105 The current supply capability and that of the seventh transistor 107 can be equal to each other; therefore, the potential of the node A can be efficiently increased. Please note that the threshold voltage V of the fifth transistor 105_thAnd the seventh transistor 107 are preferably almost equal to each other.

Please note that the ratio W/L of the channel width W of the fifth transistor 105 to the channel length L can be based on the characteristics of the transistor, the clock frequency, the gate capacitance of the first transistor 101, and the gate of the third transistor 103. The capacitor, the operating voltage of the shift register, etc. are determined.

When the channel width W of the sixth transistor 106 is large, if the sixth transistor 106 is used as a normally open transistor, the leakage current will increase; therefore, The potential at point A decreases. In addition, the node A is prevented from being charged by the fifth transistor 105. If high-speed operation is required, the potential of node B needs to be lowered in a short time in order to charge node A. In this situation, the potential of the sixth transistor needs to be lowered in a short time.

Therefore, when the channel width W of the sixth transistor is smaller than that of the fifth transistor, the potential change of the node A can be avoided. In addition, the load of Node B can be reduced. In this way, the dimensions of the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are determined by considering the characteristics of the transistors and the driving specifications, so that a highly efficient shift register can be realized.

In the third period 53, SP1 becomes the L level, so that the fifth transistor 105 and the ninth transistor 109 are turned off. In addition, CLK1 maintains the H level and the potential of node A unchanged; therefore, V is output from the first output terminal 26 and the second output terminal 27_DD(H level signal) (detailed in Figure 3C). Please note that in the third period 53, although the node B is in a floating state, the potential of the first output terminal 26 does not change; therefore, the failure due to capacitive coupling can be ignored.

In the fourth period 54, since CLK2 and CLK3 are both at the H level, the power of node B increases for a short time. In addition, CLK1 becomes the L level. Therefore, the second transistor 102 and the fourth transistor 104 are turned on, so that the electricity of the first output terminal 26 and the second output terminal 27 is reduced in a short time (detailed in FIG. 4A). In addition, the sixth transistor 106 is turned on, so that the potential of the node A becomes the L level. Therefore, the first transistor 101 and the third transistor 103 are turned off, whereby the potential of the first output terminal 26 and the potential of the second output terminal 27 become the L level.

In the fourth period 54, the potential of the node A should decrease to Vss before CLK1 reaches the H level in the sixth period (ie, in the fourth period 54 and the fifth period 55). When the potential of node A does not decrease to Vss in the fifth period 55, the potential of node A increases again due to the capacitive coupling between the gate and source of the third transistor 103; thus, the first transistor 101 and The third transistor 103 is turned on, and charges flow through the first output terminal 26 and the second output terminal 27, so that a malfunction may occur.

Therefore, the following equations (1) to (7) are used to determine the relationship between the first transistor 101, the third transistor 103, and the sixth transistor 106, thereby reducing the operation failure due to load and achieving stable operation .

i₁₀₆=(C₁₀₁+C₁₀₃)xV_f/t_off (1)

i₁₀₆=W₁₀₆/2L₁₀₆×μ×Cox×(Vgs₁₀₆-V_th106)² (2)

1/f_clk=T=t_CKH+t_CKL (3)

t_off=t_CKL-t_α (4)

C₁₀₁=L₁₀₁×W₁₀₁×Cox (5)

C₁₀₃=L₁₀₃×W₁₀₃×Cox (Cox=ε₀×ε_r/tox) (6)

V_f=(Vdd-V_th105)+Vdd (7)

In the above equation, t_CKHCorresponding to the period when CLK1 is at the H level, that is, the second period 52 and the third period 53; t_CKLCorresponding to the period when CLK1 is at the L level, that is, the fourth period 54 and the fifth period 55; and t_offCorresponding to the time required for the potential of node A to drop to Vss. That is, at t_CKLIn, the electricity of node A is located at t_offReduced to Vss. t_offIt is not particularly limited, as long as it is in the period from the fourth period 54 to the fifth period 55; for example, t_offIn the fourth period 54_1, from the fourth period 54_1 through the fourth period 54_1 The period 54_3, or the period from the fourth period 54_1 through the fourth period 54_5 (detailed in FIG. 14). In particular, the period from the fourth period 54_1 to the fourth period 54_3 corresponding to 1/2 of the period from the fourth period 54 to the fifth period 55 is preferable. The reason is as follows: when t_offSet relative to t_CKLIf it is too short, the channel width W of the sixth transistor 106 needs to be set to be large in order to quickly reduce the potential of the node A. Relatively, when t_offWhen set to long time, the potential of node A cannot be reduced to Vss before the next H-level clock signal is input, and a malfunction may occur. That is, t_offIt is determined by considering the frequency of the clock signal, etc. Please note that in the timing diagram of FIG. 14, part of the period is exaggerated (for example, the period from the fourth period 54_1 through the fourth period 54_5) is exaggerated; however, this timing diagram is not very different from the timing diagram in FIG. 2 .

C₁₀₁And C₁₀₃Denote the gate capacitance of the first transistor 101 and the gate capacitance of the third transistor 103, respectively. V_fIndicates the potential of the node A in the third period 53.

I in equation (2)₁₀₆Indicates the drain current of the sixth transistor 106. Using this, the size of the sixth transistor 106 (for example, W/L) can be determined. In other words, considering the operating frequency of CLK1, the size of the first transistor 101, the size of the third transistor 103, and the potential of the node A, the size of the sixth transistor 106 can be determined.

For example, if the operating frequency of CLK1 is high, the potential of node A needs to decrease quickly; therefore, from equation (1), t_offShould be short. Therefore, i₁₀₆Should be large. W₁₀₆Is based on equation (2) i₁₀₆Calculate and decide.

On the other hand, if the size of the first transistor 101 and the size of the third transistor 103 are small, i₁₀₆Can be small; therefore, from equation (2) W₁₀₆Become small. Please note that since the third transistor 103 is used to charge and discharge the output load, by increasing the size of the third transistor during discharging, not only the fourth transistor 104 but also the third transistor 103 is discharged. Therefore, the output potential can be reduced in a short time. Therefore, when the potential of the node A gradually decreases, compared to the situation where only the fourth transistor 104 is discharged, the output potential can be reduced in a short time because the third transistor 103 is in the on state. In this way, the size of the sixth transistor 106 is determined by considering the characteristics of the transistor and the driving specifications, so that a highly efficient shift register can be realized.

In the fourth period 54, the potential CLK1 changes from the H level to the L level, and the pulse signal (SROUT3) is input to the fifth input terminal. Therefore, the eleventh transistor 111 is turned on. Since the eleventh transistor 111 is turned on, the potential of node B increases to V_DD-V_th111. Therefore, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are turned on. When the second transistor 102 and the fourth transistor 104 are turned on, the potential of the first output terminal 26 and the potential of the second output terminal 27 become Vss. Please note that the first transistor 101 and the third transistor 103 are turned off.

At this time, except for the eleventh transistor 111, the node B is charged via the tenth transistor 110 and the eighth transistor 108. The gate of the tenth transistor 110 and the gate of the eighth transistor 108 are respectively connected to the third input terminal 23 and the second input terminal 22, and the gate capacitor of the tenth transistor 110 and the gate of the eighth transistor 108 The capacitances respectively correspond to the negative of the third input terminal 23 Load and the load of the second input terminal 22.

Please note that in the shift register described in this embodiment, the load of the transistor connected to the clock line is expressed as "the total number of stages of the shift register ÷ 4 x (L of the third transistor 103)_ov+L of the first transistor 101_ov+gate capacitance of the tenth transistor 110 + gate capacitance of the eighth transistor 108)". Please note that the gate capacitance is expressed as "ε₀×ε×(L×W)/tox". Please note that L_ovIt represents the length of the region where the source electrode layer or the drain electrode layer of the transistor overlaps the semiconductor layer along the channel length direction.

In order to reduce the gate capacitance connected to the clock line, the channel width W of the eighth transistor 108 and the channel width W of the tenth transistor 110 are preferably smaller than the channel width W of the eleventh transistor 111. Based on these structures, the load on the clock line can be reduced, thereby enabling high-speed operation. When the channel width W of the tenth transistor 110 and the channel width W of the eighth transistor 108 are reduced, a reduction in the layout area can be achieved.

In the fifth period 55, the potential of the fifth input terminal 25 (ie, SROUT3) is maintained at the H level, thereby maintaining the potential of the node B. Therefore, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept on, so that the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level (detailed in FIG. 4B).

In the sixth period 56, the fifth input terminal 25 (ie SROUT3) becomes the L level, so that the eleventh transistor 111 is turned off. At this time, the node B is in a floating state while maintaining the potential. Therefore, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept on (detailed in FIG. 4C). Please note that the potential of node B is usually due to the off-state current of the transistor And reduce. However, a transistor with a sufficiently low off-state current (for example, a transistor including an oxide semiconductor) does not have these problems. Please note that a capacitor can be configured to reduce the potential drop of node B.

If both CLK2 and CLK3 become the H level in the subsequent period, the eighth transistor 108 and the tenth transistor 110 are turned on, and the potential is periodically supplied to the node B. Therefore, even when a transistor whose off-state current is quite large is used, the malfunction of the pulse signal output circuit can be avoided.

Please note that with regard to the output from the shift register (such as OUT1 to OUT4), there is a situation where the potential increase time is estimated, and the potential decrease time situation is estimated. For example, in a situation where data is determined by an increase in potential (for example, when data is written), the time for the increase in potential is estimated. If the data is determined by the potential drop, the time for the potential drop is estimated.

If the data is determined by the potential increase, the time required to increase the potential needs to be short. For this purpose, the ratio W/L of the channel width W to the channel length L of the third transistor 103 is preferably greater than the ratio W/L of the channel width W to the channel length L of the fourth transistor 104.

If the data is determined by potential reduction, the time required to reduce the potential should be short. For this purpose, the ratio W/L of the channel width W to the channel length L of the third transistor 103 is preferably greater than the ratio W/L of the channel width W to the channel length L of the fourth transistor 104.

Please note that in an embodiment of the disclosed invention, the potential of the node A is increased to a predetermined potential by the start-up procedure using the capacitive coupling between the gate and the source of the third transistor 103. Therefore, the third transistor 103 is turned on, and the H level signal is output. Therefore, when the ratio W/L of the channel width W of the third transistor 103 to the channel length L is not sufficiently large, the H level potential output from the shift register does not increase to V_DD, May cause problems. Therefore, it is preferable that the ratio W/L of the channel width W of the third transistor 103 to the channel length L is sufficiently large.

In addition, the shift register of this embodiment is driven by a driving method in which the pulse output from the m-th pulse signal output circuit overlaps with half of the pulse output from the (m+1)-th pulse signal output circuit. Therefore, the wiring can be charged for a longer time compared to the case of using the driving method. That is, based on the driving method, a pulse signal output circuit is provided that supports heavy loads and operates at high frequencies.

[Example 2]

In this embodiment, with reference to FIGS. 5A to 5C, FIGS. 6, 7A to 7C, and FIGS. 8A and 8B, different modes of the pulse signal output circuit and shift register described in the above embodiment and its operation will be described. The configuration example of pulse signal output circuit and shift register.

&lt;circuit configuration&gt;

First, a configuration example of the pulse signal output circuit and the shift register including the pulse signal output circuit will be described with reference to FIGS. 5A to 5C.

The configuration of the shift register described in this embodiment is similar to that of the shift register described in the above embodiment. One of the differences between them is that the third input terminal 23 is not configured in the first to nth pulse signal output circuits. 10_₁To 10__nMedium (detailed Figures 5A to 5C). That is, two types of clock signals are input to a pulse signal output circuit. The other structure is similar to the above-mentioned embodiment.

Since the third input terminal 23 is not configured in the first to nth pulse signal output circuits 10_₁To 10__n, The tenth transistor connected to the third input terminal 23 is not configured (detailed in Fig. 5C). Therefore, the connection relationship of the second input signal generating circuit 202 in FIG. 1C and the connection relationship of the second input signal generating circuit 203 in FIG. 5C are partially different from each other.

Specifically, the first to nth pulse signal output circuits 10_₁To 10__nEach of them includes a pulse signal generating circuit 200 including first to fourth transistors 101 to 104; a first input signal generating circuit 201 including fifth to seventh transistors 105 to 107; and an eighth transistor 108 , The second input signal generating circuit 203 of the ninth transistor 109, and the eleventh transistor 111. Except for the first to fifth input terminals 21 to 25, signals are supplied from the first power line 31 and the second power line 32 to the first to eleventh transistors 101 to 111.

A specific example of the configuration of the second input signal generating circuit 203 is as follows.

The second terminal of the eighth transistor 108, the second terminal of the eleventh transistor 111, and the first terminal of the ninth transistor 109 are electrically connected to each other, and serve as the output terminal of the second input signal generating circuit.

The second potential is supplied to the first terminal of the eleventh transistor 111 and the first terminal of the eighth transistor 108 via the second power line 32. The first potential is supplied to the second terminal of the ninth transistor 109 via the first power line 31. The pulse signal is input to the gate terminal of the eleventh transistor 111. eleventh The gate terminal of the transistor 111 serves as the first input terminal of the second input signal generating circuit and also serves as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal CLK2 is input to the gate terminal of the eighth transistor 108. The gate terminal of the eighth transistor 108 serves as the second input terminal of the second input signal generating circuit and also serves as the second input terminal 22 of the pulse signal output circuit. The pulse signal is input to the gate terminal of the ninth transistor 109. The gate terminal of the ninth transistor 109 serves as the third input terminal of the second input signal generating circuit and also serves as the fourth input terminal 24 of the pulse signal output circuit.

Please note that the above configuration is only an example, and the disclosed invention is not limited to this.

In the following description of this embodiment, as in the above embodiment, the gate terminal of the first transistor 101, the gate terminal of the third transistor 103, and the first input signal generating circuit in the pulse signal output circuit of FIG. 5C The node where the output terminals are connected to each other is called node A. In addition, the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, the second terminal of the eighth transistor 108, the second terminal of the eleventh transistor 111, and the ninth transistor 109 The node where the first terminals are connected to each other is called node B.

A capacitor that advantageously executes the start-up program operation can be arranged between the node A and the first output terminal 26. In addition, a capacitor electrically connected to node B can be configured to maintain the potential of node B.

Oxide semiconductors are preferably used for the first to ninth transistors 101 to 109 and the eleventh transistor 111. The use of oxide semiconductors can reduce the off-state current of the transistor. In addition, compared to if amorphous silicon is used, It can increase the on-state current and field effect mobility. In addition, the deterioration of the transistor can be suppressed. Therefore, it embodies a low-power electronic circuit that can operate at high speed and with higher accuracy. Please note that since it is described in detail in the following embodiments, the description of the transistor including the oxide semiconductor is omitted here.

&lt;job&gt;

Next, the operation of the shift register in FIGS. 5A to 5C will be described with reference to FIGS. 6, 7A to 7C, and FIGS. 8A and 8B. Specifically, the operations in each of the first to fifth periods 51 to 55 in the timing chart of FIG. 6 will be described with reference to FIGS. 7A to 7C and FIGS. 8A and 8B. In the timing chart, CLK1 to CLK4 represent clock signals; SP1 represents the first start pulse; OUT1 to OUT4 represent signals from the first to fourth pulse signal output circuits 10_₁To 10_₄The output of the second output terminal; node A and node B represent the potentials of node A and node B; and SROUT1 to SROUT4 represent signals from the first to fourth pulse signal output circuits 10_₁To 10_₄The output of the first output terminal.

Please note that in the following description, the first to ninth transistors 101 to 109 and the eleventh transistor 111 are all n-channel transistors. In addition, in FIGS. 7A to 7C and FIGS. 8A and 8B, the transistor marked by a solid line indicates that the transistor is in a conducting state (open), and a transistor marked by a dotted line indicates that the transistor is in a non-conducting state (closed) .

Typically, the first pulse signal output circuit 10_₁Of homework. The first pulse signal output circuit 10_₁The configuration is as above. In addition, the relationship between the input signal and the supplied potential is also as described above. Please note that in the following Mingzhong, V_DDUsed to supply all high potentials (also called H-level, H-level signals, etc.) to input terminals and power lines, and Vss is used to use all low potentials supplied to input terminals and power lines (also known as L Level, L level signal, etc.).

In the first period 51, SP1 is at the H level, so that a high potential is supplied to the gate terminal of the fifth transistor 105 and the gate terminal of the ninth transistor 109, which serves as the first pulse signal output circuit 10_₁In the fourth input terminal 24. Therefore, the fifth transistor 105 and the ninth transistor 109 are turned on. Since the high potential is supplied to the gate terminal of the seventh transistor 107, the seventh transistor 107 is also turned on (detailed in FIG. 7A).

The fifth transistor 105 and the seventh transistor 107 are turned on, whereby the potential of the node A increases. The ninth transistor 109 is turned on, whereby the potential of the node B is lowered. When the potential of node A reaches V_AHHour (V_AH=V_DD-V_th105-V_th107), the fifth transistor 105 and the seventh transistor 107 are turned off, and the node A is brought into a floating state while maintaining its potential at V_AH。

When the potential of node A becomes V_AHAt this time, the first transistor 101 and the third transistor 103 are turned on. Here, since CLK1 is at the L level, the L level signal is output from the first output terminal 26 and the second output terminal 27.

In the second period 52, the potential of CLK1 changes from the L level to the H level. As the first transistor 101 and the third transistor 103 are turned on, the potential of the first output terminal 26 and the potential of the second output terminal 27 increase. In addition, a capacitance is generated between the gate terminal and the source terminal (or drain terminal) of the first transistor 101; based on this capacitance, the gate terminal and the source terminal (or drain terminal) are capacitively coupled. Similarly, the gate terminal of the third transistor 103 A capacitance is generated between the source terminal (or drain terminal); based on this capacitance, its gate terminal and the source terminal (or drain terminal) are capacitively coupled. Therefore, as the potential of the first output terminal 26 and the potential of the second output terminal 27 increase (start program operation), the potential of the node A in the floating state increases. The potential of node A finally becomes higher than V_DD+V_th101, And each of the potential of the first output terminal 26 and the potential of the second output terminal 27 becomes V_DD(H level) (Detailed Figure 6 and Figure 7B).

In the third period 53, the potential of CLK2 becomes the H level, and the eighth transistor 108 is turned on. Therefore, the potential of node B increases. When the potential of the node B increases, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are turned on, and the potential of the node A decreases. Therefore, the potential of the first output terminal 26 and the potential of the second output terminal 27 become the L level (detailed in FIG. 7C).

In the fourth period 54, the potential of CLK2 becomes the L level, and the eighth transistor 108 is turned off. The potential of the fifth input terminal 25 (ie, SROUT3) becomes the H level, and the eleventh transistor 111 is turned on. Therefore, the potential of the node A and the electricity of the node B are maintained during the third period 53, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are maintained at the L level (detailed in FIG. 8A).

In the fifth period 55, the potential of the fifth input terminal 25 (ie, SROUT3) becomes the L level, and the potential of the node B remains. Therefore, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept on, so that the potential of the first output terminal 26 and the potential of the second output terminal 27 are maintained at the L level (detailed in FIG. 8B).

Please note that the potential of node B is usually reduced due to, for example, the off-state current of the transistor. However, a transistor with a sufficiently low off-state current (for example, a transistor including an oxide semiconductor) does not have these problems. In order to reduce the potential drop of node B, a capacitor can be configured. The configured capacitor is electrically connected to the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, the gate terminal of the sixth transistor 106, and the first terminal of the eighth transistor 108 under this condition , And the first terminal of the ninth transistor 109.

If the power of CLK2 becomes the H level in the subsequent period, the eighth transistor 108 is turned on, and the potential is periodically supplied to the node B. Therefore, even when a transistor whose off-state current is quite large is used, the malfunction of the pulse signal output circuit can be avoided.

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

[Example 3]

In this embodiment, the configuration of the pulse signal output circuit and shift register having a different mode from the pulse signal output circuit and shift register described in any of the above embodiments will be described with reference to FIGS. 9A to 9C example.

The configuration of the shift register described in this embodiment is similar to that of the shift register described in the above embodiment. One of the differences between them lies in the first dummy pulse signal output circuit 10__D1And the second dummy pulse signal output circuit 10__D2Connect to the subsequent stage of the n-th pulse signal output circuit 10_n (detailed in Fig. 9A). The first dummy pulse signal output circuit 10__D1And the second dummy pulse signal output circuit 10__D2Have the supply pulse signal at the (n-1) And the nth pulse signal output circuit 10__n-1And the function of the fifth input terminal 25 of 10_n.

The pulse signal output circuit is not configured in the first dummy pulse signal output circuit 10__D1And the second dummy pulse signal output circuit 10__D2The follow-up level. That is, the pulse signal is not input from the subsequent stage to the first dummy pulse signal output circuit 10__D1And the second dummy pulse signal output circuit 10__D2(In this case, it is the subsequent stage of the respective next stage), which is different from the first to nth pulse signal output circuits. Therefore, the terminals corresponding to the fifth input terminal 25 of the first to n-th pulse signal output circuits are not arranged (detailed FIGS. 9B and 9C). In addition, there is no eleventh transistor 111 related to the fifth input terminal 25 (detailed in FIG. 9C).

The function of the dummy pulse signal output circuits (first and second dummy pulse signal output circuits) is to output appropriate pulse signals to the pulse signal output circuits in the normal stage (the (n-1)th and nth pulse signal output circuits); therefore , The virtual pulse signal output circuit needs to have the ability to fully charge node B. Here, in the first to nth pulse signal output circuits, the dimensions of the eighth transistor 108 and the tenth transistor 110 are small (for example, the channel width W is small, or the ratio of the channel width W to the channel length L W/L is small), so that the eleventh transistor 111 can ensure the charging capacity, so as to reduce the power consumption due to the input of the clock signal. On the other hand, in the virtual pulse signal output circuit, the eleventh transistor 111 is not configured; therefore, the sizes of the eighth transistor 108 and the tenth transistor 110 need to be large, so that the size of the eleventh transistor 111 can be compensated. Charging capacity.

Specifically, for example, the first and second dummy pulse signal output circuits Each of the channel width W (or the ratio of the channel width W to the channel length L, W/L) of the eight transistors can be greater than the channel width W (or channel The ratio of the width W to the channel length L (W/L), or the channel width W of the tenth transistor in the first and second dummy pulse signal output circuits (or the ratio of the channel width W to the channel length L) Each of W/L) may be greater than each of the channel width W (or the ratio W/L of the channel width W to the channel length L) of the tenth transistor in the first to nth pulse signal output circuits. Based on these structures, the power consumption of the pulse signal output circuit in the normal stage (the (n-1) and nth pulse signal output circuits) can be reduced, and a shift register that can perform proper operation can be realized.

Please note that except for the above differences, the basic configuration of the virtual pulse signal output circuit is similar to that of the pulse signal output circuit described in the above embodiment. Specifically, the first to nth pulse signal output circuits 10_₁To 10__nEach of them includes a dummy pulse signal generating circuit 204 including first to fourth transistors 101 to 104; a first input signal generating circuit 205 including fifth to seventh transistors 105 to 107; and including eighth to fourth transistors The second input signal generating circuit 206 of ten transistors 108 to 110. The signal is supplied from the first power line 31 and the second power line 32 to the first to tenth transistors 101 to 110.

Except for the point where the output from the subsequent stage is not input, the operation of the dummy pulse signal output circuit is also similar to that of the pulse signal output circuit described in the above embodiment. Therefore, the detailed description can refer to the above-mentioned embodiment. Please note that the tenth transistor 110 is not necessarily configured. In addition, in the virtual pulse In the signal output circuit, it is necessary to ensure the output of the pulse signal output circuit ((n-1)th and nth pulse signal output circuit) at least in the normal level; therefore, the number of output terminals is not limited to two but can be one. That is, the first output terminal 26 or the second output terminal 27 may be omitted. Please note that in this situation, the transistor attached to the output terminal to be omitted can be omitted appropriately (for example, if the second output terminal 27 is omitted, the third transistor 103 and the fourth transistor 104 can be omitted).

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

[Example 4]

In this embodiment, examples of transistors that can be used in the pulse signal output circuit and shift register described in the above embodiments will be described with reference to FIGS. 10A to 10D. There is no particular restriction on the structure of the transistor. For example, a staggered type or a flat type having a top gate structure or a bottom gate structure can be used. On the other hand, the transistor may have a single gate structure in which one channel formation region is formed, or a multi-gate structure in which two or more channel formation regions are formed. On the other hand, the transistor may have a structure in which two gate electrode layers are formed above and below the channel region, and a gate insulating layer is arranged between them.

10A to 10D depict examples of the cross-sectional structure of the transistor. The transistors depicted in FIGS. 10A to 10D each include an oxide semiconductor as a semiconductor. The advantages of using oxide semiconductors are the high mobility and low off-state current that can be obtained by a simple low-temperature process.

The transistor 410 depicted in FIG. 10A is an example of a bottom gate transistor, Also known as reverse staggered transistors.

The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b disposed on a substrate 400 having an insulating surface. In addition, an insulating layer 407 contacting the oxide semiconductor layer 403 is provided. The protective insulating layer 409 is formed on the insulating layer 407.

The transistor 420 depicted in FIG. 10B is an example of a bottom gate transistor called a channel protection (channel stop) transistor, and is also called an inverted staggered transistor.

Transistor 420 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 as a channel protection layer, a source electrode layer 405a, and a drain electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, which are disposed on a substrate 400 with an insulating surface.Polar layer405b. In addition, a protective insulating layer 409 is provided.

The transistor 430 depicted in FIG. 10C is an example of a bottom gate transistor. The transistor 430 includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403 disposed on a substrate 400 having an insulating surface. In addition, an insulating layer 407 contacting the oxide semiconductor layer 403 is provided. In addition, a protective insulating layer 409 is formed on the insulating layer 407.

In the transistor 430, the gate insulating layer 402 is disposed on and in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are disposed on the gate insulating layer 402 and Contact with it. In addition, the oxide semiconductor layer 403 is disposed on the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b.

The transistor 440 depicted in FIG. 10D is an example of a top gate transistor. The transistor 440 includes an insulating layer 437, an oxide semiconductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating layer 402, and a gate electrode layer 401 disposed on the substrate 400 having an insulating surface. The wiring layer 436a and the wiring layer 436b are arranged to be in contact with the source electrode layer 405a and the drain electrode layer 405b, respectively.

In this embodiment, as described above, the oxide semiconductor layer 403 is used as a semiconductor layer. Regarding the oxide semiconductor used for the oxide semiconductor layer 403, a four-component metal oxide such as an In-Sn-Ga-Zn-O-based oxide semiconductor; a three-component metal oxide such as an In-Ga-Zn-O-based oxide can be used Semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor , Or Sn-Al-Zn-O-based oxide semiconductor; two-component metal oxides such as In-Zn-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, or In-Mg-O-based oxide semiconductor; or single-component metal oxide such as In- O-based oxide semiconductor, Sn-O-based oxide semiconductor, or Zn-O-based oxide semiconductor. In addition, SiO₂Can be added to oxide semiconductors. Here, for example, the In-Ga-Zn-O-based oxide semiconductor is an oxide including at least In, Ga, and Zn, and the composition ratio thereof is not particularly limited. In addition, the In-Ga-Zn-O-based oxide semiconductor may include elements other than In, Ga, and Zn.

For the oxide semiconductor layer 403, the chemical formula InMO₃(ZnO)_m(m&gt;0, m is not a natural number) represents the oxide semiconductivity body. Here, the M designation is selected from one or more metal elements of gallium (Ga), aluminum (Al), manganese (Mn), and cobalt (Co). For example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, and so on.

The off-state current of the transistor 410, the transistor 420, the transistor 430, and the transistor 440 including the oxide semiconductor layer 403 can be significantly reduced. Therefore, when these transistors are used in the pulse signal output circuit and the shift register, the potential of each node can be easily maintained, so that the possibility of failure of the pulse signal output circuit and the shift register can be significantly reduce.

There is no particular limitation on the substrate that can be used as the substrate 400 with an insulating surface. For example, glass substrates, quartz substrates, etc. used in liquid crystal display devices and the like can be used. On the other hand, for example, it can be used for a substrate where an insulating layer is formed on a silicon wafer.

In each of the bottom gate transistors 410, 420, and 430, an insulating layer as a base may be disposed between the substrate and the gate electrode layer. The insulating layer has the function of preventing the diffusion of impurity elements from the substrate, and can be formed to have a single layer including one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, and a silicon oxynitride film Structure or stacked structure.

The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material including any of these materials as main components. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

One selected from the group consisting of silicon oxide film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum oxynitride film, hafnium oxide film, etc. can be used Or more films, by plasma CVD, sputtering, etc. The gate insulating layer 402 is formed. For example, a gate insulating layer with a total thickness of about 300nm can be formed in this way, that is, a silicon nitride film (SiN_y(y&gt;0)) is used as the first gate insulating layer, and a silicon oxide film (SiO_x(x&gt;0)) stacked on the first gate insulating layer as the second gate insulating layer.

Metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or alloy materials including any of these materials as main components can be used to form the source electrode layer 405a and the drain The electrode layer 405b. For example, the source electrode layer 405a and the drain electrode layer 405b may have a stack structure of metal layers including aluminum, copper, etc., and refractory metal layers including titanium, molybdenum, and tungsten. The use of aluminum materials that add elements that avoid bumps and whiskers (for example, silicon, neodymium, or scandium) can improve heat resistance.

On the other hand, a conductive metal oxide film can be used as a conductive film for the source electrode layer 405a and the drain electrode layer 405b (including a wiring layer formed from the same layer as the source electrode layer 405a and the drain electrode layer 405b). Indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂O₃-SnO₂, Sometimes abbreviated as ITO), indium oxide-zinc oxide alloy (In₂O₃-ZnO), any of these metal oxide materials including silicon oxide, etc., as conductive metal oxides.

Using materials similar to the source electrode layer 405a and the drain electrode layer 405b, the wiring layer 436a and the wiring layer 436b that contact the source electrode layer 405a and the drain electrode layer 405b, respectively, can be formed.

For each of the insulating layers 407, 427, and 437, typically An inorganic insulating film, such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, is used.

For the protective insulating layer 409, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film can be used.

In addition, a planarization insulating film for reducing surface unevenness caused by transistors can be formed on the protective insulating layer 409. For the planarization insulating film, organic materials such as polyimide, acrylic, or benzocyclobutene can be used. For substitutes for these organic materials, low-dielectric constant materials (low-k materials), etc. can be used. Please note that a planarization insulating film can be formed by stacking a plurality of insulating films including these materials.

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

[Example 5]

In this embodiment, an example of a transistor including an oxide semiconductor layer and an example of its manufacturing method will be described in detail with reference to FIGS. 11A to 11E.

11A to 11E are cross-sectional views depicting the manufacturing process of the transistor. The transistor 510 depicted here is an inverted staggered transistor similar to the transistor 410 depicted in FIG. 10A.

The oxide semiconductor used in this embodiment is an i-type (intrinsic) oxide semiconductor or a substantially i-type (intrinsic) oxide semiconductor. i-type (intrinsic) oxide semiconductors or substantially i-type (intrinsic) oxide semiconductors are obtained by removing hydrogen as n-type impurities from the oxide semiconductor and purifying the oxide semiconductor so as to contain as little as possible Oxide semiconductor The main component of impurities.

Please note that the purified oxide semiconductor includes very few carriers, and the carrier concentration is less than 1×10¹⁴/cm³, Preferably less than 1×10^12/cm³, Further preferably less than 1×10¹¹/cm³. These few carriers make the current in the off state (off state current) sufficiently small.

Specifically, in a transistor including the above-mentioned oxide semiconductor layer, when the channel length L of the transistor is 10μm and the source-drain voltage is 3V at room temperature (25°C), the channel width is closed per 1μm The state current density can be 100zA/μm (1×10^-19A/μm) or lower, or further 10zA/μm (1×10^-20A/μm) or lower.

The transistor 510 including the purified oxide semiconductor layer has almost no temperature dependence of the on-state current, and also has a very small off-state current.

The manufacturing process of the transistor 510 on the substrate 505 will be described with reference to FIGS. 11A to 11E.

First, a conductive film is formed on the substrate 505 with an insulating surface, and then the gate electrode layer 511 is formed through a first photolithography process. Please note that the resist mask used in the photolithography process can be formed by the inkjet method. The resist mask formed by the inkjet method does not require a photomask; therefore, the manufacturing cost can be reduced.

Regarding the substrate 505 with an insulating surface, a substrate similar to the substrate 400 described in the above embodiment can be used. In this embodiment, a glass substrate is used as the substrate 505.

The insulating layer as a base can be disposed between the substrate 505 and the gate electrode layer 511. The insulating layer has the function of preventing the diffusion of impurity elements from the substrate 505, and can be selected from silicon nitride film, silicon oxide film, silicon oxynitride film, oxygen nitrogen One or more films such as a silicide film are formed.

The gate electrode layer 511 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material including any of these metal materials as a main component. The gate electrode layer 511 may have a single-layer structure or a stacked structure.

Secondly, the gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 can be formed by a plasma CVD method, a sputtering method, or the like. Can be selected from one of silicon oxide film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum oxynitride film, hafnium oxide film, etc. More films form the gate insulating layer 507.

In addition, in order to make the gate insulating layer 507 and the oxide semiconductor film 530 contain as little hydrogen, hydrocarbon groups and moisture as possible, it is preferable to preheat in the preheating chamber of the sputtering equipment to form a gate electrode layer thereon. The substrate 505 of 511 or the substrate 505 on which the gate electrode layer 511 and the gate insulating layer 507 are formed is used as a pretreatment for forming the oxide semiconductor film 530 so as to remove impurities such as hydrogen and moisture adsorbed on the substrate 505. Regarding the evacuation unit, the cryopump is preferably arranged in the preheating chamber. This preheating step can be performed on the substrate 505 formed thereon up to the layer including the source electrode layer 515a and the drain electrode layer 515b. Please note that this pre-heat treatment can be omitted.

Secondly, on the gate insulating layer 507, an oxide semiconductor film 530 with a thickness greater than or equal to 2 nm and less than or equal to 200 nm is formed, preferably greater than or equal to 5 nm and less than or equal to 30 nm (detailed in FIG. 11A).

For the oxide semiconductor film 530, the above-mentioned embodiment can be used Any four-component metal oxide, three-component metal oxide, two-component metal oxide, In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn-O-based oxide semiconductor, etc. are described.

Regarding the target material used to form the oxide semiconductor film 530 by the sputtering method, it is preferable to use In:Ga:Zn=1:x:y (x is greater than or equal to 0, and y is greater than or equal to 0.5 and Target material with a composition ratio less than or equal to 5). For example, you can use In₂O₃: Ga₂O₃: ZnO=1:1:2 [molar ratio] target material. On the other hand, you can use In₂O₃: Ga₂O₃:ZnO=1:1:1[molar ratio] target material with In₂O₃: Ga₂O₃:ZnO=1:1:4 (molar ratio) target material with composition ratio, or with In₂O₃: Ga₂O₃: ZnO=1:0:2 [molar ratio] the target material of the composition ratio.

In this embodiment, an oxide semiconductor layer with an amorphous structure is formed by a sputtering method and using an In-Ga-Zn-O-based metal oxide target.

The relative density of the metal oxide in the metal oxide target is greater than or equal to 80%, preferably greater than or equal to 95%, and further preferably greater than or equal to 99.9%. Using a metal oxide target with a high relative density makes it possible to form an oxide semiconductor layer with a dense structure.

The gas for forming the oxide semiconductor film 530 is preferably a rare gas (typically argon), oxygen, or a mixed gas containing a rare gas (typically argon) and oxygen. Specifically, it is preferable to use a high-purity gas for removing impurities such as hydrogen, water, hydroxyl, or hydride, so that the impurity concentration is 1 ppm or lower (preferably 10 ppb or lower).

In forming the oxide semiconductor film 530, for example, the processing target is held at In the processing chamber maintained under reduced pressure, the processing target is heated so that the temperature of the processing target is higher than or equal to 100°C and lower than 550°C, preferably higher than or equal to 200°C and lower than or equal to 400°C. On the other hand, the temperature of the processing target in the formation of the oxide semiconductor film 530 may be room temperature (25° C.±10° C. (higher than or equal to 15° C. and lower than or equal to 35° C.)). Then, a sputtering gas for removing hydrogen, water, etc. is introduced, and moisture in the processing chamber is removed at the same time, and the above-mentioned target material is used, thereby forming an oxide semiconductor film 530. The oxide semiconductor film 530 is formed while heating the treatment target so that impurities contained in the oxide semiconductor layer can be reduced. In addition, damage due to sputtering can be reduced. To remove moisture in the processing chamber, a trapped vacuum pump is preferably used. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. can be used. On the other hand, a turbo pump equipped with a cold trap can be used. By evacuating with a cryopump or the like to remove hydrogen, water, etc. from the processing chamber, the impurity concentration in the oxide semiconductor film 530 can be reduced.

The oxide semiconductor film 530 can be formed under the following conditions, for example: the distance between the processing target and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the gas is oxygen (the ratio of oxygen is 100 %), argon (the proportion of argon is 100%), or a mixed gas including oxygen and argon. It is preferable to use a pulsed direct current (DC) power supply because the powdery substance (also called particles or dust) generated during film formation can be reduced, and the film thickness can be uniform. The thickness of the oxide semiconductor film 530 is greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 1 nm and less than or equal to 30 nm, more preferably greater than or equal to 1 nm and less than or equal to 10 nm. Based on the oxide semiconductor film 530 having the same thickness, the short channel effect caused by miniaturization can be suppressed. Please note that the appropriate thickness will follow The oxide semiconductor material used, the intended use of the semiconductor device, etc. vary; therefore, the thickness can be determined according to the material, the intended use, etc.

Please note that before forming the oxide semiconductor film 530 by the sputtering method, it is preferable to remove the adhesion on the surface where the oxide semiconductor film 530 will be formed by introducing argon gas and generating plasma by reverse sputtering ( For example, the surface of the gate insulating layer 507). Here, reverse sputtering is a method, compared to normal sputtering where the ion system collides with the sputtering target, in which the ion system collides with the processing surface, so that the surface is modified. Regarding an example of a method of causing ions to collide with the processing surface, there is a method in which a high-frequency voltage is applied to the processing surface in argon gas, so that plasma is generated near the processing target. Please note that in addition to argon, nitrogen, helium, oxygen and other gases can be used.

Next, the oxide semiconductor film 530 is processed into an island-shaped oxide semiconductor layer through a second photolithography process. Please note that the resist mask used in the photolithography process can be formed by an inkjet method. The resist mask formed by the inkjet method does not require a photomask; therefore, the manufacturing cost can be reduced.

If a contact hole is formed in the gate insulating layer 507, the step of forming the contact hole can be performed while the oxide semiconductor film 530 is processed.

Regarding the etching of the oxide semiconductor film 530, wet etching or dry etching or both of them can be used. Regarding the etchant used for wet etching of the oxide semiconductor film 530, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, or the like can be used. ITO-07N (manufactured by KANTO CHEMICAL CO., INC.) can also be used.

Next, heat treatment (first heat treatment) is performed on the oxide semiconductor layer, so that an oxide semiconductor layer 531 is formed (detailed FIG. 11B). By The first heat treatment removes excessive hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer, and improves the structure of the oxide semiconductor layer, so that the degree of defects in the energy gap can be reduced. For example, the temperature of the first heat treatment is higher than or equal to 300°C and lower than 550°C, or higher than or equal to 400°C and lower than or equal to 500°C.

For example, the heat treatment can be performed in this manner, that is, the treatment target is introduced into an electric melting furnace using a resistance heating element, etc., and heated in nitrogen at 450° C. for one hour. During the heat treatment, the oxide semiconductor layer is not exposed to air to prevent water and hydrogen from entering.

The heat treatment equipment is not limited to an electric melting furnace; the heat treatment equipment may be an equipment that heats the treatment target using heat conduction or heat radiation from a medium such as heating gas. For example, rapid thermal annealing (RTA) equipment such as lamp rapid thermal annealing (LRTA) equipment or gas rapid thermal annealing (GRTA) equipment may be used. The LRTA device is a device that uses radiation (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, or high pressure mercury lamps to heat treatment targets. GRTA equipment is equipment used to perform heat treatment using high-temperature gas. Regarding the gas, an inert gas that does not react with the treatment target by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, regarding the first heat treatment, GRTA can be performed in the following manner. The processing target is placed in heated inert gas, heated for several minutes, and then removed from the inert gas. GRTA treatment can implement high temperature heat treatment in a short time. Furthermore, even in situations where the temperature exceeds the upper limit of the treatment target temperature, GRTA treatment can be used. Please note that the inert gas can be switched during processing It is a gas including oxygen. This is because by performing the first heat treatment in a gas including oxygen, the degree of defects in the energy gap caused by lack of oxygen can be reduced.

Please note that for inert gas, it is preferable to use a gas that contains nitrogen or a rare gas (such as helium, neon, or argon) as its main component and does not contain water, hydrogen, etc. For example, the purity of nitrogen or rare gas such as helium, neon or argon introduced into the heat treatment equipment is set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1ppm or Lower, preferably 0.1 ppm or lower).

In any case, impurities are reduced by the first heat treatment to obtain an i-type (intrinsic) or substantially i-type oxide semiconductor layer. Therefore, a transistor with remarkably excellent characteristics can be embodied.

The above heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., so it can be called dehydration treatment, dehydrogenation treatment, and the like. The dehydration treatment or dehydrogenation treatment may be performed after the oxide semiconductor film 530 is formed and before the oxide semiconductor film 530 is processed into an island-shaped oxide semiconductor layer. The dehydration treatment or dehydrogenation treatment can be performed once or several times.

In addition to the above timing, the first heat treatment may be performed at any of the following timings: after the source electrode layer and the drain electrode layer are formed, after the insulating layer is formed on the source electrode layer and the drain electrode layer, and so on.

Next, a conductive film that becomes the source electrode layer and the drain electrode layer (including wiring formed from the same layer as the source electrode layer and the drain electrode layer) is formed between the gate insulating layer 507 and the oxide semiconductor layer 531 superior. The conductive film used to form the source electrode layer and the drain electrode layer can be formed using any of the materials described in the above embodiments.

In the third photolithography process, a resist mask is formed on the conductive film, and the source electrode layer 515a and the drain electrode layer 515b are formed by selective etching, and then the resist mask is removed (detailed in FIG. 11C).

UV light, KrF laser light or ArF laser light can be used to perform the exposure during the formation of the resist mask in the third photolithography step. Please note that the channel length (L) of the transistor is determined by the distance between the source electrode layer and the drain electrode layer. Therefore, it is preferable to use extreme ultraviolet light whose wavelength is as short as a few nanometers to several tens of nanometers for the exposure for forming a resist mask for transistors with a channel length (L) less than 25nm. In the exposure using extreme ultraviolet light, the resolution is high and the depth of focus is large. For this reason, the channel length (L) of the transistor to be completed later can be greater than or equal to 10 nm and less than or equal to 1000 nm, and the circuit operates at high speed. Furthermore, the power consumption of the semiconductor device can be reduced by miniaturization.

In order to reduce the number of photomasks and the number of photolithography processes, a resist mask formed with a multi-tone mask can be used to perform the etching step. Since the resist mask formed by using the multi-tone mask includes areas of multiple thicknesses and can be further changed in shape by performing etching, the resist mask can be used in multiple etching steps to provide different patterns. Therefore, a multi-tone mask can be used to form resist masks corresponding to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the number of corresponding photolithography procedures can be reduced, thereby simplifying the manufacturing process.

Please note that it is preferable to optimize the etching conditions so that the oxide semiconductor layer 531 is not etched and divided when the conductive film is etched. However, it is difficult to obtain an etching condition in which only the conductive film is etched and the oxide semiconductor layer 531 is not etched at all. Sometimes, when the conductive film is etched, part of the oxide semiconductor layer 531 It is etched, thereby forming an oxide semiconductor layer 531 having grooves (recesses).

Wet etching or dry etching can be used to etch the conductive film. Please note that dry etching is preferably used in terms of device miniaturization. The etching gas and etchant can be appropriately selected according to the material to be etched. In this embodiment, the titanium film is used as the conductive film and the In-Ga-Zn-O-based material is used for the oxide semiconductor layer 531; therefore, if wet etching is used, an ammonium hydrogen peroxide solution (31% by weight hydrogen peroxide Solution: 28% by weight ammonia: water = 5: 2: 2) It can be used as an etchant.

Secondly, use such as nitrous oxide (N₂O), nitrogen (N₂) Or argon (Ar) gas is preferably performed plasma treatment, so that water adsorbed on the exposed surface of the oxide semiconductor layer can be removed. If the plasma treatment is performed, the insulating layer 516 as a protective insulating film is formed after the plasma treatment without being exposed to the air.

By a method, such as a sputtering method, the insulating layer 516 is preferably formed to a thickness of at least 1 nm, so that impurities such as water or hydrogen are not introduced into the insulating layer 516. When hydrogen is contained in the insulating layer 516, the hydrogen enters the oxide semiconductor layer, or the oxygen in the oxide semiconductor layer is extracted by hydrogen, thereby causing the back channel of the oxide semiconductor layer to have lower resistance (with n-type Conductivity), so that parasitic channels are formed. Regarding the insulating layer 516, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is preferably used.

In this embodiment, a silicon oxide film with a thickness of 200 nm is formed as the insulating layer 516 by sputtering. The temperature of the substrate during deposition can be higher than or equal to room temperature (25°C) and lower than or equal to 300°C, in this embodiment it is 100 °C. The silicon oxide film can be deposited in a rare gas (typically argon), oxygen, or a mixed gas containing rare gas and oxygen by sputtering. Regarding the target material, a silicon oxide target material or a silicon target material can be used.

In order to remove the remaining moisture in the deposition chamber of the insulating layer 516 while the oxide semiconductor film 530 is being deposited, a trapped vacuum pump (such as a cryopump) is preferably used. When the insulating layer 516 is deposited in a deposition chamber evacuated using a cryopump, the impurity concentration in the insulating layer 516 can be reduced. The turbo pump equipped with a cold trap can be used as an evacuation unit to remove the remaining moisture in the deposition chamber for forming the insulating layer 516.

The sputtering gas used to form the insulating layer 516 is preferably a high-purity gas from which impurities such as hydrogen or water are removed.

Secondly, a second heat treatment is performed in an inert gas or oxygen. The second heat treatment is performed at a temperature higher than or equal to 200°C and lower than or equal to 450°C, preferably higher than or equal to 250°C and lower than or equal to 350°C. For example, heat treatment can be performed at 250°C for one hour in nitrogen. The second heat treatment can reduce changes in the electrical characteristics of the transistor. By supplying oxygen to the oxide semiconductor layer 531 from the insulating layer 516, oxygen deficiency in the oxide semiconductor layer 531 is reduced, thereby forming an i-type (intrinsic) or substantially i-type oxide semiconductor layer.

In this embodiment, the second heat treatment is performed after the insulating layer 516 is formed; however, the timing of the second heat treatment is not limited to this. For example, the first heat treatment and the second heat treatment may be performed sequentially, or the first heat treatment may also serve as the second heat treatment.

In the above manner, through the first heat treatment and the second heat treatment, the oxide The semiconductor layer 531 is purified so as to contain as few impurities as possible that are not the main components of the oxide semiconductor layer, whereby the oxide semiconductor layer 531 can become an i-type (intrinsic) oxide semiconductor layer.

Through the above procedure, a transistor 510 is formed (detailed in FIG. 11D).

Preferably, a protective insulating layer 506 is further formed on the insulating layer 516 (detailed in FIG. 11E). The protective insulating layer 506 prevents hydrogen, water, etc. from entering from the outside. Regarding the protective insulating layer 506, for example, a silicon nitride film, an aluminum nitride film, or the like can be used. The method of forming the protective insulating layer 506 is not particularly limited; however, the RF sputtering method is suitable for forming the protective insulating layer 506 because of its high yield.

After the protective insulating layer 506 is formed, the heat treatment may be further performed in the air at a temperature higher than or equal to 100° C. and lower than or equal to 200° C. for 1 hour to 30 hours.

The transistor including the purified oxide semiconductor layer and the transistor manufactured according to the above-mentioned embodiment has the characteristic of significantly small off-state current. Therefore, by using this transistor, the potential of the node can be easily maintained. Using these transistors in the pulse signal output circuit and the shift register can significantly reduce the possibility of causing the pulse signal output circuit and the shift register to malfunction.

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

[Example 6]

Using the shift register of the example described in any one of Embodiments 1 to 3, a semiconductor device with a display function (also referred to as a display device) can be manufactured. In addition, part or all of the driver can be formed on the same substrate as the pixel portion. Drive the circuit to obtain a system on the panel.

Regarding the display element used in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. Light-emitting elements include elements whose brightness is controlled by current or voltage according to their classification, and specifically include inorganic electroluminescence (EL) elements, organic EL elements, and the like according to their classification. In addition, display media can be used, the contrast of which is changed by electrical effects, such as electronic ink.

In FIG. 12A, the sealant 4005 is disposed so as to surround the pixel portion 4002 disposed on the first substrate 4001, and the pixel portion 4002 is sealed between the first substrate 4001 and the second substrate 4006. In FIG. 12A, the scanning line driving circuit 4004 and the signal line driving circuit 4003 formed on the separately prepared substrates are mounted on the first substrate 4001 in an area different from the area surrounded by the sealant 4005. In addition, various signals and potentials are supplied to the channel formed signal line driver circuit 4003, and from the flexible printed circuit (FPC) 4018a and 4018b of the scan line driver circuit 4004 or the pixel portion 4002.

In FIGS. 12B and 12C, the sealant 4005 is arranged so as to surround the pixel portion 4002 and the scan line driving circuit 4004 arranged on the first substrate 4001. The second substrate 4006 is disposed on the pixel portion 4002 and the scan line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006. In FIGS. 12B and 12C, the signal line driving circuit 4003 formed on the separately prepared substrate is mounted on the first substrate 4001 in a region different from the region surrounded by the sealant 4005. In Figures 12B and 12C, various signals and potentials are supplied to the separately formed The signal line driving circuit 4003, and the scanning line driving circuit 4004 or the pixel portion 4002 from the FPC 4018.

Although FIGS. 12B and 12C each depict an example in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, the present invention is not limited to this structure. The scan line driver circuits may be separately formed and then installed, or only part of the signal line driver circuits or part of the scan line driver circuits may be separately formed and then installed.

Please note that the connection method of the separately formed drive circuits is not particularly limited, and the chip mounted on glass (COG) method, wire bonding method, tape automatic bonding (TAB) method, etc. can be used. FIG. 12A depicts an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are installed by the COG method. FIG. 12B depicts an example in which the signal line driving circuit 4003 is installed by the COG method. FIG. 12C depicts an example in which the signal line driving circuit 4003 is installed by the TAB method.

In addition, the display device includes a panel in which the display element is sealed, and modules such as ICs including the controller are mounted on the panel.

Please note that the display device in this specification refers to an image display device, a display device, or a light source (including a light-emitting device). In addition, the display device also includes the following modules according to its classification: modules with connectors such as FPC, TAB tape, or TCP; modules with TAB tape or TCP with printed wiring boards at the end; and integrated circuits ( IC) A module directly mounted on the display element by the COG method.

In addition, the pixel portion disposed on the first substrate includes a plurality of transistors, and the transistors described in the above-mentioned embodiments are used as a range of the transistors. example.

If the liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. are used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, etc. depending on the situation.

On the other hand, it is possible to use liquid crystal exhibiting blue phase that does not require a calibration film. The blue phase is a liquid crystal phase that occurs shortly before the cholesterol phase changes to an isotropic phase and the temperature of the cholesterol liquid crystal increases. Since the blue phase is only generated in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition containing 5 wt% or more of a chiral agent is used for the liquid crystal layer. The liquid crystal composition including the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of 1 millisecond or less, is optically isotropic, does not require calibration processing, and has a small viewing angle dependence. In addition, there is no need to configure a calibration film, so no grinding treatment is required. Therefore, the electrostatic discharge damage caused by the grinding process can be avoided, and the defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Therefore, the productivity of the liquid crystal display device can be improved.

The specific resistivity of the liquid crystal material is greater than or equal to 1×10⁹Ω. cm, preferably greater than or equal to 1×10¹¹Ω. cm, preferably greater than or equal to 1×10¹²Ω. Cm. Please note that the specific resistance in this manual is measured at 20°C.

Considering the leakage current of the transistors arranged in the pixel portion, etc., the size of the storage capacitor formed in the liquid crystal display device is set so that the charge can be maintained for a predetermined period. The size of the storage capacitor can be set in consideration of the off-state current of the transistor.

For liquid crystal display devices, use twisted nematic (TN) mode, in-plane direction switching (IPS) mode, fringe field switching (FFS) mode, axisymmetric array micro grid (ASM) mode, optical compensation birefringence (OCB) mode , Ferroelectric liquid crystal (FLC) mode, anti-electric liquid crystal (AFLC) mode, etc.

Normally black liquid crystal panels are preferred, such as transmissive liquid crystal display devices using vertical adjustment (VA) mode. VA liquid crystal display devices come in various forms, in which the adjustment of the liquid crystal molecules of the liquid crystal display panel is controlled. In the VA liquid crystal display device, when no voltage is applied, the liquid crystal molecules are aligned in the vertical direction relative to the surface of the panel. Provide some examples of vertical adjustment modes. For example, a multi-area vertical arrangement (MVA) mode, a picture vertical adjustment (PVA) mode, an ASV mode, etc. can be used. Furthermore, a method called domain multiplication or multi-domain design can be used, in which pixels are divided into regions (sub-pixels), and molecules are aligned in different directions in each region.

In the display device, a black matrix (light blocking layer), an optical member (optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, etc. are appropriately arranged. For example, circular polarization can be obtained by using a polarizing substrate and a retarded substrate. In addition, backlights, side lights, etc. can be used as light sources.

Regarding the display method in the pixel portion, a forward method, an interlace method, etc. can be used. In addition, the color components controlled in the pixel during color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, R, G, B, and W (W corresponds to white); R, G, B, and one or more colors of yellow, cyan, magenta, etc. can be used. In addition, the size of the display area between the dots of each color component may be different. Please note It is understood that the embodiments of the disclosed invention are not limited to be applied to color display devices; the disclosed invention can also be applied to monochrome display devices.

On the other hand, regarding the display elements included in the display device, a light-emitting element using electroluminescence can be used. Light-emitting devices using electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In an organic EL device, by applying a voltage to the light-emitting device, electrons and holes are respectively injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) recombine, and the light-emitting organic compound is excited. The light-emitting organic compound returns to the grounded state from the excited state, thereby emitting light. Because of these mechanisms, light-emitting elements are called current-excited light-emitting elements.

Inorganic EL elements can be divided into dispersion-type inorganic EL elements and thin-film inorganic EL elements according to their element structure. The dispersed inorganic EL device has a light-emitting layer in which particles of the light-emitting material are dispersed in a binder, and its light-emitting mechanism is the recombination of donor-acceptor light using the donor level and the acceptor level. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further between electrodes, and its light-emitting mechanism is localized light-emitting using metal ion electron transitions in the inner shell.

In addition, the electronic paper in which the electronic ink is driven can be configured as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), which has advantages in that it has the same degree of readability as ordinary paper, has lower power consumption than other display devices, and can be set to have a thin and light type.

The electrophoretic display device may have various modes. The electrophoretic display device includes a plurality of microcapsules distributed in a solvent or a solute. Each microcapsule includes a positively charged first particle and a negatively charged second particle. By applying an electric field to the microcapsule, the particles in the microcapsule move in opposite directions to each other, and only the color of the particles gathered on one side is displayed. Please note that the first particle and the second particle each contain a pigment and do not move when there is no electric field. Furthermore, the first particles and the second particles have different colors (may be colorless).

Therefore, an electrophoretic display device is a display device that utilizes the so-called double electrophoresis effect, whereby a substance with a high dielectric constant moves to a high electric field region.

The solution in which the above-mentioned microcapsules are distributed in a solvent is called electronic ink. Electronic ink can be printed on glass, plastic, cloth, paper and other surfaces. In addition, color display can also be achieved by using color filters or particles with pigments.

Please note that the first particles and the second particles in the microcapsules can each be formed of a single material, such as selected from conductive materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, and electrochromic Materials, or magnetophoretic materials, or composite materials using any of these materials.

For electronic paper, the display device of the twist ball display system can be used. The twisted ball display system refers to a method in which spherical particles are each colored in black and white and arranged between the first electrode layer and the second electrode layer of the electrode layer of the display element, the first electrode layer and the second electrode layer A potential difference is generated between them to control the alignment of the spherical particles, so that the display is performed.

The pulse signal output circuit described in Embodiment 1 or Embodiment 2 is used in the display device of the above example, so that the display device can have various functions.

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

[Example 7]

The semiconductor device disclosed in this specification can be used in various electronic devices (including game consoles). Examples of electronic devices are televisions (also known as TVs or TV receivers), computer screens, cameras such as digital cameras or digital cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), Portable game consoles, personal digital assistants, audio reproduction devices, large game consoles such as pinballs, etc.

FIG. 13A depicts a laptop personal computer including at least the semiconductor device disclosed in this specification as components. The laptop personal computer includes a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like.

FIG. 13B depicts a personal digital assistant (PDA), which includes at least the semiconductor device disclosed in this specification as a component. The main body 3021 is configured to have a display portion 3023, an external interface 3025, operation buttons 3024, and the like. Including the stylus 3022 as a work accessory.

The semiconductor device disclosed in this specification can be used as electronic paper. Figure 13C depicts an e-book reader, which includes e-paper as a component. Figure 13C depicts an example of an e-book reader. For example, the e-book reader 2700 includes two housings 2701 and 2703. The housings 2701 and 2703 are combined with each other with a hinge 2711, so that the e-book reader 2700 can be opened and closed with the hinge 2711 as a shaft. Based on these structures, the e-book reader 2700 can operate like a paper book.

The display portion 2705 and the display portion 2707 are incorporated into the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 can display one image or different images. If the display portion 2705 and the display portion 2707 display different images, for example, the right display portion (display portion 2705 in FIG. 13C) can display text, and the left display portion (display portion 2707 in FIG. 13C) can display images.

FIG. 13C depicts an example in which the housing 2701 includes a working part and the like. For example, the housing 2701 includes a power switch 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned based on the operation key 2723. Please note that the keyboard, pointing device, etc. can be arranged on the same surface as the display portion of the housing. In addition, external connection terminals (for example, earphone terminals or USB terminals), recording medium embedding parts, etc. may be arranged on the back or side of the housing. In addition, the e-book reader 2700 can be used as an electronic dictionary.

In addition, the e-book reader 2700 can transmit and receive data wirelessly. Through wireless communication, you can purchase and download desired book information from the e-book server.

FIG. 13D depicts a mobile phone, which includes at least the semiconductor device disclosed in this specification as a component. The mobile phone includes two shells 2800 and 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like. In addition, the housing 2800 includes a solar cell 2810 for storing power in a personal digital assistant, an external memory slot 2811, and the like. In addition, the antenna is incorporated into the housing 2801.

In addition, the display panel 2802 includes a touch panel. The plural operation keys 2805 displayed as images are indicated by the dashed line in FIG. 13D. Please note that action The phone includes a booster circuit to boost the voltage output from the solar cell 2810 to the voltage required by each circuit.

The display direction of the display panel 2802 is appropriately changed according to the usage type. In addition, since the mobile phone includes the camera lens 2807 on the same surface as the display panel 2802, it can be used as a video phone. The speaker 2803 and the microphone 2804 can be used for video phone calls, recording, playback, etc., as well as voice calls. In addition, the housings 2800 and 2801 are developed as depicted in FIG. 13D, and can overlap each other by sliding; therefore, the size of the mobile phone can be reduced, making the mobile phone suitable for portability.

The external connection terminal 2808 can be connected to an AC adapter and various USB cables such as a cable, and can charge a personal computer and communicate with it. In addition, by embedding the storage medium into the external memory slot 2811, a large amount of data can be stored and moved.

In addition, in addition to the above-mentioned functions, mobile phones may have infrared communication functions, TV reception functions, and so on.

FIG. 13E depicts a digital camera, which includes at least the semiconductor device disclosed in this specification as a component. The digital camera includes a main body 3051, a first display portion 3057, an eyepiece portion 3053, an operation switch 3054, a second display portion 3055, a battery 3056, and the like.

FIG. 13F depicts an example of a television, which includes at least the semiconductor device disclosed in this specification as a component. In the television 9600, the display portion 9603 is incorporated into the housing 9601. The display portion 9603 can display images. Here, the housing 9601 is supported by the bracket 9605.

The TV 9600 can be controlled by the operation switch of the housing 9601 or the remote control To operate. In addition, the remote controller may include a display unit to display the data output from the remote controller.

Please note that the TV 9600 includes a receiver, modem, etc. Based on this receiver, general TV broadcasts can be received. In addition, when the TV is wired or wirelessly connected to a communication network via a modem, it can perform one-way (from transmitter to receiver) or two-way (between transmitter and receiver or between receivers) data communication.

The structure, method, etc. described in this embodiment can be appropriately combined with any structure, method, etc. described in other embodiments.

This application is based on the Japanese Patent Application No. 2010-045884 filed with the Japan Patent Office on March 2, 2010, the entire content of which is incorporated herein by reference.