Pulse signal output circuit and shift register

The disclosed invention relates to a pulse signal output circuit and a shift register.

Transience formed on a flat plate such as a glass substrate, as used in liquid crystal display devices, etc. Stars are mainly made from semiconductor materials such as amorphous silicon or polycrystalline silicon. Is done. Transistors using amorphous silicon have low field-effect mobility, but they are loose. It is possible to cope with a large area of the substrate. On the other hand, transistors using polycrystalline silicon Although it has high field-effect mobility, it requires a crystallization process such as laser annealing, and glass. It has the characteristic that it is not always suitable for increasing the area of the substrate.

On the other hand, transistors using oxide semiconductors as semiconductor materials are attracting attention. Example For example, a tiger using zinc oxide or an In-Ga-Zn-O oxide semiconductor as a semiconductor material. Patent Document 1 and a technique for producing an engineer and using it as a switching element of an image display device are described in Patent Document 1. It is disclosed in Patent Document 2.

Amorphous silicon is used for the transistor using the oxide semiconductor in the channel formation region. Higher field-effect mobility is obtained than the transistor. In addition, the oxide semiconductor film is It is possible to form a film at a temperature of 300 ° C or less by the putter method, etc., and polycrystalline silicon is used. It is easier to manufacture than the existing transistor.

Transistors manufactured using such oxide semiconductors are liquid crystal displays and electrics. Pixel part and drive circuit of display device such as trolley luminescence display or electronic paper It is expected to be applied to the constituent switching elements. For example, the above oxide half The pixel part of the display device and the drive circuit are composed of transistors manufactured using conductors. The technique is disclosed in Non-Patent Document 1.

However, all transistors manufactured using the above oxide semiconductors are n-channel transistors. It is an engineer. Therefore, the drive times are driven by using a transistor manufactured using an oxide semiconductor. When forming a path, the drive circuit is composed of only n-channel transistors. It will be.

<p><patcit num="1"><text>JP-A-2007-123861</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2007-96055</text></patcit></p>

<p><nplcit num="1"><text>T.Osada, 8 others, "Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT", SID '09 DIGEST, pp.184-187 (2009)</text></nplcit></p>

<p>The drive circuit used for the display device, etc. is a shift register including a pulse signal output circuit. It is composed of. If the shift register is composed of unipolar transistors, Problems such as unstable operation may occur.</p><p>In view of the above problems, one aspect of the present invention is a pulse signal output times capable of stable operation. One of the tasks is to provide a road and a shift register including the road.</p>

<p>One aspect of the present invention comprises first to tenth transistors, the first of which is a first transistor. The terminal, the first terminal of the second transistor, and the first output terminal are electrically connected, The first terminal of the third transistor, the first terminal of the fourth transistor, and the second output terminal The child is electrically connected, and the first terminal of the fifth transistor and the sixth transistor The first terminal and the first terminal of the seventh transistor are electrically connected, and the first transistor is connected. The gate terminal of the Gista, the gate terminal of the third transistor, and the second of the seventh transistor Is electrically connected to the terminal of the second transistor, and the gate terminal of the second transistor and the fourth transistor. Gate terminal, gate terminal of the 6th transistor, and 1st end of the 8th transistor The child and the first terminal of the ninth transistor are electrically connected and of the eighth transistor. The second terminal and the first terminal of the tenth transistor are electrically connected, and the first transistor The ratio W / L of the channel width W to the channel length L of the transistor and the third transistor is The ratio of the channel width W to the channel length L of the sixth transistor W / L is larger than the ratio W / L, and the fifth The ratio W / L of the channel width W to the channel length L of the transistor is the sixth transistor. The ratio of the channel width W to the channel length L of W / L is larger than the ratio W / L of the fifth transistor. The ratio W / L of the channel width W to the channel length L is relative to the channel length L of the seventh transistor. The ratio of the channel width W to be W / L is equal to the ratio W / L of the channel length W of the third transistor. The ratio W / L of the flannel width W is the ratio W of the channel width W to the channel length L of the fourth transistor. It is a pulse signal output circuit larger than / L.</p><p>In the above pulse signal output circuit, the second terminal of the first transistor and the third transistor The first clock signal is input to the second terminal of the Langista, and the second transistor is connected to the eighth transistor. The second clock signal is input to the input terminal, and the gate terminal of the tenth transistor is , The third clock signal is input, the second terminal of the second transistor, the fourth transistor The second terminal of the data, the second terminal of the sixth transistor, and the second terminal of the ninth transistor The terminal is given a first potential, the second terminal of the fifth transistor, the seventh transistor. The gate terminal of the data and the second terminal of the tenth transistor have a higher potential than the first potential. Given a potential of 2, the gate terminal of the 5th transistor and the game of the 9th transistor The first pulse signal is input to the input terminal, and from the first output terminal or the second output terminal, A second pulse signal may be output.</p><p>Further, it has a capacitive element, and the capacitive element has a gate terminal of a second transistor and a fourth transistor. The gate terminal of the Gista, the gate terminal of the 6th transistor, and the 1st of the 8th transistor It may be electrically connected to the terminal of the 9th transistor and the 1st terminal of the 9th transistor.</p><p>In the above, the eleventh transistor is provided, and the first terminal of the eleventh transistor is the first terminal. The gate terminal of the 2nd transistor, the gate terminal of the 4th transistor, and the 6th transition The gate terminal of the star, the first terminal of the eighth transistor, and the first terminal of the ninth transistor Electrically connected to the terminal, the second terminal of the eleventh transistor is the eighth transistor Electrically connected to the second terminal of the data, the first terminal of the ninth transistor, and the capacitive element. The channel width W of the 8th transistor and the 10th transistor is the 11th transition. It may be smaller than the channel width W of the star.</p><p>Further, in the above pulse signal output circuit, the second terminal of the eleventh transistor has a second terminal. A potential of 2 is given, and a third pulse signal is input to the gate terminal of the 11th transistor. May be</p><p>Further, a shift register can be configured by using a plurality of the above pulse signal output circuits. More specifically, for example, 2 pulse signal output circuits having no 11th transistor are used. It has n (n: natural numbers) pulse signal output circuits having the 11th transistor. A pulse signal output circuit that is an n-stage shift register and does not have an eleventh transistor. The channel width W of the 8th transistor or the 10th transistor is the 11th transistor. The cha of the 8th transistor or the 10th transistor of the pulse signal output circuit having a data. The configuration may be larger than the flannel width W.</p><p>In addition, a plurality of transistors constituting the above-mentioned pulse signal output circuit or shift register It is preferable to use an oxide semiconductor as either of them. Also, the above pulse signal output circuit A plurality of shift registers can be used to form a shift register.</p><p>In the above, a transistor may be configured using an oxide semiconductor, but it is disclosed. The invention to be made is not limited to this. A material that can achieve off-current characteristics equivalent to those of oxide semiconductors, For example, wide-gap materials such as silicon carbide (more specifically, for example, d. A semiconductor material having an energy gap Eg greater than 3 eV) may be applied.</p><p>In addition, in this specification etc., the term "above" or "below" means that the positional relationship of the components is "directly above". Or, it does not limit that it is "directly under". For example, "Gate on the gate insulating layer The expression "electrode" includes other components between the gate insulating layer and the gate electrode. Do not exclude.</p><p>Further, in the present specification and the like, the terms "electrode" and "wiring" refer to these components as functional. It is not limited to. For example, "electrodes" may be used as part of "wiring". And vice versa. In addition, the terms "electrode" and "wiring" refer to multiple "electrodes". ] And "wiring" are integrally formed.</p><p>In addition, the "source" and "drain" functions can be used when using transistors with different polarities. , When the direction of the current changes in the circuit operation, it may be replaced. For this reason , In this specification, the terms "source" and "drain" are used interchangeably. Can be done.</p><p>In addition, in this specification etc., "electrically connected" means "thing having some kind of electrical action". Included when connected via. Here, "something that has some kind of electrical action" Is not particularly limited as long as it enables the exchange of electric signals between the connection targets.</p><p>For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements such as switching elements, resistance elements, inductors, capacitors, etc. Elements and the like are included.</p>

<p>Provides a pulse signal output circuit capable of stable operation and a shift register including the same. can do.</p>

<figref num="1">The figure which shows the configuration example of a pulse signal output circuit and a shift register.</figref><figref num="2">Shift register timing chart.</figref><figref num="3">The figure explaining the operation of the pulse signal output circuit.</figref><figref num="4">The figure explaining the operation of the pulse signal output circuit.</figref><figref num="5">The figure which shows the configuration example of a pulse signal output circuit and a shift register.</figref><figref num="6">Shift register timing chart.</figref><figref num="7">The figure explaining the operation of the pulse signal output circuit.</figref><figref num="8">The figure explaining the operation of the pulse signal output circuit.</figref><figref num="9">The figure which shows the configuration example of a pulse signal output circuit and a shift register.</figref><figref num="10">The figure which shows the structural example of a transistor.</figref><figref num="11">The figure which shows the example of the manufacturing method of a transistor.</figref><figref num="12">The figure explaining one form of the semiconductor device.</figref><figref num="13">The figure which shows the electronic device.</figref><figref num="14">Shift register timing chart.</figref>

An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows. Not limited to the description of the present invention, and without departing from the spirit and scope of the present invention. It is easily understood by those skilled in the art that the details can be changed in various ways. Therefore, the present invention is as follows. It is not construed as being limited to the description of the embodiment shown in.

In addition, the position, size, range, etc. of each configuration shown in the drawings etc. are actual for easy understanding. It may not represent the position, size, range, etc. of the edge. Therefore, the disclosed invention is indispensable. However, the position, size, range, etc. disclosed in the drawings and the like are not limited.

The ordinal numbers such as "first", "second", and "third" in the present specification and the like are a mixture of components. It should be added that it is attached to avoid the same and is not limited in number.

(Embodiment 1) In the present embodiment, a pulse signal output circuit and a shift register including a pulse signal output circuit A configuration example of the data and its operation will be described with reference to FIGS. 1 to 4.

&lt;Circuit configuration&gt; First, a pulse signal output circuit and a shift register circuit including a pulse signal output circuit. A configuration example will be described with reference to FIG.

The shift register shown in this embodiment is the first pulse signal output circuit 10_{_1}~ Nth pal Signal output circuit 10_{_n}(N is a natural number greater than or equal to 2) and the first signal that transmits the clock signal It has lines 11 to 4th signal line 14 (see FIG. 1 (A)). The first signal line 11 has the first A lock signal CLK1 is given, and a second clock signal CLK2 is given to the second signal line 12. Therefore, the third signal line 13 is given the third clock signal CLK3, and the fourth signal line 1 The fourth clock signal CLK4 is given to 4.

A clock signal is a signal that repeats an H signal (high potential) and an L signal (low potential) at regular intervals. To. Here, the first clock signal CLK1 to the fourth clock signal CLK4 are 1/4 laps. The signal is delayed by period. In the present embodiment, the pulse signal is used by using the clock signal. Controls the output circuit, etc.

First pulse signal output circuit 10_{_1}~ Nth pulse signal output circuit 10_{_n}, Each 1st input terminal 21, 2nd input terminal 22, 3rd input terminal 23, 4th input terminal 24, It has a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see Fig. 1 (B)). Teru).

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are the first signal line 11 ~ Electrically connected to any of the 4th signal lines 14. For example, the first pulse signal output times Road 10_{_1}Is that the first input terminal 21 is electrically connected to the first signal line 11 and the second input Terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is the third signal line 1. It is electrically connected to 3. Also, the second pulse signal output circuit 10_{_2}Is the first input Terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is the third signal line 1. Electrically connected to 3 and the third input terminal 23 is electrically connected to the fourth signal line 14. To. Here, the nth pulse signal output circuit 10_{_n}The signal line connected to is the second The case where the signal line 12, the third signal line 13, and the fourth signal line 14 are shown is shown, but the nth signal line is shown. Ruth signal output circuit 10_{_n}The signal line connected to will differ depending on the value of n. This Therefore, it should be added that the configuration shown here is just an example.

Further, the mth pulse signal output circuit of the shift register shown in the present embodiment (m is 2 or more self). The fourth input terminal 24 is the first output of the (m-1) pulse signal output circuit. Electrically connected to terminal 26, the fifth input terminal 25 is the (m + 2) pulse signal output circuit. It is electrically connected to the first output terminal 26 of the first output terminal 26, and the first output terminal 26 is the first (m + 1) pulse. It is electrically connected to the 4th input terminal 24 of the signal output circuit, and the 2nd output terminal 27 is OUT ( Output a signal to m).

For example, the third pulse signal output circuit 10_{_3}Then, the fourth input terminal 24 is the second pulse signal. No. output circuit 10_{_2}Is electrically connected to the first output terminal 26 of the 5 pulse signal output circuit 10_{_5}Electrically connected to the first output terminal 26 of the first output Terminal 26 is the fourth pulse signal output circuit 10_{_4}4th input terminal 24 and 1st pulse signal No. output circuit 10_{_1}It is electrically connected to the fifth input terminal 25 of.

Also, the first pulse signal output circuit 10_{_1}Then, is it the fifth wiring 15 to the fourth input terminal 24? The first start pulse (SP1) of these is input. Also, the kth pulse signal output circuit 1 0_{_k}(K is a natural number of 2 or more and n or less), the output pulse of the previous stage is input to the 4th input terminal 24. Be empowered. In addition, the (n-1) th pulse signal output circuit 10_(n-1)Then, the fifth input end The second start pulse (SP2) is input to the child 25. Also, the nth pulse signal output times Road 10_{_n}Then, the third start pulse (SP3) is input to the fifth input terminal 25. The second start pulse (SP2) and the third start pulse (SP3) are external. It may be a signal to be input or a signal generated inside the circuit.

Next, the first pulse signal output circuit 10_{_1}~ Nth pulse signal output circuit 10_{_n}Specific The configuration will be described.

First pulse signal output circuit 10_{_1}~ Nth pulse signal output circuit 10_{_n}Each of the first Pulse signal generation circuit 20 composed of transistors 101 to 104 of A first input signal composed of 0 and the fifth transistor 105 to the seventh transistor 107. It is composed of the No. generation circuit 201 and the 8th transistor 108 to the 11th transistor 111. It includes a second input signal generation circuit 202 (see FIG. 1 (C)). In addition, the first mentioned above In addition to the input terminals 21 to 5 of, the first power supply line 31 and the second power supply line 32 Therefore, a signal is supplied to the first transistor 101 to the eleventh transistor 111.

A specific configuration example of the pulse signal generation circuit is as follows.

The first terminal of the first transistor 101 (one of the source terminal and the drain terminal, the same applies hereinafter) And the first terminal of the second transistor 102 and the first output terminal 26 are electrically connected. To. Similarly, the first terminal of the third transistor 103 and the first terminal of the fourth transistor 104 The terminal 1 and the second output terminal 27 are electrically connected. And the first transistor 1 The gate terminal of 01, the gate terminal of the third transistor 103, and the first input signal generation times. The output terminal of the road is electrically connected. Also, the gate terminal of the second transistor 102 And the gate terminal of the fourth transistor 104 and the output terminal of the second input signal generation circuit, Are electrically connected.

The second terminal of the first transistor 101 (the other of the source terminal and the drain terminal, the same applies hereinafter) And the second terminal of the third transistor are electrically connected, and the first clock signal CLK 1 is entered in the node. Also, the second terminal of the first transistor 101 and the third transistor The second terminal of the engineer also functions as the first input terminal 21 of the pulse signal output circuit. The second terminal of the second transistor 102 has a first potential (eg,) via the first power line 31. For example, low potential VSS) is given, and the second terminal of the fourth transistor 104 is connected to the first terminal. A first potential is applied via the power line 31.

A specific configuration example of the first input signal generation circuit is as follows.

The first terminal of the fifth transistor 105, the first terminal of the sixth transistor 106, The first terminal of the seventh transistor 107 is electrically connected to the first terminal. Also, the 7th Tran The second terminal of the Gista 107 functions as an output terminal of the first input signal generation circuit. Also , The gate terminal of the fifth transistor 105 is the first input terminal of the first input signal generation circuit. It also functions as the fourth input terminal 24 of the pulse signal output circuit.

A second potential is applied to the second terminal of the fifth transistor 105 via the second power line 32. Eh, the second terminal of the sixth transistor 106 is connected to the first power line 31 via the first power line 31. A potential is applied, and the gate terminal of the fifth transistor 105 is connected to the pulse signal from the previous stage ( The start pulse signal) is input in the first pulse signal output circuit. 6th transistor The output signal of the second input signal generation circuit is input to the gate terminal of 106. Also, the 6th The gate terminal of the transistor 106 of the above is used as the second input terminal of the first input signal generation circuit. Function. The gate terminal of the seventh transistor 107 is connected to the second power line 32 via the second power line 32. An electric potential is given.

In the present embodiment, the seventh transistor 107 is provided, but the seventh transistor is provided. A configuration in which the data 107 is not provided may be used. When providing the 7th transistor 107, On the potential of the first terminal of the fifth transistor 105, which can occur due to the tosstrap operation. The rise can be suppressed. That is, between the gate and source of the fifth transistor 105 (or game). A fifth transition can be prevented from applying a large voltage to the area (between the drain and the drain). Deterioration of the star 105 can be suppressed.

A specific configuration example of the second input signal generation circuit is as follows.

The second terminal of the tenth transistor 110 and the first terminal of the eighth transistor 108 Are electrically connected. Also, the second terminal of the eighth transistor and the eleventh transistor The second terminal of the data and the first terminal of the ninth transistor are electrically connected to each other to form a second input. It functions as an output terminal of a signal generation circuit.

The first terminal of the eleventh transistor 111 and the first terminal of the tenth transistor 110 Is given a second potential via the second power line 32. 9th transistor 109 A first potential is applied to the second terminal via the first power line 31. Eleventh transition A pulse signal from two steps behind is input to the gate terminal of the star 111. Also, the eleventh To The gate terminal of the Langista 111 functions as the first input terminal of the second input signal generation circuit. At the same time, it also functions as the fifth input terminal 25 of the pulse signal output circuit. 8th Tran The second clock signal CLK2 is input to the gate terminal of the Gista 108. Also the 8th The gate terminal of the transistor 108 serves as the second input terminal of the second input signal generation circuit. In addition to functioning, it also functions as the second input terminal 22 of the pulse signal output circuit. 9th tiger The pulse signal from the previous stage is connected to the gate terminal of the engineer 109 (in the first pulse signal output circuit). Start pulse signal) is input. Also, the gate terminal of the 9th transistor 109 is It functions as the third input terminal of the second input signal generation circuit and also of the pulse signal output circuit. It also functions as the fourth input terminal 24. At the gate terminal of the 10th transistor 110, the 1st The clock signal CLK3 of 3 is input. Also, the gate end of the 10th transistor 110 The child functions as the fourth input terminal of the second input signal generation circuit and outputs the pulse signal. It also functions as the third input terminal 23 of the circuit.

Each configuration of the pulse signal output circuit described above (pulse signal generation circuit, first input signal generation) The circuit and the configuration example of the second input signal generation circuit, etc.) are only examples, and the disclosed invention is It is not limited to this.

In the following description of the present embodiment, in the pulse signal output circuit shown in FIG. 1 (C), the first unit The gate terminal of the Langista 101, the gate terminal of the third transistor 103, and the first input A node configured by connecting to the output terminal of the power signal generation circuit is referred to as node A. Also , The gate terminal of the second transistor 102 and the gate terminal of the fourth transistor 104 , The node composed of the connection with the output terminal of the second input signal generation circuit is referred to as node B. To do.

In order to preferably perform bootstrap operation between the above node A and the first output terminal 26 Capacitive elements may be provided. In addition, in order to maintain the potential of the node B, the node B is charged. An air-connected capacitive element may be provided.

In FIG. 1 (C), the cha of the first transistor 101 and the third transistor 103 The ratio W / L of the channel width W to the flannel length L is the channel length L of the sixth transistor 106. It is preferable that the ratio of the channel width W to W / L is larger than W / L.

Further, in FIG. 1 (C), the channel with respect to the channel length L of the fifth transistor 105. The ratio W / L of the width W is the ratio of the channel width W to the channel length L of the sixth transistor 106. It is preferably larger than W / L. Also, the channel length L of the fifth transistor 105 The ratio W / L of the channel width W to the channel width W is the ratio W / L of the seventh transistor 107 to the channel length L. It is preferably equal to the ratio W / L of the channel width W. Or, the fifth transistor 105 The ratio W / L of the channel width W to the channel length L is the channel length of the seventh transistor 107. It is preferably larger than the ratio W / L of the channel width W to L.

Further, in FIG. 1 (C), the channel with respect to the channel length L of the third transistor 103. The ratio W / L of the width W is the ratio of the channel width W to the channel length L of the fourth transistor 104. It is preferably larger than W / L.

Further, in FIG. 1C, the eighth transistor 108 and the tenth transistor 110 The channel width (W) of is smaller than the channel width (W) of the eleventh transistor 111. Is preferable.

Oxide semiconductors are used for the first transistor 101 to the eleventh transistor 111. It is preferable to have. By using oxide semiconductors, the off-current of transistors is reduced. can do. Also, compared to amorphous silicon etc., on-current and field effect transfer You can increase the degree. In addition, deterioration of the transistor can be suppressed. By this Therefore, an electronic circuit with low power consumption, high-speed operation, and improved operation accuracy is realized. To. The transistor using an oxide semiconductor will be described in detail in a later embodiment. Therefore, it is omitted here.

&lt;motion&gt; Next, the operation of the shift register shown in FIG. 1 will be explained with reference to FIGS. 2 to 4 and 14. I will reveal. Specifically, in the timing chart shown in FIG. 2, the first period 51 to the sixth period The operation in each period of 56 will be described with reference to FIGS. 3 and 4. In the timing chart , CLK1 to CLK4 each indicate a clock signal, and SP1 is the first start pulse. As shown, OUT1 to OUT4 are the first pulse signal output circuits 10._{_1}~ 4th pulse signal output Power circuit 10_{_4}Shows the output from the second output terminal of, node A and node B respectively The potentials of node A and node B are shown, and SROUT1 to SROUT4 are the first pulse signals. No. output circuit 10_{_1}~ 4th pulse signal output circuit 10_{_4}Output from the first output terminal of Shown.

In the following description, the first transistor 101 to the eleventh transistor 111 are , All are n-channel type transistors. Also, in FIGS. 3 and 4, When a transistor is represented by a solid line, the transistor is in a conductive state (on state). ), And when it is represented by a broken line, the transistor is in a non-conducting state ( It shall indicate that it is in the off state).

Typically, the first pulse signal output circuit 10_{_1}The operation of is described. 1st pulse signal No. output circuit 10_{_1}The configuration of is as described above. Also, each signal that is input is supplied. The relationship between the potentials is also as described above. In the following explanation, each input terminal and each power line All given high potentials (also called H level, H signal, etc.) are VDD, and low potentials (L level) (Also called L signal, L signal, etc.) are all VSS.

Since SP1 is at H level in the first period 51, the first pulse signal output circuit 10_{_1}The gate terminal and the ninth of the fifth transistor 105 that function as the fourth input terminal 24 of the A high potential is applied to the gate terminal of the transistor 109 of the fifth transistor 105 and the fifth transistor. Transistor 109 of 9 becomes conductive. In the first period 51, CLK3 is also H level Therefore, the tenth transistor 110 is also turned on. Also, the 7th Transis Since a high potential is given to the gate terminal of the data 107, the seventh transistor 107 is also (See Fig. 3 (A)).

When the 5th transistor 105 and the 7th transistor 107 are turned on, The potential of the mode A rises. Also, when the ninth transistor 109 is turned on, , The potential of node B drops. The potential of the second terminal of the fifth transistor 105 is VDD Therefore, the potential of the first terminal of the fifth transistor 105 is the fifth from the potential of the second terminal. Value lowered by the threshold voltage of transistor 105 of₁₀₅). So Then, since the potential of the gate terminal of the 7th transistor 107 is VDD, the 7th transistor Threshold voltage Vth of Gista 107₁₀₇Is Vth₁₀₅In the above cases, the power of node A The place is (VDD-Vth₁₀₇), And the 7th transistor 107 is turned off. one One, Vth₁₀₇Is Vth₁₀₅If less than, the 7th transistor 107 is on. The potential of node A is (VDD-Vth)₁₀₅). Below, the first Set the reaching point (maximum potential) of the potential of node A in period 51 to V_AHAnd.

Node A potential is V_AHThen, the first transistor 101 and the third transistor 103 is turned on. Here, since CLK1 is at the L level, the first output terminal 26 And the L level is output from the second output terminal 27.

In the second period 52, the potential of CLK1 switches from the L level to the H level. here Since the first transistor 101 and the third transistor 103 are in the ON state, The potential of the first output terminal 26 and the potential of the second output terminal 27 rise. In addition, the first There is a capacitance between the gate terminal and the source terminal (or drain terminal) of the transistor 101. It exists, which capacitively couples the gate and source (or drain) terminals. ing. Similarly, the gate terminal and source terminal (or drain) of the third transistor 103. There is a capacitance between the terminal and the gate terminal and the source terminal (or drain). The terminal) is capacitively coupled. Therefore, the potential of the first output terminal 26 and the second output As the potential of the force terminal 27 rises, the potential of the floating node A rises ( Bootstrap operation). The potential of node A is finally VDD + Vth₁₀₁Be higher , The potential of the first output terminal 26 and the potential of the second output terminal 27 are VDD (H level). (See Figure 2 and Figure 3 (B)).

Further, in the second period 52, since the ninth transistor 109 is in the ON state, Mode B is also maintained at L level. Therefore, the first output terminal 26 is changed from L level to H level. Suppresses the potential fluctuation of node B due to capacitive coupling when changing to a bell, resulting in a defect It is possible to prevent the occurrence of a case.

As described above, in the second period 52, the potential of the second output terminal 27 is set to the H level. In this case, in order to surely raise the potential of the second output terminal 27 to VDD (H level) , The gate voltage of the third transistor to turn on the third transistor 103 (Vgs) needs to be large enough. Vgs of the third transistor 103 is small In this case, the drain current related to the third transistor becomes smaller, so it is within the specified period (this). Here, within the second period), the potential of the second output terminal 27 is raised to VDD (H level). It takes time to make it. As a result, the rising edge of the waveform of the second output terminal 27 rises. It becomes dull and causes malfunction.

By the way, the magnitude of Vgs of the third transistor 103 in the second period 52 is the first. Determined by the potential of node A during period 51 of. Therefore, the third transistor 10 In order to increase Vgs of 3, the potential of node A can be increased as much as possible during the first period 51. It is necessary to increase it (due to circuit design, maximum VDD-Vth₁₀₅Or VDD-Vth₁₀₇). The same applies to Vgs of the first output terminal 26 and the first transistor 101. Can be said.

Therefore, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is , Larger than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106 It is preferable. Ratio of channel width W to channel length L of fifth transistor 105 W / L is the ratio W / L of the channel width W to the channel length L of the sixth transistor 106. By increasing the potential, the potential of node A in the first period 51 can be increased to V in a shorter time. DD-Vth₁₀₅Or VDD-Vth₁₀₇Can be raised to. Also, the first In period 51 of 1, the sixth transistor 106 is off, but the fifth transistor The ratio W / L of the channel width W to the channel length L of the Gista 105 is determined by the sixth transistor 1. By making the ratio of the channel width W to the channel length L of 06 W / L larger than the 6th Because the leakage current (Ioff) in the transistor 106 can be reduced. Node A potential in a shorter time VDD-Vth₁₀₅Can be raised to.

In addition, when the channel length L becomes smaller due to the miniaturization of transistors, the threshold voltage shifts. May cause the sixth transistor 106 to become normalized. In such a case Also, the ratio W / L of the channel width W to the channel length L of the sixth transistor 106 is set to the fifth. It should be smaller than the ratio W / L of the channel width W to the channel length L of the transistor 105. Therefore, the on-resistance of the 6th transistor 106 is changed to the on-resistance of the 5th transistor 105. Can be larger than. As a result, the potential of node A is changed to VDD-Vth.₁₀₅Or VDD -Vth₁₀₇The potential can be closer.

Further, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is the third. The ratio of the channel width W to the channel length L of the transistor 107 of 7 is approximately equal to W / L. Is preferable. Approximately equal is a place where there are some differences due to manufacturing errors and variations. This is a case where it can be regarded as equal, assuming that there is a match. Fifth transistor Ratio W / L of channel width W to channel length L of 105 and 7th transistor 107 By equalizing, the fifth transistor 105 and the seventh transistor 107 Since the current supply capacity can be equalized, the potential of node A can be raised efficiently. Can be done. The threshold values of the 5th transistor 105 and the 7th transistor 107 It is desirable that the voltage Vth is approximately equal.

The ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is Langista characteristics, clock frequency, first transistor 101 and third transistor It can be determined by the gate capacitance of 103, the operating voltage of the shift register, and the like.

Further, when the channel width W of the sixth transistor 106 becomes large, the sixth transistor is characterized. When the sex is normalized, the leakage current increases, which leads to a potential drop in node A. I will. Or, it interferes with the charging of node A by the fifth transistor 105. Let's go. Furthermore, when high-speed operation is required, the potential of node B is lowered in a short time, and the node It is necessary to charge A in a short time. In such a case, the potential of the 6th transistor is shortened. Need to descend between.

Therefore, the channel of the sixth transistor is larger than the channel width W of the fifth transistor. By reducing the width W, it is possible to prevent the displacement of the potential of the node A. Also, The load on the mode B can be reduced. In this way, it matches the characteristics and drive specifications of the transistor. Let the fifth transistor 105, the sixth transistor 106 and the seventh transistor By determining the size of the data 107, it is possible to realize an efficient shift register. it can.

In the third period 53, SP1 becomes L level, and the fifth transistor 105 and the ninth Transistor 109 is turned off. Also, CLK1 is maintained at H level and the node Since the potential of A does not change, VDD from the first output terminal 26 and the second output terminal 27. (H level) is output (see Fig. 3 (C)). In addition, node B floats in the third period 53. Although it is in a play state, the potential of the first output terminal 26 does not change, so there is a problem due to capacitive coupling. It can be ignored.

In the fourth period 54, CLK2 and CLK3 are at H level, so that node B The potential rises in a short time. Also, CLK1 becomes the L level. As a result, the second transition The star 102 and the fourth transistor 104 are turned on, and the first output terminal 26 and And the potential of the second output terminal 27 drops in a short time (see Fig. 4 (A)). Also, the sixth tiger Since the engineer 106 is turned on, the potential of node A becomes the L level. This will Since the first transistor 101 and the third transistor 103 are in the off state, the first transistor The potentials of the output terminal 26 and the second output terminal 27 of the above are at the L level.

In the fourth period 54, the potential of node A is before the sixth period when CLK1 becomes H level. By (that is, during the 4th period 54 and the 5th period 55), it must be ensured to be VSS. To. During the fifth period 55, if the potential of node A has not dropped to VSS, the third tran Due to the capacitive coupling between the gate and the source of Gista 103, the potential of node A rises again, and the first Transistor 101 of 1 and transistor 103 of 3 are turned on, and the first output Charges may flow to the terminal 26 and the second output terminal 27, resulting in malfunction.

Therefore, the first transistor 101, the third transistor 103, and the sixth transistor By determining the relationship of the star 106 as in equations (1) to (7), the operation caused by the load It is possible to reduce the problems of the above and stabilize the operation.

<maths num="1"><img file="JP5111680B2_D0001.tif" /></maths> (1)

<maths num="2"><img file="JP5111680B2_D0002.tif" /></maths> (2)

<maths num="3"><img file="JP5111680B2_D0003.tif" /></maths> (3)

<maths num="4"><img file="JP5111680B2_D0004.tif" /></maths> (4)

<maths num="5"><img file="JP5111680B2_D0005.tif" /></maths> (5)

<maths num="6"><img file="JP5111680B2_D0006.tif" /></maths> (6)

<maths num="7"><img file="JP5111680B2_D0007.tif" /></maths> (7)

In the above equation, t_CKHIs the H level period of CLK1, that is, the second period 52 and the third Corresponds to period 53, t_CKLIs the L level period of CLK1, that is, the fourth period 54 And corresponds to the fifth period 55, t_offIs when node A takes to discharge to VSS Corresponds in between. That is, t_CKLT during the period_offUse the time of node A to increase the potential of node A It will be lowered to VSS. t_offIs in the 4th period 54 and the 5th period 55 Then, for example, the fourth period 54_1 and the fourth period 54_1 to 54_3 are the fourth. The period may be 54_1 to 54_5 (see Fig. 14). Preferably the fourth period 54 and the fifth It is the fourth period 54_1 to 54_3, which corresponds to the period of 1/2 of the period 55 of. t_CKLTo On the other hand t_offIf is set too short, the 6th to lower the potential of node A quickly It is necessary to increase the channel width W size of the transistor 106 of the t_offSet up for a long time If it is determined, the potential of node A cannot be completely discharged to VSS by the time signal H of the next clock is input, which is an error. This is because there is a possibility of operation. That is, t_offConsiders the frequency of the clock signal, etc. It is necessary to make a decision with consideration. The timing chart shown in FIG. 14 shows a part of the period (example). For example, the fourth period 54_1 to 54_5) is exaggerated, but the timing shown in Fig. 2 is shown. There is no big difference from the chart.

Also, C₁₀₁And C₁₀₃Is the first transistor 101 and the third transistor, respectively. Indicates the gate capacity of Gista 103, V_fIndicates the potential of node A in the third period 53.

I shown in equation (2)₁₀₆Indicates the drain current of the sixth transistor 106. This From this, the size of the sixth transistor 106 (for example, W / L) can be determined. That is, the size of the sixth transistor 106 is the operating frequency of CLK1 and the first transistor. Determined by the size of the data 101 and the third transistor 103, and the potential of node A. Can be done.

For example, if the operating frequency of CLK1 is high, the potential of node A needs to drop faster. Therefore, from equation (1), t_offNeeds to be smaller, so i₁₀₆To It will be necessary to increase it. So i₁₀₆W from equation (2) according to₁₀₆Calculate and W size can be determined.

On the other hand, when the size of the first transistor 101 and the third transistor 103 is small. To i₁₀₆Can be small, so from equation (2), W₁₀₆Becomes smaller. by the way, Since the third transistor 103 is used for charging / discharging the output load, the third transistor 103 By increasing the size of the data, not only the fourth transistor 104 but also the fourth transistor 104 will be discharged during discharge. , Since the third transistor 103 can also be discharged, the output potential can be lowered. It can be done in a short time. Therefore, if the potential of node A is gradually lowered, the third Transistor 103 is in the ON state, so only the fourth transistor 104 discharges. Therefore, the potential of the output can be lowered in a short time. In this way, the characteristics of the transistor It is effective by determining the size of the sixth transistor 106 according to the characteristics and drive specifications. A high-rate shift register can be realized.

Also, in the fourth period 54, at the same time as CLK1 changes from H level to L level, the fifth A pulse signal (SROUT3) is input to the input terminal 25 of the 11th transistor 111. Is turned on. When the eleventh transistor 111 is turned on, the power of node B is turned on. Place is VDD-Vth₁₁₁Charged up to, 2nd transistor 102, 4th transistor The data 104 and the sixth transistor 106 are turned on. Second transistor 102 And when the 4th transistor 104 is turned on, the 1st output terminal 26 and the 1st output terminal 26 and the 4th transistor 104 are turned on. The potential of the output terminal 27 of 2 is VSS. Also, the first transistor 101 and the third The transistor 103 is turned off.

At this time, the node B is charged through the eleventh transistor 111 and the first It is done through the zero transistor 110 and the eighth transistor 108. 10th Tran The gates of the Gista 110 and the eighth transistor 108 are the third input terminals 23, respectively. And is connected to the second input terminal 22, and the gate capacitance remains the same as the third input terminal 23. And it becomes the load of the second input terminal 22.

In the shift register shown in the present embodiment, the transformer connected to the clock line The load of the gista is the total number of stages of the shift register ÷ 4 × (Lov + of the third transistor 103) Lov of the first transistor 101 + gate capacitance of the tenth transistor 110 + eighth It is represented by the gate capacitance of the transistor 108). The gate capacitance is ε₀× ε × ( Expressed as L × W) / tox. Lov is the source electrode layer of the transistor or the disk. It represents the length of the region where the rain electrode layer and the semiconductor layer overlap in the channel length direction.

Eighth transistors 108 and ten to reduce the gate capacitance connected to the clock line The channel width (W) of the transistor 110 is the channel width of the eleventh transistor 111. It is preferably smaller than (W). This makes it possible to reduce the load on the clock line. It can be operated at high speed. Also, the 10th transistor 110 and the 8th tiger The layout area is reduced by reducing the channel width (W) of the engineer 108. Can be made.

In the fifth period 55, the potential of the fifth input terminal 25 (that is, SROUT3) is H level. By holding the node B, the potential of the node B is held. Therefore, the second transistor 102, 4th transistor 104 and 6th transistor 106 are kept on Therefore, the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level (Fig.). See 4 (B)).

In the sixth period 56, the fifth input terminal 25 (that is, SROUT3) becomes the L level. Therefore, the eleventh transistor 111 is turned off. At this time, the node B has the above-mentioned potential. It becomes a floating state while holding. As a result, the second transistor 102 and the fourth transistor The Jista 104 and the 6th transistor 106 continue to be on (see Fig. 4 (C)). .. The potential of node B usually drops due to the off-current of the transistor, etc. A transistor with a small off-current (for example, a transistor using an oxide semiconductor) is suitable. When used, such a problem does not occur. It also alleviates the drop in the potential of node B. Therefore, a capacitive element may be provided.

If both CLK2 and CLK3 reach H level in the subsequent period, the first Transistor 108 of 8 and transistor 110 of 10 are turned on and periodically no An electric potential is given to de B. Therefore, when using a transistor with a relatively large off-current Even so, the malfunction of the pulse signal output circuit can be prevented.

Regarding the output from the shift register (OUT1 to OUT4, etc.), when the potential rises There are cases where emphasis is placed on the time when the potential drops. For example, due to an increase in electric potential When determining the data (for example, when writing data), when the potential rises Is emphasized. In addition, when the data is confirmed by the decrease of the potential, the time of the decrease of the potential is It is emphasized.

When the data is confirmed by the increase of the potential, it is necessary to shorten the time required for the increase of the potential. There is a need. For that purpose, the channel width with respect to the channel length L of the third transistor 103 The ratio W / L of W is the ratio W of the channel width W to the channel length L of the fourth transistor 104. It is preferably larger than / L.

When the data is confirmed by the decrease of the potential, it is necessary to shorten the time required for the decrease of the potential. There is a need. For that purpose, the channel width with respect to the channel length L of the third transistor 103 The ratio W / L of W is the ratio W of the channel width W to the channel length L of the fourth transistor 104. It is preferably larger than / L.

However, in one aspect of the disclosed invention, the potential of node A is controlled by the gate of the third transistor 103. It is raised to a predetermined potential by bootstrap operation using capacitive coupling between the source and the source. As a result, the third transistor 103 is turned on and an H level signal is output. Therefore, the ratio W / L of the channel width W to the channel length L of the third transistor 103 is If it is not large enough, the H level potential output by the shift register rises to VDD. Since the problem of not being able to cut can occur, the channel length L of the third transistor 103 can be changed. It is desirable that the ratio W / L of the channel width W be sufficiently large.

The shift register shown in this embodiment is output from the mth pulse signal output circuit. The pulse to be generated and the pulse output from the (m + 1) th pulse signal output circuit are half overlapped. The movement method is adopted. Therefore, compared to the case where the drive method is not adopted, the wiring is filled. The time that can be used for electricity can be extended. In other words, depending on the drive method, a large negative A pulse signal output circuit that can withstand loads and operates at high frequencies is provided.

(Embodiment 2) In this embodiment, the pulse signal output circuit and shiftless shown in the previous embodiment A configuration example different from that of the gista and its operation will be described with reference to FIGS. 5 to 8. ..

&lt;Circuit configuration&gt; First, a pulse signal output circuit and a shift register circuit including a pulse signal output circuit. A configuration example will be described with reference to FIG.

The configuration of the shift register shown in the present embodiment is the shift register shown in the previous embodiment. It is similar to the composition of the star. One of the differences is the first pulse signal output circuit 10_{_1}~ Nth Pulse signal output circuit 10_{_n}Is the point that does not have the third input terminal 23 (Fig. 5 (A)). See Figure 5 (C)). In other words, two types of clock signals are input to one pulse signal output circuit. Be empowered. Other configurations are the same as those in the previous embodiment.

First pulse signal output circuit 10_{_1}~ Nth pulse signal output circuit 10_{_n}Is the third input Since it does not have terminal 23, it does not have a tenth transistor connected to it (Fig. 5 (C). )reference). Along with this, the second input signal generation circuit 202 shown in FIG. 1 and FIG. 5 are shown. The connection relationship of the second input signal generation circuit 203 is partially different.

Specifically, the first pulse signal output circuit 10_{_1}~ Nth pulse signal output circuit 10_{_n}of Each is a pulse signal composed of the first transistor 101 to the fourth transistor 104. It is composed of a generation circuit 200 and a fifth transistor 105 to a seventh transistor 107. First input signal generation circuit 201, eighth transistor 108, ninth transistor 10 A second input signal generation circuit 203, which is composed of 9th and 11th transistors 111, Including. Further, in addition to the first input terminal 21 to the fifth input terminal 25 described above, the first power supply line 3 From the 1st and 2nd power lines 32, the 1st transistor 101 to the 11th transistor 11 A signal is supplied to 1.

A specific configuration example of the second input signal generation circuit 203 is as follows.

The second terminal of the eighth transistor 108 and the second terminal of the eleventh transistor 111 , The second input signal generation time is electrically connected to the first terminal of the ninth transistor 109. Functions as a road output terminal.

To the first terminal of the eleventh transistor 111 and the first terminal of the eighth transistor 108 Is given a second potential via the second power line 32. 9th transistor 109th A first potential is applied to the second terminal via the first power line 31. 11th Transis A pulse signal is input to the gate terminal of the data 111. Also, the eleventh transistor 111 The gate terminal of is functioning as the first input terminal of the second input signal generation circuit, and the pal It also functions as the fifth input terminal 25 of the signal output circuit. 8th transistor 108 The second clock signal CLK2 is input to the input terminal. Also, the eighth transistor 10 The gate terminal of 8 functions as the second input terminal of the second input signal generation circuit, and also functions as a power supply. It also functions as the second input terminal 22 of the loose signal output circuit. 9th transistor 109 A pulse signal is input to the gate terminal. Also, the gate terminal of the ninth transistor 109 Functions as the third input terminal of the second input signal generation circuit and the pulse signal output times. It also functions as the fourth input terminal 24 of the road.

The above-mentioned configuration is only an example, and the disclosed invention is not limited to this.

In the following description of the present embodiment, the pulse signal output shown in FIG. 5 (C) is output as in the previous embodiment. In the power circuit, the gate terminal of the first transistor 101 and the third transistor 103 A node consisting of a connection between the gate terminal and the output terminal of the first input signal generation circuit. , Node A. Also, the gate terminal of the second transistor 102 and the fourth transistor The gate terminal of the data 104, the second terminal of the eighth transistor 108, and the eleventh transition It is configured by connecting the second terminal of the star 111 and the first terminal of the ninth transistor 109. Let the formed node be node B.

In order to preferably perform bootstrap operation between the above node A and the first output terminal 26 Capacitive elements may be provided. In addition, in order to maintain the potential of the node B, the node B is charged. An air-connected capacitive element may be provided.

The first transistor 101 to the ninth transistor 109 and the eleventh transistor 1 It is preferable to use an oxide semiconductor for 11. By using oxide semiconductors The off current of the Langista can be reduced. Also, compared to amorphous silicon etc. On-current and field effect mobility can be increased. In addition, it suppresses the deterioration of the transistor. can do. As a result, power consumption is low, high-speed operation is possible, and operation accuracy is high. It is possible to realize an enhanced electronic circuit. A transition using an oxide semiconductor The star will be described in detail in a later embodiment, and will be omitted here.

&lt;motion&gt; Next, the operation of the shift register shown in FIG. 5 will be described with reference to FIGS. 6 to 8. Specifically Specifically, each period of the first period 51 to the fifth period 55 in the timing chart shown in FIG. The operation in the above will be described with reference to FIGS. 7 and 8. In the timing chart, CLK1 ~ CLK4 indicates the clock signal, SP1 indicates the first start pulse, and OUT 1 to OUT4 are the first pulse signal output circuit 10_{_1}~ 4th pulse signal output circuit 10_{_}₄Indicates the output from the second output terminal of, node A and node B are node A and node B, respectively. And the potential of node B, SROUT1 to SROUT4 are the first pulse signal output circuit 1 0_{_1}~ 4th pulse signal output circuit 10_{_4}Indicates the output from the first output terminal of.

In the following description, the first transistor 101 to the ninth transistor 109, the first transistor 109 It is assumed that all the transistors 111 of 11 are n-channel type transistors. Also , In FIGS. 7 and 8, when the transistor is represented by a solid line, the transistor is concerned. Indicates that the gista is in a conductive state (on state), and if it is represented by a broken line, it corresponds to the relevant state. It shall indicate that the transistor is in a non-conducting state (off state).

Typically, the first pulse signal output circuit 10_{_1}The operation of is described. 1st pulse signal No. output circuit 10_{_1}The configuration of is as described above. Also, each signal that is input is supplied. The relationship between the potentials is also as described above. In the following explanation, each input terminal and each power line All given high potentials (also called H level, H signal, etc.) are VDD, and low potentials (L level) (Also called L signal, L signal, etc.) are all VSS.

Since SP1 is at H level in the first period 51, the first pulse signal output circuit 10_{_1}The gate terminal and the ninth of the fifth transistor 105 that function as the fourth input terminal 24 of the A high potential is applied to the gate terminal of the transistor 109 of the fifth transistor 105 and the fifth transistor. Transistor 109 of 9 becomes conductive. Also, the gate end of the 7th transistor 107 Since the child is given a high potential, the seventh transistor 107 is also turned on (Fig. 7). See (A)).

When the 5th transistor 105 and the 7th transistor 107 are turned on, The potential of the mode A rises. Also, when the ninth transistor 109 is turned on, , The potential of node B drops. Node A potential is V_AH(V_AH= VDD-Vth₁₀₅-Vth₁₀₇), The fifth transistor 105 and the seventh transistor 107 is off and node A is V_AHIt becomes a floating state while maintaining.

Node A potential is V_AHThen, the first transistor 101 and the third transistor 103 is turned on. Here, since CLK1 is at the L level, the first output terminal 26 And the L level signal is output from the second output terminal 27.

In the second period 52, the potential of CLK1 switches from the L level to the H level. here Since the first transistor 101 and the third transistor 103 are in the ON state, The potential of the first output terminal 26 and the potential of the second output terminal 27 rise. In addition, the first There is a capacitance between the gate terminal and the source terminal (or drain terminal) of the transistor 101. It exists, which capacitively couples the gate and source (or drain) terminals. ing. Similarly, the gate terminal and source terminal (or drain) of the third transistor 103. There is a capacitance between the terminal and the gate terminal and the source terminal (or drain). The terminal) is capacitively coupled. Therefore, the potential of the first output terminal 26 and the second output As the potential of the force terminal 27 rises, the potential of the floating node A rises ( Bootstrap operation). The potential of node A is finally VDD + Vth₁₀₁Be higher , The potential of the first output terminal 26 and the potential of the second output terminal 27 are VDD (H level). (See Figure 6 and Figure 7 (B)).

In the third period 53, the potential of CLK2 becomes H level, and the eighth transistor 10 8 turns on. As a result, the potential of node B rises. To increase the potential of node B 2nd transistor 102, 4th transistor 104, and 6th transistor The data 106 is turned on, and the potential of node A drops. Therefore, the first output terminal 26 The potential of and the potential of the second output terminal 27 are at the L level (see FIG. 7 (C)).

In the fourth period 54, the potential of CLK2 becomes the L level, and the eighth transistor 10 8 is turned off, but the potential of the 5th input terminal 25 (that is, SROUT3) is H level. Therefore, the eleventh transistor 111 is turned on. Therefore, with the potential of node A The potential of node B is maintained at the potential of 53 during the third period, and the potential of the first output terminal 26 and the potential of the first output terminal 26 are maintained. The potential of the second output terminal 27 is held at the L level (see FIG. 8 (A)).

In the fifth period 55, the potential of the fifth input terminal 25 (that is, SROUT3) is L level. The potential of node B is maintained. Therefore, the second transistor 102, the fourth The on state of the transistor 104 and the sixth transistor 106 is held, and the first output The potentials of the force terminal 26 and the second output terminal 27 are held at the L level (see Fig. 8 (B)). ..

The potential of node B usually drops due to the off-current of the transistor, etc., but it is sufficient. Apply a transistor with a small off-current (for example, a transistor using an oxide semiconductor) If so, such a problem does not occur. Also, to mitigate the drop in the potential of node B May be provided with a capacitive element. The capacitive element provided in this case is the second transistor 1. 02 gate terminal, 4th transistor 104 gate terminal, 6th transistor 1 The gate terminal of 06, the first terminal of the eighth transistor 108, and the ninth transistor 1 It is electrically connected to the first terminal of 09.

If the potential of CLK2 reaches the H level in the subsequent period, the eighth tran Gista 108 is turned on and potential is periodically applied to node B. For this reason, off Malfunction of pulse signal output circuit even when using a transistor with a relatively large current Can be prevented.

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 3) In this embodiment, the pulse signal output circuit and shiftless shown in the previous embodiment A configuration example of a mode different from that of the gista will be described with reference to FIG.

The configuration of the shift register shown in the present embodiment is the shift register shown in the previous embodiment. It is similar to the composition of the star. One of the differences is the nth pulse signal output circuit 10_{_n}In the latter part , 1st dummy pulse signal output circuit 10_{_D1}And the second dummy pulse signal output circuit 1 0_{_D2}Is the point where is connected (see Figure 9 (A)). 1st dummy pulse signal output times Road 10_{_D1}And the second dummy pulse signal output circuit 10_{_D2}Is the n-1th pulse signal output Power circuit 10_{_n-1}And the nth pulse signal output circuit 10_{_n}To the 5th input terminal 25 of It has a function to supply a signal.

First dummy pulse signal output circuit 10_{_D1}And the second dummy pulse signal output circuit 10_{_D}₂There is no pulse signal output circuit in the latter stage. That is, the first to nth pulse signal outputs Unlike the circuit, the first dummy pulse signal output circuit 10_{_D1}And the second dummy pulse signal Output circuit 10_{_D2}The pulse signal from the latter stage (in this case, two stages later) is not input to. This Therefore, the terminal corresponding to the fifth input terminal 25 in the first to nth pulse signal output circuits is Does not exist (see Figures 9 (B) and 9 (C)). Also related to the 5th input terminal 25 The eleventh transistor 111 also does not exist (see FIG. 9 (C)).

The function of the dummy pulse signal output circuit (first and second dummy pulse signal output circuits) is the normal stage. Outputs an appropriate pulse signal to the pulse signal output circuit (n-1st to nth pulse signal output circuit) of Because it is a force, the dummy pulse signal output circuit can be fully charged with its node B. Ability is required. Here, in the first to nth pulse signal output circuits, the clock signal is input. Eighth transistor 108 and tenth transistor to reduce power consumption due to force Reduce the size of the engineer 110 (for example, for channel width W or channel length L) The ratio W / L of the channel width W is reduced), and the charging capacity is increased by the 11th transistor 111. It is effective to take a configuration that secures. On the other hand, the dummy pulse signal output circuit has the eleventh Since the transistor 111 does not exist, the charging capacity of the eleventh transistor 111 is supplemented. To the extent that it can be done, of the 8th transistor 108 and the 10th transistor 110 It is necessary to increase the size.

Specifically, for example, the eighth transistor of the first and second dummy pulse signal output circuits, or Is the ratio of the channel width W to the channel width W (or channel length L) of the tenth transistor. W / L), the 8th transistor or the 10th transistor of the 1st to nth pulse signal output circuits Greater than the channel width W (or the ratio W / L of the channel width W to the channel length L) of the engineer Just listen. By adopting such a configuration, the pulse signal output circuit of the normal stage (nth) -Ensure proper operation while reducing power consumption in the nth pulse signal output circuit) A shift register is realized.

The basic configuration of the dummy pulse signal output circuit is the above-described embodiment except for the above differences. It is the same as the pulse signal output circuit shown in. Specifically, the first pulse signal output times Road 10_{_1}~ Nth pulse signal output circuit 10_{_n}Each of the first transistors 101 ~ A dummy pulse signal generation circuit 204 composed of a fourth transistor 104 and a fifth transistor First input signal generation circuit 205 composed of engineer 105 to seventh transistor 107 And the second input signal composed of the 8th transistor 108 to the 10th transistor 110 Includes number generation circuit 206 and. Also, from the first power line 31 and the second power line 32, the first A signal is supplied to the 1st transistor 101 to the 10th transistor 110.

Also, regarding the operation of the dummy pulse signal output circuit, except that the output of the subsequent stage is not input. This is the same as the pulse signal output circuit shown in the previous embodiment. Therefore, in detail It is possible to take into account the previous embodiment. The tenth transistor 110 is , May or may not be provided. Also, in the dummy pulse signal output circuit, at least The output to the regular stage pulse signal output circuit (n-1st to nth pulse signal output circuit) is secured. Therefore, the number of output terminals is not limited to two, but may be one. That is, the first output It is possible to omit the terminal 26 or the second output terminal 27. In this case, A transistor associated with the omitted output terminal (for example, a place where the second output terminal 27 is omitted) In that case, the third transistor 103 and the fourth transistor 104) should be omitted as appropriate. Just do it.

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 4) In this embodiment, it is applied to the pulse signal output circuit and the shift register described in the above embodiment. An example of a possible transistor will be described with reference to FIG. The structure of the transistor Is not particularly limited, for example, top gate structure or bottom gate structure, stagger type or An appropriate structure such as a planar type can be adopted. Also, the transistor is a channel type Even in a single gate structure having one growth region, a multi-gate structure having two or more channel formation regions It may have a gate structure. In addition, it is arranged above and below the channel region via a gate insulating layer. A structure having two gate electrode layers may be used.

10 (A) to 10 (D) show an example of the cross-sectional structure of the transistor. Figure 10 (A) The transistor shown in FIG. 10 (D) uses an oxide semiconductor as a semiconductor. .. The advantage of using oxide semiconductors is that it is a simple process, a low temperature process, and a high transfer rate. It can be said that motility and low off-current can be realized.

The transistor 410 shown in FIG. 10 (A) is an example of a transistor having a bottom gate structure. Also called a reverse staggered transistor.

The transistor 410 is a gate electrode layer 401, a gate, on a substrate 400 having an insulating surface. Insulation layer 402, oxide semiconductor layer 403, source electrode layer 405a, and drain electrode layer 40 Including 5b. Further, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. Insulation A protective insulating layer 409 is further formed on the layer 407.

The transistor 420 shown in FIG. 10 (B) is a channel protection type (also referred to as a channel stop type). This is an example of a bottom gate structure transistor called (c), which is an inverted staggered transistor. Also called.

The transistor 420 is a gate electrode layer 401, a gate, on a substrate 400 having an insulating surface. Insulating layer 402, oxide semiconductor layer 403, insulating layer 427 functioning as a channel protection layer, The base electrode layer 405a and the drain electrode layer 405b are included. In addition, a protective insulation layer 409 is installed. It has been kicked.

The transistor 430 shown in FIG. 10 (C) is an example of a bottom gate type transistor. .. Transistor 430 is a gate electrode layer 401, a game, on a substrate 400 having an insulating surface. Insulation layer 402, source electrode layer 405a, drain electrode layer 405b, and oxide semiconductor layer Includes 403. Further, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. Absolute A protective insulating layer 409 is further formed on the edge layer 407.

In the transistor 430, the gate insulating layer 402 is the substrate 400 and the gate electrode layer 40. The source electrode layer 405a and the drain are provided on the gate insulating layer 402 in contact with the source electrode layer 405a. The in-electrode layer 405b is provided in contact with the in-electrode layer 405b. Then, the gate insulating layer 402 and the source An oxide semiconductor layer 403 is provided on the electrode layer 405a and the drain electrode layer 405b.

The transistor 440 shown in FIG. 10 (D) is an example of a transistor having a top gate structure. To. The transistor 440 is an insulating layer 437, a half oxide, on a substrate 400 having an insulating surface. Conductor layer 403, source electrode layer 405a, drain electrode layer 405b, gate insulating layer 402, And the gate electrode layer 401. Then, the source electrode layer 405a and the drain electrode layer 405 A wiring layer 436a and a wiring layer 436b are provided in contact with b, respectively.

In the present embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. Oxidation The oxide semiconductor used for the product semiconductor layer 403 is In-Sn-, which is a quaternary metal oxide. Ga-Zn-O system, In-Ga-Zn-O system, which is a ternary metal oxide, In-Sn-Z nO system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system , Sn-Al-Zn-O system, In-Zn-O system which is a binary metal oxide, In-Ga- O system, Sn-Zn-O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, I n-Mg-O type, In-O type, Sn-O type, Zn-O type, which are unified metal oxides, etc. is there. In addition, SiO is added to the oxide semiconductor.₂May be added. Here, for example, In-G An a-Zn-O oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio of. It may also contain elements other than In, Ga and Zn.

The oxide semiconductor layer 403 has the chemical formula InMO.₃(ZnO)_m(m&gt; 0, m: non-natural Oxide semiconductors represented by numbers) can be used. Where M is gallium (Ga) , Aluminum (Al), Manganese (Mn) and Cobalt (Co) Indicates multiple metal elements. For example, M includes Ga, Ga and Al, Ga and Mn, and so on. There are also Ga and Co.

Transistor 410, transistor 420, transistor using oxide semiconductor layer 403 The 430 and the transistor 440 can make the off-current extremely small. Therefore By using this for the pulse signal output circuit and shift register, the potential holding of each node can be maintained. It will be easier and the probability of malfunction of the pulse signal output circuit and shift register will be kept extremely low. Can be done.

There are no major restrictions on the substrates that can be used with the substrate 400 having an insulating surface. For example A glass substrate or a quartz substrate used for a liquid crystal display device or the like can be used. Also , A substrate in which an insulating layer is formed on a silicon wafer or the like may be used.

For bottom gate structure transistor 410, transistor 420, transistor 430 Therefore, an insulating layer as a base may be provided between the substrate and the gate electrode layer. The insulating layer is a substrate It has a function to prevent the diffusion of impurity elements from silicon nitride film, silicon oxide film, and nitriding. Formed by one or more films selected from a silicon oxide film or a silicon oxynitride film Can be done.

The gate electrode layer 401 is composed of molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Metallic materials such as nium, copper, neodymium, scandium, or alloy materials containing these as the main components Can be formed using. Further, the structure may be a single-layer structure or a laminated structure. May be.

The gate insulating layer 402 is a silicon oxide film using a plasma CVD method, a sputtering method, or the like. Silicon nitride film, silicon oxide film, silicon oxide film, aluminum oxide film, nitride Aluminum film, aluminum nitride film, aluminum nitride film, hafnium oxide film It can be formed by one or more films selected from the above. For example, the first gate is cut off Silicon nitride film with a film thickness of 50 nm or more and 200 nm or less by plasma CVD method as an edge layer ( SiN_y(y&gt; 0)) is formed, and a spa is formed as a second gate insulating layer on the first gate insulating layer. Silicon oxide film (SiO) with a film thickness of 5 nm or more and 300 nm or less by the cutter method_x(x&gt; 0)) It can be formed into a gate insulating layer having a total film thickness of about 300 nm.

The source electrode layer 405a and the drain electrode layer 405b are molybdenum, titanium, chromium, and tan. Metallic materials such as tar, tungsten, aluminum, copper, neodymium, scandium, etc. It can be formed by using an alloy material containing these as the main components. For example, aluminum or copper With a laminated structure of a metal layer such as titanium, molybdenum, and a refractory metal layer such as tungsten can do. Elements that prevent the generation of hillocks and whiskers (silicon, neodymium, Even if the heat resistance is improved by using an aluminum material with scandium added) good.

In addition, the source electrode layer 405a and the drain electrode layer 405b (wiring formed by the same layer). A conductive metal oxide film may be used as the conductive film (including the layer). Conductive metallic acid Indium oxide (In₂O₃), Tin oxide (SnO)₂), Zinc oxide (ZnO) ), Indium tin oxide alloy (In₂O₃SnO₂, Sometimes abbreviated as ITO ), Indium tin oxide alloy (In₂O₃ZnO) or these metal oxide materials It is possible to use a product containing silicon oxide or the like.

Wiring layer 436a and wiring layer 436 in contact with the source electrode layer 405a and the drain electrode layer 405b. For b, use the same materials as the source electrode layer 405a and drain electrode layer 405b. Can be done.

The insulating layer 407, the insulating layer 427, and the insulating layer 437 are typically a silicon oxide film or an oxide. Inorganic insulating film such as silicon nitride film, aluminum oxide film, or aluminum nitride film Can be used.

The protective insulating layer 409 includes a silicon nitride film, an aluminum nitride film, and a silicon nitride film. , An inorganic insulating film such as an aluminum nitride film can be used.

Further, on the protective insulating layer 409, flattening is performed to reduce surface unevenness caused by the transistor. A marginal membrane may be formed. The flattening insulating film includes polyimide, acrylic, and benzocyclobu. Organic materials such as ten can be used. In addition to the above organic materials, low dielectric constant materials (l ow-k material) etc. can be used. A plurality of insulating films formed of these materials are provided. A flattening insulating film may be formed by laminating.

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 5) In the present embodiment, an example of a transistor including an oxide semiconductor layer and a method for producing the same is presented. This will be described in detail with reference to FIG.

11 (A) to 11 (E) are cross-sectional views of the transistor manufacturing process. In addition, here The transistor 510 shown in FIG. 10 is a reverse stagger similar to the transistor 410 shown in FIG. 10 (A). It is a type transistor.

The oxide semiconductor used for the semiconductor layer of the present embodiment uses hydrogen, which is an n-type impurity, as an oxide semiconductor. Remove from the oxide semiconductor to make it highly pure so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. With i-type (intrinsic) oxide semiconductors or i-type (intrinsic) oxide semiconductors It was done.

In the highly purified oxide semiconductor, the number of carriers is extremely small, and the carrier concentration is 1 ×. Ten¹⁴/cm³Less than, preferably 1x10¹²/cm³Less than, more preferably 1x1 0¹¹/cm³Will be less than. Also, due to the small number of carriers like this, you can stay off. Current (off current) is sufficiently small.

Specifically, the transistor provided with the oxide semiconductor layer described above is placed at room temperature (25 ° C). Off-current density per 1 μm of channel width, transistor channel length L is 10 μm, 100zA / μm (1) under the condition that the voltage between the source and drain of the transistor is 3V. × 10^-19A / μm) or less, and even 10zA / μm (1 × 10)^-20A / μm) or less It is possible to.

Further, the transistor 510 provided with the highly purified oxide semiconductor layer has an on-current temperature. Little dependence is seen and the off-current remains very small.

Hereinafter, using FIGS. 11 (A) to 11 (E), a process for manufacturing the transistor 510 on the substrate 505. I will explain the process.

First, after forming a conductive film on the substrate 505 having an insulating surface, the first photolithography The gate electrode layer 511 is formed by the process. Used in the photolithography process The resist mask may be formed by an inkjet method. Ink jet mask Since the photomask is not used when it is formed by the method, the manufacturing cost can be reduced.

For the substrate 505 having an insulating surface, a substrate similar to the substrate 400 in the above embodiment is used. Can be In this embodiment, a glass substrate is used as the substrate 505.

An insulating layer as a base may be provided between the substrate 505 and the gate electrode layer 511. The relevant The insulating layer has a function of preventing the diffusion of impurity elements from the substrate 505, and is a silicon nitride film. , Silicon oxide film, silicon nitride film, silicon oxide film, etc. It can be formed by a plurality of films.

The gate electrode layer 511 is composed of molybdenum, titanium, chromium, tantalum, tungsten, etc. Metallic materials such as aluminum, copper, neodymium, scandium, etc. It can be formed using a gold material. Further, the structure may be a single-layer structure or a product. It may be a layered structure.

Next, the gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 , It can be formed by using a plasma CVD method, a sputtering method, or the like. Also, Sirico Oxidation Film, silicon nitride film, silicon oxide film, silicon oxide film, aluminum oxide film , Aluminum nitride film, Aluminum nitride film, Aluminum nitride film, Huffni oxide It can be formed by one or more membranes selected from a um membrane or the like.

The gate insulating layer 507 and the oxide semiconductor film 530 contain hydrogen, hydroxyl groups, and water as much as possible. Sputtering device as a pretreatment for film formation of the oxide semiconductor film 530 to prevent it from getting stuck Substrate 505 or gate insulating layer 507 on which the gate electrode layer 511 is formed in the preheating chamber of Preheat the substrate 505 on which the above is formed, and remove hydrogen, moisture, etc. adsorbed by the substrate 505. It is preferable to remove impurities. The exhaust means provided in the preheating chamber is cryopo. It is preferable to use a pump. Further, the preheating is performed on the source electrode layer 515a and the drain. This may be performed on the substrate 505 formed up to the electrode layer 515b. In addition, this preheating process The theory can be omitted.

Next, on the gate insulating layer 507, the film thickness is 2 nm or more and 200 nm or less, preferably 5 nm or more. An oxide semiconductor film 530 having an upper diameter of 30 nm or less is formed (see FIG. 11 (A)).

The oxide semiconductor film 530 is provided with the quaternary metal oxide and the ternary metal oxidation shown in the above-described embodiment. Material, binary metal oxide, In-O type, Sn-O type, Zn-O type, etc. can be used. ..

As a target for producing the oxide semiconductor film 530 by the sputtering method, in particular, In: Ga: Zn = 1: x: y (x is 0 or more, y is 0.5 or more and 5 or less) It is preferable to use it. For example, In₂O₃: Ga₂O₃: ZnO = 1: 1: 2 [mol A target having a composition ratio of [number ratio] can be used. Also, In₂O₃: Ga₂O₃: ZnO = 1: 1: 1 [mol number ratio] target or In₂O₃: Ga₂O₃Targets with a composition ratio of: ZnO = 1: 1: 4 [mol number ratio] and In₂O₃: Ga₂O₃: ZnO = 1: 0: 2 [mol number ratio] target with composition ratio It can also be used.

In the present embodiment, the oxide semiconductor layer having an amorphous structure is oxidized with an In-Ga-Zn-O-based metal. It is formed by a sputtering method using an object target.

The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more. More preferably, it is 99.9% or more. Use a metal oxide target with high relative density Thereby, it is possible to form an oxide semiconductor layer having a dense structure.

The forming atmosphere of the oxide semiconductor film 530 is a rare gas (typically argon) atmosphere and an oxygen atmosphere. It is preferable to use a mixed atmosphere of gas or a rare gas (typically argon) and oxygen. .. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides have a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere that has been removed to a concentration of 10 ppb or less (preferably 10 ppb or less). Is.

When forming the oxide semiconductor film 530, for example, the treatment chamber kept in a reduced pressure state is subjected to treatment. Holds the object and the temperature of the object to be treated is 100 ° C or more and less than 550 ° C, preferably 200 ° C or more and 40 Heat the object to be treated so that it is 0 ° C or less. Alternatively, it is covered when the oxide semiconductor film 530 is formed. The temperature of the processed product may be room temperature (25 ° C ± 10 ° C (15 ° C or more and 35 ° C or less)). Soshi Then, while removing the water in the treatment chamber, introduce the sputter gas from which hydrogen and water have been removed. The oxide semiconductor film 530 is formed using the target. Half an oxide while heating the object to be treated By forming the conductor film 530, impurities contained in the oxide semiconductor layer can be reduced. it can. In addition, damage due to sputtering can be reduced. Removes moisture in the processing chamber Therefore, it is preferable to use an adsorption type vacuum pump. For example, Cryopump, Io Pumps, titanium sublimation pumps, etc. can be used. Also, turbopon A cold trap may be added to the cap. Exhaust using a cryopump, etc. By doing so, hydrogen, water, etc. can be removed from the processing chamber, so that the oxide semiconductor film 530 The concentration of impurities inside can be reduced.

As a condition for forming the oxide semiconductor film 530, for example, the distance between the object to be treated and the target 170mm, pressure 0.4Pa, direct current (DC) power 0.5kW, atmosphere is oxygen (oxygen) 100%) atmosphere, or argon (100% argon) atmosphere, or oxygen and argon Conditions such as a mixed atmosphere can be applied. In addition, pulse direct current (DC) power supply When used, powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness can be reduced. It is preferable because the distribution is uniform. The thickness of the oxide semiconductor film 530 is 1 nm or more and 50 nm or less. Below, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. .. By using the oxide semiconductor film 530 with such a thickness, the short channel effect due to miniaturization It is possible to suppress. However, applicable oxide semiconductor materials and applications of semiconductor devices Since the appropriate thickness varies depending on the material used, the thickness should be selected according to the material used and the application. You can also do it.

Before forming the oxide semiconductor film 530 by the sputtering method, argon gas is introduced. The surface of the formed surface (for example, the surface of the gate insulating layer 507) is subjected to reverse sputtering to generate plasma. ) Is preferable to remove the deposits. Here, reverse sputtering is the odor of ordinary sputtering. Where the ions collide with the sputter target, conversely, the ions are struck on the treated surface. It refers to a method of modifying the surface by poking. Ions collide with the treated surface As a method of making it, a high frequency voltage is applied to the surface side of the treatment under an argon atmosphere, and the object to be treated is attached. There is a method to generate plasma nearby. In addition, instead of the argon atmosphere, nitrogen and helium , Oxygen or the like may be applied.

Next, the oxide semiconductor film 530 is subjected to an island-shaped oxide semiconduct by a second photolithography step. Process into body layer. The resist mask used in the photolithography process is ink. It may be formed by the jet method. When the resist mask is formed by the inkjet method, the photoma Since no desk is used, the manufacturing cost can be reduced.

When a contact hole is formed in the gate insulating layer 507, the process is an oxide semiconductor. It can be performed at the same time as the processing of the film 530.

Etching of the oxide semiconductor film 530 may be dry etching or wet etching. Alternatively, both may be used. For example, it is used for wet etching of the oxide semiconductor film 530. As the etching solution, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. .. Further, ITO 07N (manufactured by Kanto Chemical Co., Inc.) may be used.

After that, the oxide semiconductor layer is heat-treated (first heat treatment), and the oxide semiconductor layer 53 is subjected to heat treatment. Get 1 (see Figure 11 (B)). Excess water in the oxide semiconductor layer due to this first heat treatment Removes elements (including water and hydroxyl groups), prepares the structure of the oxide semiconductor layer, and is in the energy gap. Defect level can be reduced. The temperature of the first heat treatment is, for example, 300 ° C or higher 55 It shall be less than 0 ° C, or 400 ° C or more and 500 ° C or less.

For heat treatment, for example, the object to be processed is introduced into an electric furnace using a resistance heating element or the like, and the object to be treated is placed in a nitrogen atmosphere. It can be done at 450 ° C for 1 hour. During this time, the oxide semiconductor layer is exposed to the atmosphere. Do not allow water or hydrogen to enter.

The heat treatment device is not limited to an electric furnace, but heat conduction or heat radiation from a medium such as heated gas. Depending on the situation, a device for heating the object to be processed may be used. For example, LRTA (Lamp Ra) pid Thermal Anneal) device, GRTA (Gas Rapid The) RTA (Rapid Thermal Anneal) for rmal Anneal equipment, etc. ) The device can be used. LRTA equipment is halogen lamp, metal halide run Xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp It is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from a lamp such as a lamp. .. The GRTA device is a device that performs heat treatment using a high-temperature gas. As gas, al A rare gas such as gon, or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment. The body is used.

For example, as the first heat treatment, the object to be treated is placed in a heated inert gas atmosphere for several minutes. After heating for a while, GRTA treatment may be performed to take out the object to be treated from the inert gas atmosphere. .. The GRTA treatment enables high temperature heat treatment in a short time. In addition, the heat resistant temperature of the object to be treated It can be applied even under temperature conditions exceeding degrees. During the treatment, the inert gas was replaced with oxygen. You may switch to a gas containing. By performing the first heat treatment in an atmosphere containing oxygen, This is because the defect level in the energy gap due to oxygen deficiency can be reduced. ..

The inert gas atmosphere includes nitrogen or a rare gas (helium, neon, argon, etc.). ) Is the main component, and it is desirable to apply an atmosphere that does not contain water, hydrogen, etc. I'm sorry. For example, nitrogen to be introduced into a heat treatment device or a rare gas such as helium, neon, or argon. Purity is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

In any case, the first heat treatment reduces impurities and is type i (intrinsic semiconductor) or type i. By forming an oxide semiconductor layer that is as close to as possible, a transistor with extremely excellent characteristics can be realized. Can be revealed.

By the way, since the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., The heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, or the like. The dehydration treatment , Dehydrogenation treatment is performed after the oxide semiconductor film 530 is formed and before it is processed into an island-shaped oxide semiconductor layer. It is also possible to do it in. In addition, such dehydration treatment and dehydrogenation treatment can be performed at once. It is not limited to this, and it may be performed multiple times.

In addition to the above, the first heat treatment is performed after forming the source electrode layer and the drain electrode layer. After forming the insulating layer on the source electrode layer and the drain electrode layer, the row is performed at a timing such as. I can.

Next, the source electrode layer and the dray are placed on the gate insulating layer 507 and the oxide semiconductor layer 531. A conductive film to be an electrode layer (including wiring formed of the same layer) is formed. Source electrode As the conductive film used for the layer and the drain electrode layer, the material shown in the above embodiment is used. Can be used.

A resist mask is formed on the conductive film by the third photolithography step, and selectively pressed. After ching is performed to form the source electrode layer 515a and the drain electrode layer 515b, the resist is formed. Remove the mask (see Figure 11 (C)).

For exposure during resist mask formation in the third photolithography process, ultraviolet rays or KrF It is advisable to use laser light or ArF laser light. The channel length (L) of the transistor is the same. It is determined by the distance between the base electrode layer and the drain electrode layer. Therefore, the channel length (L) is For exposure during mask formation used for manufacturing transistors of less than 25 nm, several nm to several tens of n It is desirable to use Extreme Ultraviolet, which has a short wavelength of m. I'm sorry. Exposure with ultra-ultraviolet rays has a high resolution and a large depth of focus. Therefore, it will be formed later The channel length (L) of the transistor should be 10 nm or more and 1000 nm (1 μm) or less. It is also possible to increase the operating speed of the circuit. Also, due to miniaturization, it is half It is also possible to reduce the power consumption of the conductor device.

In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, multiple floors The etching step may be performed using a resist mask formed by the adjustment mask. Many Resist masks formed using gradation masks have regions of different thickness and are etched. Since the shape can be further deformed by doing this, it is possible to process multiple patterns into different patterns. It can be used in a number of etching steps. Therefore, with one multi-tone mask, less At a minimum, resist masks corresponding to two or more different patterns can be formed. As a result, the number of exposure masks can be reduced, and the corresponding photolithography process is also reduced. Since the number can be reduced, the process can be simplified.

When etching the conductive film, the oxide semiconductor layer 531 is divided by etching. It is desirable to optimize the etching conditions so that this does not occur. However, conductive The condition that only the film is etched and the oxide semiconductor layer 531 is not etched at all is obtained. It is difficult to do so, when etching the conductive film, a part of the oxide semiconductor layer 531 is etched. A groove (recess) may be formed.

Either wet etching or dry etching may be used for etching the conductive film. I. From the viewpoint of miniaturization of the device, it is preferable to use dry etching. D The etching gas and etching solution can be appropriately selected according to the material to be etched. Wear. In this embodiment, a titanium film is used as the conductive film, and the oxide semiconductor layer 531 is made of In. -Since Ga-Zn-O material is used, for example, when applying wet etching As an etchant, ammonia overwater (31% by weight hydrogen peroxide solution: 28% by weight ammo) Near water: water = 5: 2: 2) can be used.

Then nitrous oxide (N₂O), nitrogen (N)₂), Or a gas such as argon (Ar) The existing plasma treatment was performed to remove hydrogen and water adhering to the surface of the exposed oxide semiconductor layer. It is desirable to remove it. When performing the plasma treatment, the condition is that it does not come into contact with the atmosphere after the treatment. , An insulating layer 516 serving as a protective insulating film is formed.

The insulating layer 516 has a film thickness of at least 1 nm or more, and water is applied to the insulating layer 516 by a sputtering method or the like. It is desirable to form it by a method that does not mix impurities such as hydrogen and hydrogen. Insulation layer 516 When hydrogen is contained, it invades the oxide semiconductor layer of hydrogen and is contained in the oxide semiconductor layer by hydrogen. The back channel of the oxide semiconductor layer has a lower resistance (n-type) due to the extraction of oxygen from the oxide semiconductor layer. This is because parasitic channels may be formed. In addition, the insulating layer 516 is covered with oxide. Recon film, silicon nitride film, aluminum oxide film, or aluminum nitride film It is desirable to use.

In the present embodiment, a silicon oxide film having a film thickness of 200 nm is used as the insulating layer 516 by a sputtering method. Is used to form a film. The substrate temperature at the time of film formation may be room temperature (25 ° C) or higher and 300 ° C or lower. , In this embodiment, it is set to 100 ° C. The film formation of the silicon oxide film by the sputtering method is a rare gas. In an atmosphere (typically argon), in an oxygen atmosphere, or in a mixed atmosphere of rare gas and oxygen Can be done at. Also, as a target, silicon oxide target or silicon Target can be used.

As in the case of forming the oxide semiconductor film 530, the residual moisture in the film forming chamber of the insulating layer 516 is removed. Therefore, it is preferable to use an adsorption type vacuum pump (cryopump or the like). Cry Impurities contained in the insulating layer 516 are formed by forming a film in a film forming chamber exhausted using an opump. Can reduce the concentration of. In addition, an exhaust device for removing residual moisture in the film forming chamber of the insulating layer 516. As the stage, a turbo pump with a cold trap added may be used.

The sputter gas used to form the insulating layer 516 has high purity from which impurities such as hydrogen and water have been removed. It is desirable to be gas.

Next, the second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. Second heat treatment The temperature of is 200 ° C or more and 450 ° C or less, preferably 250 ° C or more and 350 ° C or less. Example For example, heat treatment may be performed at 250 ° C. for 1 hour in a nitrogen atmosphere. Performing a second heat treatment Therefore, it is possible to reduce the variation in the electrical characteristics of the transistor. Also, the insulating layer Oxygen in the oxide semiconductor layer 531 is supplied from 516 to the oxide semiconductor layer 531. Compensate for defects to form an i-type (intrinsic semiconductor) or oxide semiconductor layer that is as close as possible to i-type You can also do it.

In the present embodiment, the second heat treatment is performed after the formation of the insulating layer 516, but the second heat treatment is performed. The timing of the heat treatment is not limited to this. For example, a first heat treatment followed by a second heat treatment Or the first heat treatment may be combined with the second heat treatment.

As described above, the oxide semiconductor layer 531 is removed by the first heat treatment and the second heat treatment. It is possible to make it i-type (intrinsic) by purifying it so that impurities other than the main component of Wear.

The transistor 510 is formed by the above steps (see FIG. 11 (D)).

It is desirable to further form a protective insulating layer 506 on the insulating layer 516 (Fig. 11 (Fig. 11). See E)). The protective insulating layer 506 prevents the intrusion of hydrogen, water, etc. from the outside. Out of protection As the edge layer 506, for example, a silicon nitride film, an aluminum nitride film, or the like can be used. it can. The film forming method is not particularly limited, but the RF sputtering method has good mass productivity, so that it is protected and insulated. Suitable as a film forming method for layer 506.

After forming the protective insulating layer 506, further, in the atmosphere, 100 ° C or more and 200 ° C or less, 1 The heat treatment may be performed under the conditions of time or more and 30 hours or less.

As described above, the tiger containing the highly purified oxide semiconductor layer produced by using the present embodiment. The engineer has a feature that the off-current is extremely small. Because of this, this transition By using the star, it becomes easy to hold the potential of the node. Therefore, this is a pulse signal output Malfunction of pulse signal output circuit and shift register by using it for power circuit and shift register The probability of

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 6) The display function is displayed by using the shift register shown as an example in the above-described first to third embodiments. A semiconductor device (also referred to as a display device) having the semiconductor device can be manufactured. Also part of the drive circuit Alternatively, the whole can be integrally formed on the same substrate as the pixel part to form a system-on-panel. it can.

Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements) and light emitting elements (light emitting). A display element) can be applied. The light emitting element is bright depending on the current or voltage. Is included in the category, specifically, inorganic EL (Electro Lu). minescence), organic EL, etc. are included. Also, for electrical action such as electronic ink A display medium having a more variable contrast can also be applied.

In FIG. 12A, so as to surround the pixel portion 4002 provided on the first substrate 4001. Then, the sealing material 4005 is provided, and the first substrate 4001 and the second substrate 4006 It is sealed. In FIG. 12 (A), the sealing material 4005 on the first substrate 4001 Therefore, the scanning line drive circuit 40 is placed on a separately prepared substrate in an area different from the enclosed area. 04, signal line drive circuit 4003 is mounted. In addition, a separately formed signal line drive circuit 4 Various signals and potentials given to 003 and the scanning line drive circuit 4004 or the pixel unit 4002. Is FPC (Flexible printed circuit) 4018a, 401 Supplied from 8b.

In FIGS. 12 (B) and 12 (C), the pixel portion 40 provided on the first substrate 4001. A sealing material 4005 is provided so as to surround the 02 and the scanning line drive circuit 4004. To. In addition, a second substrate 4006 is provided on the pixel section 4002 and the scanning line drive circuit 4004. It has been. Therefore, the pixel unit 4002 and the scanning line drive circuit 4004 are connected to the first substrate 4001. It is sealed together with the display element by the sealing material 4005 and the second substrate 4006. In FIGS. 12 (B) and 12 (C), the sealing material 4005 on the first substrate 4001 is used. Therefore, the signal line drive circuit 40 is placed on a separately prepared board in an area different from the enclosed area. 03 is implemented. In FIGS. 12 (B) and 12 (C), separately formed signals Various types given to the line drive circuit 4003 and the scanning line drive circuit 4004 or the pixel unit 4002. Signals and potentials are sourced from FPC4018.

Further, in FIGS. 12 (B) and 12 (C), the signal line drive circuit 4003 is separately formed. An example of mounting on the first board 4001 is shown, but the configuration is not limited to this. Scan line The drive circuit may be formed and mounted separately, or a part of the signal line drive circuit or the scan line drive circuit. Only a part of the above may be separately formed and mounted.

The method of connecting the separately formed drive circuit is not particularly limited, and COG (Ch) is not particularly limited. ip On Glass) method, wire bonding method, or TAB (Tape A) The utomated Bonding) method or the like can be used. Figure 12 (A) shows This is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by the COG method. , Fig. 12 (B) is an example of mounting the signal line drive circuit 4003 by the COG method, and Fig. 1 2 (C) is an example of mounting the signal line drive circuit 4003 by the TAB method.

Further, the display device includes a panel in which the display element is sealed and a controller on the panel. Includes modules that are equipped with ICs and the like.

The display device in the present specification is an image display device, a display device, or an optical device. Refers to the source (including lighting equipment). Also, if a connector, such as FPC or TAB tape, Or a module with TCP attached, a printed wiring board at the end of TAB tape or TCP An IC (integrated circuit) is directly mounted on the provided module or display element by the COG method. All the modules are included in the display device.

Further, the pixel portion provided on the first substrate has a plurality of transistors, and the transition is provided. As a star, the transistor illustrated in the previous embodiment may be applied.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, or a polymer liquid Crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. are used. These liquid crystal materials , Cholesteric phase, smectic phase, cubic phase, chiral nematic phase, depending on the conditions Indicates the phase, isotropic phase, etc.

Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases Yes, when the temperature of the cholesteric liquid crystal is raised, the direct transition from the cholesteric phase to the isotropic phase It is a previously expressed phase. The blue phase is expressed only in a narrow temperature range, which improves the temperature range. Therefore, it is preferable to use a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed of 1 msec or less. In addition, since it is optically isotropic, no orientation treatment is required, and the viewing angle dependence is small. Also, the alignment film Since it is not necessary to provide the rubbing process, the rubbing process becomes unnecessary. Therefore, it is pulled by the rubbing process. It is possible to prevent electrostatic breakdown caused by defects and damage of the liquid crystal display device during the manufacturing process. Can be mitigated. Therefore, it is possible to improve the productivity of the liquid crystal display device.

The inherent resistance of the liquid crystal material is 1 x 10.⁹Ω · cm or more, preferably 1 × 10¹¹Ω · cm or more, more preferably 1 × 10¹²Ω cm or more. In addition, this specification The value of the intrinsic resistance in the document shall be the value measured at 20 ° C.

The size of the holding capacity provided in the liquid crystal display device is the size of the transistor arranged in the pixel section. It is set so that the electric charge can be retained for a predetermined period in consideration of the current and the like. Large holding capacity The size may be set in consideration of the off-current of the transistor and the like.

The liquid crystal display device has TN (Twisted Nematic) mode and IPS (In-P). lane-Switching) mode, FFS (Fringe Field Swit) ching) mode, ASM (Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui) d Crystal) mode, AFLC (Anti Ferroelectric Liq) uid Crystal) mode etc. is used.

In addition, a normally black type liquid crystal display device, for example, a vertical orientation (VA) mode was adopted. It may be a transmissive liquid crystal display device. The VA type liquid crystal display device is the liquid crystal of the liquid crystal display panel. It is a type of method that controls the arrangement of molecules. A voltage is applied to the VA type liquid crystal display device. This is a method in which the liquid crystal molecules face the panel surface in the vertical direction when there is no liquid crystal molecule. In vertical orientation mode For example, MVA (Multi-Domain Verti) cal Alignment) mode, PVA (Patterned Vertical) Alignment) mode, ASV mode, etc. can be used. Also, pixels ( Divide the pixel) into several areas (subpixels) and defeat the molecules in different directions. Use a method called multi-domain or multi-domain design that has been devised be able to.

Further, in a display device, a black matrix (light-shielding layer), a polarizing member, a retardation member, and reflection An optical member (optical substrate) such as a preventive member is appropriately provided. For example, polarizing boards and retardation groups Circular polarization by a plate may be used. Also, use a backlight, side light, etc. as a light source. You may.

Further, as the display method in the pixel section, a progressive method, an interlaced method, or the like is used. be able to. In addition, as a color element controlled by pixels when displaying in color, RGB (R is It is not limited to the three colors (red, G stands for green, and B stands for blue). For example, RGBW (W stands for white) , Or RGB with one or more colors such as yellow, cyan, and magenta added. In addition, it should be noted. The size of the display area may be different for each dot of the color element. However, the invention to be disclosed Is not limited to color display devices, but applies to monochrome display devices. You can also do it.

In addition, a luminescent element that uses electroluminescence as a display element included in a display device. Children can be applied. Light emitting elements that utilize electroluminescence are light emitting materials. Is distinguished by whether it is an organic compound or an inorganic compound, and in general, the former is organic E. The L element and the latter are called inorganic EL elements.

In an organic EL element, by applying a voltage to the light emitting element, electrons and positives are transmitted from a pair of electrodes. Each of the pores is injected into a layer containing a luminescent organic compound and an electric current flows through it. And those keys The recombination of carriers (electrons and holes) causes the luminescent organic compound to form an excited state. It forms and emits light when its excited state returns to the ground state. From the mechanism, such a departure The optical element is called a current-excited light-emitting element.

The inorganic EL element is divided into a dispersed inorganic EL element and a thin film type inorganic EL element depending on the element configuration. It is similar. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels. Ccepter recombination type luminescence. In the thin film type inorganic EL element, the light emitting layer is sandwiched between the dielectric layers, Furthermore, it has a structure in which it is sandwiched between electrodes, and the emission mechanism utilizes the inner-shell electronic transition of metal ions. Localized light emission to be used.

It is also possible to provide electronic paper that drives electronic ink as a display device. To. Electronic paper is also called an electrophoresis display device (electrophoresis display), and is paper. It has the same readability as, low power consumption compared to other display devices, and can be made thinner and lighter. It has the advantage of.

The electrophoresis display device can be in various forms, but with the first particle having a positive charge. Multiple microcapsules in solvent or solute, including, with a second particle with a negative charge It is dispersed, and by applying an electric field to the microcapsules, microcapsules It is also possible to move the particles in the cell in opposite directions and display only the color of the particles gathered on one side. It is. The first particle or the second particle contains a dye and is transferred when there is no electric field. It doesn't work. Also, the color of the first particle and the color of the second particle are different (including colorless). ).

In this way, in the electrophoresis display device, a substance with a high dielectric constant moves to an electric field region with a high dielectric constant, so to speak. It is a display that utilizes the loose dielectrophoretic effect.

The microcapsules dispersed in a solvent are called electronic inks. Electronic ink can be printed on the surface of glass, plastic, cloth, paper, etc. Also Color display is also possible by using a color filter or particles having a dye.

The first particles and the second particles in the microcapsules include a conductor material and an insulator material. , Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electroluminescence A coutrochromic material, a type of material selected from magnetic electrophoretic materials, or a composite of these materials Should be used.

In addition, as electronic paper, a display device that uses a twist ball display method can also be applied. it can. The twist ball display method uses spherical particles painted in black and white for the display element. It is arranged between the first electrode layer and the second electrode layer, which are the existing electrode layers, and is arranged between the first electrode layer and the second electrode layer. A method of displaying by controlling the orientation of spherical particles by causing a potential difference in the electrode layer. is there.

The pulse signal output times shown in the first embodiment or the second embodiment are displayed on the display device exemplified above. By applying the road, it is possible to provide a display device having various functions.

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

(Embodiment 7) The semiconductor device disclosed in this specification shall be applied to various electronic devices (including game machines). Can be done. Electronic devices include, for example, television devices (televisions, or televisions). Receivers), monitors for computers, digital cameras, digital video cameras Cameras such as LA, digital photo frames, mobile phones (also known as mobile phones and mobile phone devices) C), portable game machines, mobile information terminals, sound playback devices, pachinko machines, and other large game machines. Which can be mentioned.

FIG. 13 (A) is manufactured by mounting the semiconductor device disclosed in the present specification as at least one component. It is a notebook type personal computer, and the main body 3001, the housing 3002, and the display unit 3 It consists of 003, keyboard 3004, etc.

FIG. 13B is made by mounting the semiconductor device disclosed in the present specification as at least one component. It is a personal digital assistant (PDA), and the main body 3021 has a display unit 3023 and an external interface. A face 3025 and an operation button 3024 are provided. Also as an accessory for operation There is a stylus 3022.

Further, the semiconductor device disclosed in the present specification can be applied as an electronic paper. Figure 13 (C) is an electronic book produced by mounting the electronic paper as one component. Figure 13 ( C) shows an example of an electronic book. For example, the e-book 2700 has a housing 2701 and It consists of two housings, the housing 2703 and the housing 2703. The housing 2701 and the housing 2703 are shafts. It is integrated by the part 2711, and it is possible to open and close the shaft part 2711 as an axis. Wear. With such a configuration, it is possible to perform an operation like a paper book.

The display unit 2705 is incorporated in the housing 2701, and the display unit 2707 is assembled in the housing 2703. It is included. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. It may be configured to display different screens. Configure to display different screens So, for example, the text is displayed on the right display (display 2705 in Fig. 13 (C)), and the text is displayed on the left. An image can be displayed on the display unit (display unit 2707 in FIG. 13C).

Further, FIG. 13 (C) shows an example in which the housing 2701 is provided with an operation unit and the like. For example The housing 2701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. I have. The page can be sent by the operation key 2723. The same as the display part of the housing A keyboard, a pointing device, or the like may be provided on the surface. Also, of the housing External connection terminals (earphone terminal, USB terminal, etc.), recording medium insertion part, etc. on the back or side It may be configured to include. Furthermore, the electronic book 2700 has a function as an electronic dictionary. It may be configured as a set.

Further, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By radio Purchase desired book data, etc. from the e-book server and download it. Is also possible.

FIG. 13 (D) is manufactured by mounting the semiconductor device disclosed in the present specification as at least one component. It is a mobile phone, and is composed of two housings, a housing 2800 and a housing 2801. Case Body 2801 includes display panel 2802, speaker 2803, microphone 2804, Pointing device 2806, camera lens 2807, external connection terminal 2808, etc. It has. In addition, the housing 2800 has a solar cell 28 that charges a portable information terminal. 10, equipped with external memory slot 2811, etc. Also, the antenna is inside the housing 2801. It is built in the part.

In addition, the display panel 2802 is equipped with a touch panel, and the image is displayed in Fig. 13 (D). Multiple operation keys 2805 are shown by dotted lines. Output with solar cell 2810 A booster circuit is also mounted to boost the voltage to be generated to the voltage required for each circuit.

The display direction of the display panel 2802 changes as appropriate according to the usage pattern. Also, the display panel Since the camera lens 2807 is provided on the same surface as the 2802, videophone calls are possible. To. Speaker 2803 and microphone 2804 are not limited to voice calls, but videophones, Recording and playback are possible. In addition, the housing 2800 and housing 2801 slide and show. It can be changed from the unfolded state like 13 (D) to the overlapping state, which is suitable for carrying. It is possible to reduce the size.

External connection terminal 2808 can be connected to various cables such as AC adapter and USB cable It is possible to charge and communicate data with a personal computer or the like. Also external By inserting a recording medium into the memory slot 2811, a larger amount of data can be stored and moved. I can handle it.

In addition to the above functions, even if it has an infrared communication function, a TV reception function, etc. Good.

FIG. 13 (E) is manufactured by mounting the semiconductor device disclosed in the present specification as at least one component. It is a digital video camera, the main body 3051, the first display part 3057, the eyepiece part 3053 , Operation switch 3054, 2nd display 3055, battery 3056, etc. Has been done.

FIG. 13 (F) shows a tele-device in which the semiconductor device disclosed in the present specification is mounted as at least one component. An example of a vision device is shown. On the television device 9600, it is displayed on the housing 9601. Part 9603 is incorporated. It is possible to display images by the display unit 9603. To. Further, here, the configuration in which the housing 9601 is supported by the stand 9605 is shown. ..

The operation of the television device 9600 is performed by the operation switch provided in the housing 9601 and the separate remote control. It can be done by a control machine. Also, from the remote control controller to the remote controller A display unit for displaying the information to be output may be provided.

The television device 9600 is configured to include a receiver, a modem, and the like. To the receiver It can receive more general TV broadcasts, and can be wired or wireless via a modem. One-way (sender to recipient) or two-way by connecting to a communication network It is also possible to perform information communication (between the sender and the receiver, or between the recipients, etc.).

As described above, the configurations, methods, etc. shown in the present embodiment are suitable with the configurations, methods, etc. shown in other embodiments. It can be used in any combination.

11 Signal line 12 signal line 13 signal line 14 signal line 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 31 Power line 32 power line 51 period 52 period 53 period 54 period 55 period 56 period 101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 111 transistor 200 pulse signal generation circuit 201 First input signal generation circuit 202 Second input signal generation circuit 203 Second input signal generation circuit 204 Dummy pulse signal generation circuit 205 1st input signal generation circuit 206 Second input signal generation circuit 400 board 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulation layer 409 Protective insulation layer 410 transistor 420 transistor 427 insulation layer 430 transistor 436a Wiring layer 436b Wiring layer 437 Insulation layer 440 transistor 505 board 506 Protective insulation layer 507 Gate insulating layer 510 transistor 511 Gate electrode layer 515a Source electrode layer 515b Drain electrode layer 516 Insulation layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 2700 e-book 2701 chassis 2703 chassis 2705 Display 2707 Display 2711 Shaft 2721 power supply 2723 Operation keys 2725 speaker 2800 housing 2801 housing 2802 display panel 2803 speaker 2804 microphone 2805 Operation keys 2806 Pointing device 2807 Camera lens 2808 External connection terminal 2810 solar cell 2811 External memory slot 3001 body 3002 housing 3003 Display 3004 keyboard 3021 body 3022 stylus 3023 Display 3024 Operation buttons 3025 External interface 3051 body 3053 Eyepiece 3054 Operation switch 3055 Display 3056 battery 3057 Display 4001 board 4002 pixel part 4003 Signal line drive circuit 4004 Scan line drive circuit 4005 Sealing material 4006 board 4018 FPC 4018a FPC 4018b FPC 9600 television equipment 9601 housing 9603 Display 9605 stand