Method and apparatus for processing a received signal in a communications system

Method and device for processing signals received in communication system

Background of the invention

Invention category

This invention relates to data communication. More particularly, the present invention relates to a method and device for effectively processing signals received in a communication system.

Related skills

In a typical digital communication system, data is processed, modulated, conditioned in the transmitting unit, and transmitted to the receiver unit. Data processing includes, for example, formatting the data into a special frame format, encoding the formatted data to provide error detection/correction in the receiver unit, encoding data channelization (in other words, covering), and Expand the channelized data and so on in the system bandwidth. Generally, the data processing is defined by the implemented system or standard.

At the receiver unit, it receives, conditionally processes, demodulates the transmission signal, and digitizes it to restore the transmission data. The processing in the receiver unit is complementary to the part that may be performed in the transmitter unit, for example, de-spreading the received samples, de-covering the de-spreading samples to generate a de-covering symbol, and decoding the de-covering symbol Wait. Because of multiple paths and other phenomena, the transmitted signal can reach the receiving unit via multiple signal paths. To improve performance, general receiver units are designed to have the ability to handle multiple received signals (and the strongest).

To perform the required signal processing, some traditional receiver units are designed with several processing elements, and each processing element is specially designed to perform a specific function. For example, a receiver unit can be designed with a searcher element and several data processing elements. This crawler meta The element searches for strong signal conditions in the received signal, and the data processing element is allocated to handle specific signal conditions with sufficient signal strength. The realization of multiple parallel processing elements will lead to increased circuit complexity and cost. Usually the processing element is a fixed design and does not provide programmable functions (for example, processing the received signal with different parameter value sets, for example, performing pre-processing, signal search, and data demodulation) . In addition, the number of signal situations that can be processed is limited by the number of processing elements implemented.

To reduce complexity, some other traditional receiver units are designed with several parallel front-end units coupled to a common data path processor. Each front-end unit will perform partial processing of the assigned signal conditions (for example, de-expand and de-cover). Then the shared data path processor will perform the remaining processing on the partially processed data (for example, perform demodulation and energy calculation with the preamble). Similarly, the limited number of signal conditions can be based on the number of front-end units implemented, and generally do not provide programmable functions.

For user terminals, the ability to handle many received signal conditions can improve performance. For the base, it is usually necessary to process multiple signals of multiple users at the same time, so effective signal processing technology is also required. For various reasons, the ability to process signals from multiple users with a small number of signal processing elements is both economical and technically demanding. For example, a higher board density, a smaller number of components, and a lower Cost etc. It is also desirable to use various parameter values determined by coefficients such as transmission rate (for example, various channelized codes with different lengths) to transmit data. Programmable ability to add signal processing elements to the communication system.

As can be seen, there is a great need for technologies that can effectively process signals received in communication systems.

Summary of the invention

The present invention provides a precision demodulator design with many advantages over traditional designs. According to a specific aspect of the present invention, a data processor is provided to perform many computationally intensive operations and a controller is provided to perform the remaining tasks (e.g., demodulation) required to process the received signal. This architecture allows the controller to manage the processing of many signal conditions and support multiple users at the same time. In some designs, a microcontroller is provided to perform the "micro-management" of the data processor and relieve the controller's management load related to the low-level sequence of the data processor. The plurality of various kinds of characteristics can be produced with a superior performance of conventional design improved simplified design.

The data processor and the controller can be designed to perform operations with a processing clock, which can be asynchronous, and usually faster than the sampling rate of the received samples. The faster processing clock can handle more received signal conditions without additional circuit complexity, and can also scale the processing throughput with the clock frequency. The data processor can also be designed to process data based on programmable parameter values, which provides higher flexibility and functionality. For example, the search time interval, channelization (for example, Walsh) coding, time offset, and other programming parameters can all be programmable. The data processor can also be designed to share the processing elements to reduce circuit complexity and cost.

A specific example of the present invention provides a method used in a wireless communication system (example For example, the user terminal of the CDMA system or the receiver unit of the base station. The receiver unit includes a first buffer coupled to the data processor. The first buffer will receive and store digitized samples at a special sampling rate (and can also store PN samples as de-expanded digitized samples). The data processor retrieves the digitized sampled section from the first buffer and processes the retrieved section with a special parameter value set. The data processor operates based on a processing clock with a frequency higher than (for example, ten times or higher) than the chip rate. The multiple situations of the received signal can be processed by retrieving and processing multiple digitized sample sections from the first buffer.

Usually, the receiver unit also includes a receiver and a controller. The receiver will receive and process a transmission signal to provide the digitized sample. The controller assigns work to the data processor and processes the signal information from the data processor.

The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator de-expands the extracted digitized sample section with the relative PN de-expansion sequence section to provide correlated samples. The symbol demodulator and combiner will receive and further process the correlated samples to provide processed symbols. The second buffer stores the processed symbol, and can be designed to provide de-interleaving of the processed symbol. In this type of design, the second buffer is divided into two or more parts, one part stores the processed symbols of the current packet and the other part stores the processed symbols of the previously processed packets. The second buffer can also be designed to store packet fragments. The symbol of the current packet will be processed and the previous packets Symbols will be provided to subsequent signal processing elements.

The correlator can be designed to include a de-expander, a second (sample) accumulator, and an interpolator, or a combination thereof. The de-expander includes a set of K multipliers that can be simultaneously de-expanded into K complex digitized sample groups. The sample accumulator includes a set of K summers coupled to K multipliers, and each adder receives and sums up samples from a separate set of multipliers. The interpolator receives and interpolates the de-expanded samples to generate interpolated samples.

The symbol demodulator and combiner can be designed to include a de-covering element, a preamble demodulator, and a third (symbol) accumulator, or a combination thereof. The de-covering element will receive and de-cover the associated samples with one or more channelization codes to provide de-covering symbols. The channelization code may be a Walsh code having a controllable length and defined by the parameter value. The preamble demodulator demodulates the uncovered symbol on the preamble symbol to provide a demodulated symbol. And the symbol accumulator will accumulate the processed symbols.

The de-covering element can be completed with a fast Hadamard transform (FHT) element with L stage, and can be designed to receive and process the in-phase and quadrature associated sampling in the exchange clock cycle . The FHT element can be designed to use one or more lengths of 1, 2, 4, 8, 16, 32, 64, or 128, or some other length (controllable) Walsh (Walsh) symbols to solve cover.

The first accumulator will receive and process the correlated samples to provide an accumulation result. The first accumulator can be designed to accumulate in a controllable time interval The correlated sampling provides an estimate of the leading signal. The first accumulator may include several accumulation elements, and each accumulation element is used to provide a leading signal estimation for a special time compensation.

The sampling rate is asynchronous to the processing clock. In this case, the controller can be designed to implement a delay-locked loop to track the chip rate of the digitized sample and provide a reset value, which is used to generate a signal which is then used to write the packet of the digitized sample Enter to the first buffer starting at the specified position.

The controller can be designed to maintain a time state machine for each processing signal instance. Each time state machine can be maintained by DSP firmware, and can include a time tracking loop used to (1) track the movement of the processed signal instance and (2) generate time compensation that matches the signal instance. The time compensation can be used to retrieve an appropriate sampling section from the first buffer for processing. The controller can also receive timing signals, which are used to start the processing of the sampling section. The timing signal is generated based on the comparison value provided by the controller.

The receiver unit also includes a microcontroller for receiving the work sent by the controller and generating a set of control signals to guide the operation of the elements in the receiver unit. For example, the microcontroller can be a working state machine for each processing task, and includes a sequence controller for receiving one or more indication signals and sending tasks and generating the control signal group.

Another embodiment of the present invention provides a method for processing signals received in a wireless communication system. According to this method, a transmission signal is received, processed, and digitized to provide digitized sampling with a special sampling rate. Then the digitized sample is buffered in the first buffer, and the digitized sample section is retrieved from the first buffer and processed with a set of special parameter values, some of which are programmable. The processing is based on a processing clock with a frequency higher than the sampling rate.

The processing includes the following combination (1) unexpanding the extracted digitized sample section with the relevant PN unwrapping sequence to provide correlated samples, (2) uncovering the correlated samples with one or more channelization codes , (3) the leading symbol demodulates the uncovered symbol to provide a demodulated symbol, and (4) accumulates the demodulated symbol from multiple signal instances to provide a processed symbol.

The characteristics, essence, and advantages of the present invention can be better understood from the detailed description given below by referring to the drawings. The same symbols represent the same parts: Figure 1 is a simplified block diagram of a communication system; Figure 2 is shown Is a block diagram of a specific concrete example of a receiver unit that is suitable for receiving and processing modulated signals; Figure 3 shows the format of the data frame transmitted to the connection before the high data rate (HDR) CDMA system; Figure 4 The block diagram shown is a specific example block diagram of the receiving data processor that can be used to process the previous transmission to the connection in the HDR CDMA system; FIG. 5 is a block diagram of a specific specific example of the data processor of the present invention; FIG. 6A and The diagrams shown in 6B are respectively writing samples to the buffer and reading samples from the buffer, and writing PN samples to the buffer and reading PN samples from the buffer; Fig. 6C shows a block diagram of a specific concrete example of the data buffer of the receiver design shown in Figs. 2 and 5; Fig. 7A shows a block diagram of a specific concrete example of the correlator in the data processor of Fig. 5 Figure; Figure 7B is a block diagram of a specific specific example of a multiplier that can perform complex number solution expansion; Figure 7C is a diagram of linear interpolation; Figure 7D is a specific specific example of an interpolator The block diagram; Fig. 8A is a block diagram of specific examples of the symbol demodulator and combiner inside the data processor of Fig. 5; Fig. 8B is a block diagram of a fast Hadamard transform (FHT) element A block diagram of a specific specific example; Figure 8C is a block diagram of a specific specific example of a leading demodulator; Figure 9 is a specific example of an accumulator used to process flow data, leading reference, and other signal data A block diagram of a specific example; Fig. 10 is a block diagram of a specific specific example of a microcontroller that can be used to control the operation of the elements of the receiver unit; and the time compensation shown in Figs. 11A and 11B is zero, respectively And 1.5 timing diagram for data sampling processing of data processor.

Detailed description of specific concrete examples

FIG. 1 shows a simplified block diagram of a specific example of signal processing for data transmission in the communication system 100. In the transmitter unit 110, data is transmitted from the data source 112, usually in packets, to the transmission (TX) data processor 114 It will format, encode, and process the data to generate a baseband signal. The baseband signal is then provided to a transmitter (TMTR) 116, quadrature modulated, filtered, amplified, and up-converted to generate a modulated signal that is transmitted to one or more receiver units via the antenna 118.

In the receiver unit 130, the transmission signal is received by the antenna 132 and provided to the receiver (RCVR) 134. In the receiver unit 134, the received signal is amplified, filtered, down converted, quadrature demodulated into a fundamental frequency, and digitized to provide in-phase (I) quadrature (Q) sampling. The sample is provided to the receiving (RX) data processor 136 and decoded and processed to restore the transmitted data. The decoding and processing at the receiver unit 130 are complementary to the decoding and processing performed at the transmitting unit 110. Then the restored data will be provided to a data slot 138.

The above-mentioned signal processing supports one-way packet data, information, voice, video transmission, and other communication types. The two-way communication system supports two-way data transmission. However, for the sake of simplicity, the figure does not show signal processing in other directions.

The communication system 100 may be a code division multiplexing (CDMA) system or other multiple access communication system that supports voice and data communication between users through a land connection. The use of CDMA technology in multiple access communication systems is disclosed in US Patent No. 4,901,307, titled "SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS," and US Patent No. 5,103,459, titled "SYSTEM AND METHOD FOR GENERATING WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM". Another specific CDMA system is disclosed in U.S. Patent Application Serial No. 08/963,386, entitled "METHOD AND APPARATUS FOR HIGH RATE PACKET DATA TRANSMISSION," filed on November 3, 1997. These The patent case and patent application case are assigned to the assignee of the present invention, and are incorporated herein by reference.

CDMA systems are typically designed to comply with one or more standards, such as "TIA/EIA/IS-95-A Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Celluar System" (hereinafter referred to as IS -95-A standard), "TIA/EIA/IS-98 Recommanded Minimum Standard for Dual-Mode Wideband Spread Spectrum Celluar, Mobile Station" (hereafter referred to as IS-98 standard), which is called the standard provided by the joint organization It is "3rd Generation Partnership Project" (3GPP) and is embodied in a set of documents numbered 3G TS 25.211, 3G TS 25.212, 3G TS 25.213, and 3G TS 25.214 (hereinafter referred to as W-CDMA) documents, and "TR-45.5 Physical Layer Standard for CDMA2000 Spread Spectrum System" (hereinafter referred to as CDMA-2000 standard). New CDMA standards will continue to be proposed and used. These CDMA standards will be referenced here.

FIG. 2 shows a block diagram of a specific example of a receiver unit 200 suitable for receiving and processing modulated signals. The receiver unit 200 is a specific embodiment of the receiver unit 130 in FIG. 1. The modulated signal will be received by the antenna 212 and provided to a front-end unit 214. In the front-end unit 214, the received signal is amplified, filtered, frequency down-converted, and quadrature demodulated to provide a fundamental frequency. Then the baseband signal will use one or more A frequency analog-to-digital converter (ADC) and a sampling clock SCLK are digitized to generate in-phase (I_A_D_C) And quadrature (Q_A_D_C) The sampling is provided to the data interface circuit 222. The front-end unit 214 and the ADC 216 can be implemented in the receiver 134 of FIG. 1.

With the change of the special design of the receiver unit 200, the ADC 216 can provide a high sampling rate I_A_D_CAnd Q_A_D_CSampling and receiving relative signals from one or more antennas. The data interface circuit 222 may substantially eliminate (in other words, remove) unnecessary samples, arrange (in other words, sort) the samples that match each antenna, and combine the samples into words suitable for efficient storage in the buffer 224. In a specific example, each word group includes 32 bits of data, and each I_A_D_COr Q_A_D_CThe sample includes 4 bits of data, and there are four pairs of I in each word group_A_D_CAnd Q_A_D_Csampling. Other word widths (for example, 16-bit, 64-bit, 128-bit, etc.) can be used and are encompassed within the scope of the present invention. When the word storage is available, the address generator 220 generates a data write address DW_ADDR and writes the data generated by the word write to the buffer 224 at the location specified by the address.

Then the data processor 230 retrieves samples from the buffer 224, the controller 240 instructs the processing of the retrieved samples, and provides the processed symbols to the buffer/de-interleaver 234. The data processor 230 can then retrieve the symbols from the buffer/de-interlacer 234 and accumulate the symbols from the multiple signal instances to provide the accumulated symbols to be sent back to the buffer/de-interlacer 234. When the demodulated symbol can be retrieved from the buffer/deinterlacer 234, the address generator 236 generates a symbol read address SR_ADDR and provides the symbol to the decoder 260. The data processor 230 can also directly provide the processed signal data to the controller 240. untie The encoder 260 decodes the demodulated symbol according to a decoding technique complementary to the encoding technique used in the transmission unit and provides the decoded data to the data slot 262.

Generally, the data processor 230 includes a correlator, an accumulator, a symbol demodulator (multiplier), and a combiner, or a combination thereof, which is determined by the special design of the data processor. The data processor 230 performs many functions required for demodulating the received samples. The data processor 230 may be designed to directly provide demodulated symbols to the decoder 260 for decoding and directly provide processed signal data to the controller 240 for further processing. This type of processed signal data includes, for example, forward reference and data rate control (DRC) symbol accumulation for reverse connection processing, and power control for forward connection processing.

The controller 240 can be designed to perform various functions, such as leading filtering, finger lock detection, time tracking of each processed signal, finger time compensation maintenance, frequency tracking (forward connection processing for remote terminals), or Its combination. The controller 240 also instructs the data processor 230 and the buffer/de-interval inserter 234 to perform the desired functions.

In some designs, the microcontroller 232 is used to direct the operation of the data processor 230. In this type of design, the microcontroller 232 receives instructions or commands from the controller 240 to perform special tasks (for example, perform one or all of the associations of assigned fingers). Then the microcontroller 232 instructs the data processor 230 and other units (for example, the buffer 224, the buffer/de-interpolator 234) to perform the operations. The microcontroller 232 can reduce the number of management required by the controller 240 and the controller 240 and other elements Interaction between. So the microcontroller 230 can release the controller 240 and enable it to support additional channels/users.

For the design shown in FIG. 2, the number of users can be scaled with the frequency of the clock signal provided to the data processor 230 and the controller 240. The two clocks are independent and related to their special frequencies. Usually one of the clocks will limit the number of signal instances/users that can be supported.

The clock generator 218 generates the sampling clock SCLK of the ADC 216 and other clocks in the receiver unit 200. In a specific example, the clock generator 218 includes a free-running clock source for generating a main clock signal and one or more real-time clock counters (and/or phase-locked loops) for Generate clock signals used by other elements in the receiver unit 200. The free clock source can be realized by a voltage-controlled crystal vibrator or other types of vibrators. The real-time clock counter is triggered by the main clock signal and generates a lower frequency clock signal that is synchronized with the main clock signal. Such clock signals include ADC sampling clock SCLK, data processor clock PCLK, address generator 220 and 236 clocks, etc. In a specific example, the sampling clock SCLK is derived from the main clock signal and has a frequency close to the chip rate of the received signal (but does not need to be locked).

In a specific example, the address generator 220 includes a data write address generator that generates a data write address DW_ADDRESS and a data read address generator that generates a data read address DR_ADDR. The address generator 220 also includes other address generators that can also store data (PN sequence) in the buffer 224. In a specific example, the address generator 236 It includes a symbol write address generator for generating the symbol write address SW_ADDRESS and a symbol read address generator for generating the symbol read address SR_ADDR. The address generators 220 and 236 are described in further detail as follows.

The implementation and operation of the receiver 200 metatable are described in further detail as follows.

According to the present invention, the design of the data processor 230 and the controller 240 has a set of characteristics that provide performance and efficiency improvements over traditional data processing units. Some features are briefly described as follows.

First, the data processor 230 performs many computationally intensive operations so that the controller 240 can support many users at the same time. The data processor 230 may be designed to perform processing required for receiving data and directly provide the demodulation symbols to the decoder 260. Therefore, the controller 240 can reduce intensive data processing (for example, dot product computation), which is usually required by more complex controllers in traditional designs and traditionally prevents the controller from supporting multiple users at the same time Or process multiple signal instances. In addition, the microcontroller 232 can perform the "micro-management" of the data processor 230 and reduce the general management burden of the controller 240.

Second, each data processor 230 and controller 240 can use a pulse signal that is asynchronous at, and usually faster than, the sampling rate of the samples stored in the buffer 224 for calculations. For example, it can be selected to be twice the chip rate of the received signal (in other words, f_s_a_m<img file="TW595149B_D0001.tif" />2.4 Msps) and the size of the clock signal PCLK can be selected to be one level faster than the sampling rate (in other words, f_P_C_L_K&gt;50 MHz). If the data processor 230 and the controller 240 are used in the user terminal, the faster clock signal can be processed more quickly. Multiple examples of receiving signals. In this example, the data processor 230 and the controller 240 can be used to support more finger of rake receivers without additional circuit complexity. If the processor 230 and the controller 240 are used in a base station, the faster clock signal can process received signals from more users and/or more received signal instances.

Third, each data processor 230 and controller 240 can be designed to process data based on programmable parameter values. For example, the controller 240 may select the number of samples to be accumulated and provide it to the data processor 230 during the search. As another example, the data processor 230 can use one or more programmable length channelization codes to decover the samples. On the contrary, the design of traditional receivers usually includes dedicated hardware elements that execute a specific small part of the workgroup with little or no programming capabilities. The programmable feature of the present invention can improve the performance better than the traditional design.

Fourth, the data processor 230 and the controller 240 can be designed to share a common place to reduce circuit complexity and cost. Each data processor 230 and controller 240 usually includes a set of processing elements to perform various required functions (for example, de-expansion, de-covering, accumulation, and demodulation before the data processor 230, and before the controller 240 Guide recovery and time tracking). In order to perform a special task on a sampling section, only the processing elements required for the task are activated and the remaining elements are closed or skipped. The processing elements in each data processor 230 and controller 240 are generally not copied, unless it is an example of parallel processing to further improve performance. On the contrary, the design of traditional receivers usually includes duplication of multiple functions, which will increase circuit complexity and cost.

The data processor 230 can be designed to process data transmission according to various CDMA standards and systems. For the sake of clarity, the present invention will now describe the specific CDMA system described in the aforementioned US Patent Application Serial No. 08/963,386, hereinafter referred to as a high data rate (HDR) CDMA system.

Figure 3 shows a diagram based on the format of the data frame transmitted to the connection before the HDR CDMA system. In the forward connection, the traffic data, the leading reference, and the signal data are time-multiplexed in one frame and sent from a base station to a special user terminal. Each frame covers a time unit called a slot (for example, 1.67 in a special design of an HDR system). Each time slot includes flow data fields 302a, 302b, and 302c, leading reference fields 304a and 304b, and signal data (OH) fields 306a and 306b. The flow data field 302 and the leading reference field 304 are used for transmitting flow data and leading reference, respectively. The signal data field 306 is used to transmit signal information, such as a forward connection activity (FAC) indicator, a reverse connection busy indicator, and a reverse connection power control command. The FAC indicator will indicate whether the base station has traffic data to be sent to some special time slots. The reverse connection busy indicator will indicate whether the reverse connection capacity limit of the base station has been reached. The power control command will instruct the transmitting user terminal to increase or decrease its transmission power.

According to the HDR CDMA system, before transmission, the traffic data is covered by the Walsh code of the channel used for the data transmission, and the power control data of each user terminal is allocated to the user The Walsh code coverage of the terminal. Then the leading reference, coverage flow, and power control data will be used to allocate to the special base station The short PN expansion sequence is multiplied by the complex PN expansion sequence generated by the long PN expansion sequence allocated to the user terminal for expansion.

FIG. 4 shows a block diagram of a specific example of the receiving data processor 400 that can be used to process the HDR CDMA system before transmitting to the connection data. Digital I from the receiver_A_D_CAnd Q_A_D_CThe sampling will provide several data correlators 410 (for simplicity, only one is shown in FIG. 4). Due to multiple paths and other phenomena, the transmitted signal may reach a certain receiver unit via multiple signal paths. To improve performance, the receiver unit is usually designed to have the ability to handle multiple (and the strongest) received signal instances. For a traditional design, several data associators 410 are provided, and each data associator 410 is generally called a finger of rake receiver. Each data associator 410 can be assigned to process a specific instance of the received signal.

In the data correlator 410, I_A_D_CAnd Q_A_D_CThe samples are provided to a complex multiplier 412 which will also receive the complex PN de-expansion sequence from the multipliers 414a and 414b. The complex PN unrolling sequence is generated by multiplying the short PNI and PNQ sequence corresponding to the base station receiving the signal by the long PN sequence allocated to the receiver unit 400. The PN sequence has a time compensation corresponding to the special signal instance processed by the data correlator 410.

Multiplier 412 will perform complex number I_A_D_CAnd Q_A_D_CThe sample is multiplied by the complex number PN to solve the complex multiplication of the expansion sequence and provide the complex number solution expansion I_D_E_SAnd Q_D_E_SSample to Walsh (Walsh) to uncover elements 422 and 442. The solution expands I_D_E_SThe samples are also provided to Walsh de-cover element 432.

The Walsh (Walsh) uncovering element 422 will use the Walsh (Walsh) code used in the base station to cover the data to uncover the solution._D_E_SAnd Q_D_E_SSampling and generating several uncovered sample strings, where each channel string is transmitted as data. The sample string is then provided to a symbol accumulator 424 which accumulates the samples in each string based on the channel data rate used to transmit the string. For each string, the symbol accumulator 424 accumulates several uncovered samples to generate a uncovered symbol. The de-covering symbol is then provided to a leading demodulator 426.

The Walsh uncovering element 432 will be used by the base station to cover the special Walsh code W of the preamble reference._p(For example, Walsh (Walsh) code 0) to uncover the solution expansion I_D_E_Ssampling. The de-covering preamble samples are then provided to an accumulator 434 and accumulated in a special time interval (for example, in the preamble reference duration) to generate a preamble symbol. The preamble symbol is then provided to a preamble filter 436 and used to generate a restored preamble signal. The restored preamble signal includes preamble symbols estimated or predicted in the duration between preamble references and is provided to the preamble demodulator 426.

The preamble demodulator 426 performs demodulation on the uncovered data symbols from the symbol accumulator 424 consistent with the preamble symbols from the preamble filter 436 and provides the demodulated data symbols to a symbol combiner 450. The synchronous demodulation is accomplished by performing the dot product and cross product of the de-covering data symbol and the leading symbol, as described below. The point and the cross product can effectively perform the phase demodulation of the data and can also use the relative strength of the de-cover preamble to further scale the generated output. In order to make an effective combination, different received signal examples will have different contributions to the scaling of the preamble according to the quality of the received signal examples. therefore This point and the cross product will play the dual roles of phase projection and signal weighting, both of which are characteristics of a synchronous rake receiver.

The symbol combiner 450 receives the demodulated data symbols from each distributed data correlator 410, combines the symbols at the same time, and provides the restored data symbols to the deinterlacer 452. The despacing inserter 452 rearranges the symbols in a manner complementary to that performed by the base station. The decoder 460 then decodes the data symbols from the deinterlacer 452 and provides them to a data slot.

The design and operation of the rake receiver of the CDMA system is in US Patent No. 5,764,687, titled "MOBILE DEMODULATOR ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM," and US Patent No. 5,490,165, titled "DEMODULATION ELEMENT ASSIGNMENT IN A SYSTEM CAPABLE OF RECEIVING "MULTIPLE SIGNALS" has further details. The preamble carrier dot product and the (optimal) weighting of the finger path of the rake receiver are described in further detail in US Patent No. 5,506,865, titled "PILOT CARRIER DOT PRODUCT CIRCUIT". This patent is assigned to the assignee of the present invention and is incorporated herein by reference.

In the HDR CDMA system, the power control data of a special user terminal is covered by a special Walsh code assigned to the terminal and transmitted in each time slot. Therefore, in the data associator 410, the solution expansion I_D_E_SAnd Q_D_E_SThe sampling system uses the Walsh uncovering element 442 with the assigned Walsh code for uncovering. Then this The uncovered power control samples are provided to an accumulator 444 and accumulated during the duration of the power control to generate the power control bits of the processing signal instance. The power control bits from all distributed data accumulators 410 will be consistently combined (not shown in FIG. 4 for simplicity) to generate a combined power control bit, which is then used to adjust the user terminal The transmission power.

FIG. 5 shows a block diagram of a specific specific example of the data processor 230, which can handle data transmission of forward and reverse connections in various CDMA systems. For example, the data processor 230 can use the preamble reference of the synchronous demodulation of the forward connection data transmission in the HDR CDMA system, as shown in FIG. 4 above, to perform signal processing.

Refer to Figure 2, I from ADC 216_A_D_CAnd Q_A_D_CThe sample is formatted using the input data interface 222 and stored in the buffer 224. In a specific example, the buffer 224 is implemented as a ring, and the size of the two-dimensional buffer is selected based on some coefficients, such as input sampling rate, input sampling resolution, output sampling rate, and so on. The buffer 224 is designed to have the ability to store data samples received in a particular time period (for example, two sampling frames, or some other period). The selection of the time period must be long enough to collect a sufficient amount of data for all processing signal paths, but must be short enough to avoid writing new samples to old, unprocessed samples. The time period for collecting and storing samples is programmable.

In a specific example, in order to simplify the writing of data into the buffer 224, the width of each row of the buffer matches the width of the output block of the input data interface 222 (for example, 32 bits). When the word group can be written When entering the buffer 224, the data write address generator 512a generates a data write address DW_ADDR corresponding to the next available row in the buffer 224. Then the word group is written into the column indicated by the generated address of the buffer 224. After that, the stored samples can be captured and processed by the data processor 230.

The data processor 230 can be instructed to process data samples according to a set of special parameter values. For the flow data processing, the data processor 230 can be instructed to: (1) de-expand and de-cover the special case of the received signal under special time compensation, (2) perform the demodulation before de-covering symbols, and (3) Consistently combine the demodulation symbols corresponding to different signal instances. For signal (for example, preamble and power control) data processing, the data processor 230 can be instructed to: (1) de-expand and/or de-cover a special case of the received signal, (2) accumulate the data in a special time interval De-cover sampling, (3) Combine accumulated symbols from different signal instances. The data processor 230 can also search for strong instances of the received signal. The data processor 230 can be designed to perform various signal processing procedures, which are determined by the special CDMA standard or system and the special (forward or reverse connection) data transmission supported.

The buffer/de-interval inserter 234 stores the processed symbols from the data processor 230. When the symbol processed by the data processor 230 can be written into the buffer/de-interlacer 234, the symbol write address generator 542a will generate the symbol write corresponding to the appropriate position in the buffer/de-interlacer 234. Enter the address SW_ADDR. Then, the processed symbol is written to the position indicated by the write address of the generated symbol in the buffer/de-interval inserter 234. After that, the storage symbol will be provided back to the data processor 230 for further processing (for example, accumulating processed symbols from other signal instances). Therefore, the buffer/de-interval inserter 234 stores the result of the leading demodulation of the first signal instance, and further stores the accumulated result of the leading demodulation of the subsequent signal instance.

By generating appropriate symbol reading and writing addresses, the buffer/de-interlacing inserter 234 can rearrange the symbols according to the special de-interlacing technique operation. When the symbol is ready to be provided to the decoder 260, the controller 240 will start the reading process at an appropriate time. Then the symbol address generator 542b will generate an appropriate read address to reach the desired symbol deinterval insertion. The deinterval insertion (in other words, demodulation) symbols are provided to the decoder 260 for decoding.

In the specific example shown in FIG. 5, the I and Q samples from the buffer 224 are provided to the correlator 522 in the data processor 230. The correlator 522 still receives the complex PN de-expansion sequence, which will also be stored in the buffer 224 or generated by a PN generator (not shown in FIG. 5). For flow data processing, the correlator 522 will use the complex PN de-expansion sequence to de-expand the I and Q samples to provide de-expansion samples. Therefore, the correlator 522 performs the de-expansion function performed by the complex multiplier 412 in FIG. 4. The correlator 524 can also be designed to perform other functions, such as accumulating multiple de-expansion samples for each chip interval, de-expansion sampling and interpolation, and so on. The de-expanded samples are provided to a symbol demodulator and combiner 524.

The symbol demodulator and combiner 524 can perform de-covering, synchronous demodulation of the preamble, symbol combination of multiple signal instances, symbol accumulation of repeated symbols in the packet, or a combination thereof. For de-covering, the symbol demodulator The sum combiner 524 receives the de-expansion samples from the correlator 522 and performs de-covering with a set of Walsh symbols. In a specific example, the length of the Walsh symbol is programmable and can be selected as 1, 2, 4, 8, 16, or other lengths (for example, 32, 64, 128, etc.). For synchronous demodulation, the symbol demodulator and combiner 524 will receive and use the restored preamble symbol to demodulate the overlay symbol to generate the demodulation stored in the buffer/de-interlacer 234. symbol. For symbol combination, the symbol demodulator and combiner 524 receives and combines the demodulated symbols corresponding to various signal instances to generate the restored symbols that are stored back to the buffer/de-interlacer 234. Therefore, the symbol demodulator and combiner 524 can perform the functions performed by the data associator 410 and the symbol accumulator 450 in FIG. 4.

The buffer/deinterval inserter 234 stores the intermediate and final results of the symbol accumulation. The processed symbols from the symbol demodulator and combiner 524 are written into the buffer/deinterlacer 234 at the location specified by the symbol write address generator 542a in the address generator 236. The stored symbol is retrieved from the location specified by the symbol read address generator 542b in the buffer/deinterlace inserter 234. The buffer/de-interlacing inserter 234 can generate appropriate symbol read addresses for symbol de-interlacing complementary to the function performed at the transmitter unit. The symbols retrieved from the buffer/de-interval inserter 234 include the demodulated symbols provided to the decoder 260.

For signal data processing, the correlator 522 can use the complex PN de-expansion sequence to de-expand the I and Q samples and extract the de-expansion samples. An accumulator 526 is provided. The accumulator 526 can use one or more Walsh codes to uncover the unwrapped samples, accumulate the unwrapped or unwrapped samples in a special time period (for example, a leading reference period), and provide the restoration (For example, preamble or power control) data is given to the controller 240. The accumulator 526 can also provide processed samples to search for strong instances of the received signal under various time compensations.

In a specific example, the controller 240 processes the preamble symbols from the accumulator 526 and generates the restored preamble for synchronous demodulation of the data symbols. In other specific examples, the preamble processor may be implemented in the data processor 230 to filter the preamble symbols and generate the restored preamble. Other designs for handling leading references can also be considered and are all within the scope of the present invention.

In the specific example shown in FIG. 5, the data bus 510 is interconnected with various elements of the receiver unit 200, such as the address generator 220, the data processor 230, the microcontroller 232, and the controller 240. The data bus 510 supports effective transmission of data and other information between elements coupled to the data bus. For example, the controller 240 can use the data bus 510 to send tasks to the microcontroller 232 and send the processed leading symbols to the data processor 230. Other mechanisms for interconnecting the elements of the receiver unit 200 can be considered and are all within the scope of the present invention.

FIG. 6A shows a diagram of writing data samples to the buffer 224 and reading data samples from the buffer 224. In a typical digital communication system, data is divided into packets and processed, and then transmitted in a frame of a special time duration. For example, in the HDR CDMA system, the data is Packets are transmitted, and each packet is transmitted in one or more time slots. Each time slot is a part of a frame and (in the HDR system) includes 2048 chips. The cycle TC of each chip is related to the bandwidth of the entire system (in other words, T_C=1/BW).

In a specific example, the received samples are from a designated address, which can be selected arbitrarily (for example, a zero address, as shown in FIG. 6A), and start writing to the buffer 224. In a specific example, when a reset event occurs (such as turning on the power), a data write address indicator is activated to the specified address and samples are written to the buffer 224 starting from the address specified by the indicator. Therefore, there will be any compensation or phase shift between the writing address indicator and the actual boundary of the over-the-air frame represented by the sample. The frame boundary is equivalent to any address in the buffer 224. During the acquisition process, the compensation is calculated by the controller 240. The subsequent data capture uses the calculated compensation, which adds the compensation to the read address index for compensation.

The data write address generator generates a data write address DW_ADDR pointing to the next available location in the buffer 224. In a specific example, the samples written into the buffer 224 are consecutive locations and the data write address DW_ADDR is increased after each write operation. In a specific example, the buffer 224 is a circular buffer that can be wrapped around. Using the size of the selection buffer 224, whose size is a power of 2, a two-bit counter can be used to provide the required write (or read) address. When the end of the buffer 224 is reached, the counter will cycle and reset to zero.

After storing a sufficient number of samples in the buffer 224, the special sample section can be retrieved from the buffer and processed. The sampling section includes data sampling of the entire packet or part of the packet. In a specific example, each data sampling section is equivalent to a separate preamble reference, and the size of the section is limited by the duration of synchronization between the channel and the preamble reference. In a specific example, as part of the preamble processing in the controller 240, the leading vector corresponding to the preamble reference is phase-rotated according to a frequency error estimate to generate the leading estimate, which is then provided to the data processor 230 performs preamble demodulation. Therefore, the controller 240 will sample the leading reference at the beginning of the segment and use the leading reference to generate a leading estimate of the duration of the segment. The phase error in the preamble estimation is accumulated over the length of the sampling section, so the length of the sampling section must be limited to reduce the amount of accumulated phase errors in the preamble estimation. This design may not require a dedicated complex rate multiplier to rotate the sample itself, which will increase the complexity of the data processor.

Data sampling sections corresponding to different signal instances (or multiple paths) can be processed continuously. For example, the samples corresponding to the first multipath with zero time compensation are retrieved from the buffer 224 and processed by the data processor 230. After the processing of the first multipath is completed, another sample section (for example, corresponding to the second multipath) is retrieved from the buffer 224 and processed. For each section to be processed, the data read address generator will load an initial address, which will take into account (1) the zero offset arrangement of the sample and the write address index Compensation between (2) relative to the segment address at the beginning of the packet, and (3) with the special multipath to be processed Related time compensation.

FIG. 6B shows a diagram of writing PN samples into the buffer 224 and reading PN samples from the buffer 224. In a specific example, the complex number of PN samples used to unspread the received samples is calculated using a PN generator and stored in a portion of the buffer 224. Similarly, the PN sample can be stored from the designated address. Afterwards, the PN sample section can be retrieved from the buffer 224 and used to de-expand a corresponding data sample section.

A PN write address generator is used to generate a PN write address PW_ADDR indicating the next available position in the buffer 224, and a PN read address generator is used to generate samples for reading PN The PN read address PR_ADDR. For each data section that must be processed that requires PN sampling, the PN read address generator loads the address of the first PN sample in the section. The PN write and read address generator will increase appropriately after each PN write or read operation.

The number of PN samples stored in the buffer 224 will vary based on several factors and will match the number of data samples to be stored. For example, the two time slots of PN sampling can store the two time slots of data sampling. The number of PN samples used for storage is also related to, for example, the size of the buffer 224, the number of supported multipath deskews, and so on.

FIG. 6C shows a block diagram of a specific concrete example of the data buffer of the receiver design shown in FIGS. 2 and 5. I from ADC_A_D_CAnd Q_A_D_CSampling is provided to the input data interface 222, which removes redundant samples and removes The samples are packed into blocks, and these blocks are provided to a multiplexer 612. A PN generator 614 will receive the PN mask from the data bus 510, generate a part of the position of the IPN and QPN sequence for de-expanding the data sample, and sample the generated IPN and QPN (in word Group) is provided to the multiplexer 612. The multiplexer 612 provides each received block, including data sampling or PN sampling, to the buffer 224 at the location indicated by the write address provided by the address generator 220.

6C also shows a block diagram of a specific example of the address generator 220 for generating the address of the buffer 224. The address generator 220 includes a data write address generator 512a, a data read address generator 512b, a PN write address generator 512c, and a PN read address generator 512d respectively coupled to the latch 514a, 514b, 514c, and 514d. The address generators 512a to 512d are also coupled to a multiplexer 622, which selects the generated address from one of the address generators 512 and provides the selected address to the buffer 224.

Each latch 514 stores a value representing the first address of the section to be processed generated by the address generator 512. For example, a special data sample section is read from the buffer 224, and the address of the first data sample in the section is provided to the latch 514b at an appropriate time. The data read address generator 512b loads the value stored in the latch 514b and uses this value as the starting address. For example, the counter in the data read address generator 512b is incremented to generate the subsequent data read address.

As described above, the data sample can be stored in any designated buffer location (for example, zero) in the buffer 224. Similarly, the buffer 224 is designed to It has the ability to retain a certain number of samples. In a specific example, the size of the buffer 224 is a power of two. Then, a two-bit counter is used to generate the write (or read) address of the buffer 224. When the end of the buffer 224 is reached, the counter will cycle to zero.

In a specific example, because the data samples are written to the buffer 224 in sequential order, the data write address generator 512a can also be used as a sampling counter for calculating the number of samples stored in the buffer 224. The data write address from the address generator 512a is supplied to a comparator 628 and compared with the comparison value provided by the controller 240. The comparison value indicates the storage of the special sample quantity (for example, one packet) that the controller 240 wants to be notified of. If the data writing address is equal to the comparison value, the comparator 628 will provide a time signal indicating this situation. The controller 240 uses this time signal to start the process of storing samples.

Fig. 6C also shows a specific example of the time processing of each designated multipath. In a specific example, the controller 240 maintains a time state machine 630 in each multipath (in other words, fingers) to be processed. Although the block diagram shown in FIG. 6C is shown, the state machine 630 is usually implemented and maintained by the DSP firmware at each time. The data processor 230 can be instructed to perform certain signal processing in order to search for the strongest received signal instance in the data samples (for example, the PN sampling section is associated with several data sampling sections under various time compensations). Each correlation peak is an example of a strong signal. If the correlation peak exceeds the special standard, the controller 240 will activate a new time state machine 630 for the multiple paths corresponding to the correlation peak. Then it will determine the time compensation that should be allocated for the multipath and use it The address of the sample to be read from the buffer 224 is generated.

In a specific example, each state machine 630 includes a time tracking loop 634 for tracking the movement of the multiple paths. This time tracking can use samples processed at +1/2 and -1/2 chip compensation (for example, equivalent to the leading reference) to determine the difference between the leading accumulation at +1/2 and -1/2 chip compensation, And filtering the difference value to generate a correction coefficient to complete. Therefore, when the multiple paths move over time, the time tracking loop 634 determines the number of moves and uses the correction factor to update the time compensation. The time compensation is provided to a data/PN address calculation unit 636 and used to calculate the start address of each data segment to be processed. Then the calculated starting address will be provided to the latch 514b via the data bus 510 at an appropriate time.

As described above, the samples stored in the buffer 224 start at any point in time from the designated location in the memory. Therefore, the initial sample of each signal instance to be processed corresponds to any position in the buffer 224. In a specific example, the time tracking loop can be used to determine the starting position of the received data packet for each signal instance to be processed. The time tracking loop processes the received samples to determine the special time compensation for the received signal instance. This time compensation is then used to generate the start address of each sampling section to be processed.

The state machine 630 is implemented by the controller 240 using DSP firmware and a set of basic processing elements. For example, a single time tracking loop 634 and a single data/PN address calculation unit 636 may be time division multiplexing and used to implement all state machines 630. The controller 240 maintains a separate register to store the time compensation associated with each example state machine 630.

In a specific example, for the forward connection processing in the remote terminal, the controller 240 also maintains a frequency tracking loop to lock the frequency of the clock source to the data rate of the data sample. The frequency tracking loop can be designed to determine the amount of phase rotation in the leading reference, use the phase information to determine whether the sampling clock is too fast or too slow relative to the chip rate, and thus adjust the frequency of the clock source. If the frequency of the sampling clock is locked at the chip rate, a special number of data samples (for example, 2048) will be provided for each frame. Therefore, when the frequency is locked, it can be regarded as a frame sample to be received by counting the number of samples written to the buffer 224.

FIG. 6C also shows a block diagram of the address generator 236 used to generate the address of the buffer/despacing inserter 234. The address generator 236 includes a symbol write address generator 542a and a symbol read address generator 542b, which are respectively coupled to the latches 544a and 544b. The address generators 542a and 542b are also coupled to a multiplexer 546 for selecting and generating an address from one of the address generators 542a and 542b and provide the selected address to the buffer/de-interpolator 234.

Each latch 544 stores a value generated by the address generator 542 representing the first address of the section to be processed. The initial value provided to the latch 544 is generally related to the value provided to the latch 514, but the method of providing is based on various factors, such as the processing delay of the data processor 230. The symbol read address generator 542a loads the value stored in the latch 544a and uses the loaded value as the starting address. For example, the subsequent symbol read address can be generated by incrementing the counter in the symbol read address generator 542a.

In a specific example, the buffer/de-interval inserter 234 is used to store the intermediate value and the final result of the sign accumulation of the multipath. At the beginning, special multipath samples are processed, and the obtained samples are stored in a special location of the buffer/de-interval inserter 234. To simplify the addressing, the symbol of a particular multipath (for example, the first one to be processed) can be stored in the buffer/deinterlacing inserter 234, starting from a specified position (for example, zero, N_sEtc. address). For each subsequent multipath, the demodulated symbol of this multipath can be combined with the corresponding stored symbol of the previously processed multipath. Then the combined symbol will be stored back to the same position in the buffer/de-interval inserter 234. Therefore, the symbols of the processed multipath will be "appropriately" combined with the relative previously accumulated symbols. When the symbols of the various multipaths are to be combined, the address generator 236 generates appropriate symbol read and write addresses, as determined by the values stored in the latches 544a and 544b.

In many communication systems that include HDR CDMA systems, interval interpolation is used to provide short-term diversity in the transmitted data. This interval interpolation reduces the possibility of receiving a series of continuous errors due to impulse noise. In the receiver unit, the received symbols are reordered. The reordering can effectively expand the series of symbols received in the error of the entire frame, which can improve the possibility of correct decoding of the received symbols. The interval interpolation is performed in the transmitter unit so that a brief diversity can be completed before the receiver unit decodes it.

In a specific example, the buffer/deinterval inserter 234 can also provide deinterval insertion of the processed symbol. In a specific example, writing to the buffer The processing symbols of the impulse/de-interval inserter 234 are in sequential order, but the readout is performed in a pseudo-random order defined by the implemented special interval interpolation technique. Because the symbol is read in a non-continuous manner, the buffer/de-interval inserter 234 can first fill the symbol during the execution of the corresponding interval interpolation. For example, in the HDR CDMA system, each data frame can be interpolated at intervals. Therefore, in the receiver unit, a complete symbol frame is processed and stored in the buffer/deinterlacer 234. After processing the complete frame, the symbol of the frame will be read to the subsequent decoder. In a specific example, data processing is performed on one data frame at a time. In this case, after the current frame is processed and stored in a section of the buffer/deinterval inserter 234, the previous processing will be retrieved from the section of another buffer/deinterval inserter 234 The frame of the past.

The symbol read address generator 542b includes necessary circuits to generate appropriate symbol addresses to be provided to the symbol demodulator and combiner 524 for symbol accumulation, and symbols to be provided to the subsequent decoder 260 for decoding. The symbol read addresses of the two end points can be generated in a time division multiplexing manner. For example, the symbols can be provided to the symbol demodulator and combiner 524 and the decoder 260 in an alternate symbol reading cycle. In addition, after providing a group of symbols to the symbol demodulator and combiner 524, a group of symbols may be provided to the decoder 260.

FIG. 7A shows a block diagram of a specific example of the associator 522 in the data processor 230. In a specific example, the correlator 522 is designed to support several functions including, for example, using the complex PN solution to expand Sequence data sampling and de-expansion, accumulate multiple de-expansion samples in each chip cycle, and interpolate. To enhance performance, the correlator 522 can be designed to operate on multiple (for example, four) complex samples at the same time. Other designs and functions of the correlator 522 can be implemented and all fall within the scope of the present invention.

In a specific example, for each data read cycle, four pairs of digitized I are retrieved from the buffer 224_A_D_CAnd Q_A_D_CSampling (in other words, four kinds of complex data sampling) and locking by latches 712a to 712d. In the next data reading cycle, the samples from the latches 712a to 712d will be further locked by the latches 714a to 714d, and the following four pairs of digitization I_A_D_CAnd Q_A_D_CThe sampling will be locked by the latches 712a to 712d. In a specific example, there will be two data samples per chip cycle (that is, double sampling) and the double locking of latches 712 and 714 can handle on-time (OT) sampling or obsolescence of each chip. late, LT) sampling.

The multiplexers 716a to 716d receive lock samples from the latches 712a to 712d, respectively, and lock samples from 714a to 714d, respectively. Each multiplexer 716 will provide one of the received samples, depending on whether it is processed on the current or obsolete samples, to another gate 718. The gates 718a and 718b also receive the control signal ZERO_0, and the gates 718c and 718d also receive the control signal ZERO_1. Each gate 718 will provide received samples or zero ("0") values to the individual multiplexer 720, depending on the control signal ZERO_x.

In a specific embodiment, the buffer 224 is designed to also store the IPN and QPN sequences used to de-expand the data sampling. In a specific example, for each PN reading cycle, a 16-chip section of a complex PN unrolling sequence is retrieved from the buffer 224, corresponding to the data to be processed. In this way, it is locked by the latch 732 and provided to a multiplexer 734. The multiplexer 734 selects a portion of the locked complex PN section (for example, the 2-chip portion) and provides the selected portion to a barrel shift register 736. The register 736 then provides appropriate IPN and QPN samples to each of the multipliers 720a to 720d.

In a specific example, the ADC can oversample the data and provide twice the wafer rate (in other words, the sampling rate is twice the wafer rate). The over-sampling can use a finer time to resolve the strong instances of the received signal, which can improve performance. For the correlator structure shown in FIG. 7A, four parallel processing paths are provided and at most four complex data samples corresponding to two data chips can be processed simultaneously in each cycle. As shown in FIG. 7A, multipliers 720a and 720b will de-expand two complex data samples corresponding to chip index n (for example, current and obsolete samples), and multipliers 720c and 720d will de-expand two corresponding chip indexes n+ Sampling of 1's complex data. The large displacement register 736 provides IPN and QPN samples corresponding to the chip index n to the multipliers 720a and 720b, and provides IPN and QPN samples corresponding to the chip index n+1 to the multipliers 720c and 720d.

Each multiplier 720 uses the complex PN sample to perform complex solution expansion of the complex data sample. In the HDR CDMA system, in the transmitter unit, the complex data to be transmitted will be expanded using the complex PN sequence. The complex expansion can be expressed as:<maths><img file="TW595149B_D0002.tif" /></maths>In the receiver unit, the data can be recovered by performing complementary complex solution expansion, which can be expressed as:<maths><img file="TW595149B_D0003.tif" /></maths>Where I_A_D_C=I_T_X+ Noise, Q_A_D_C=Q_T_X+ Noise, I_D_E_S=I_D_A_T+ Noise, and Q_D_E_S=Q_D_A_T+ Noise.

FIG. 7B shows a block diagram of a specific concrete example of the multiplier 720 that performs the complex number solution expansion represented by equation (2). Inside the multiplier 720. Sampling the complex data, I_A_D_CAnd Q_A_D_C, Will be provided to each multiplexer 762a and 762b, and the plural PN samples, IPN and QPN, will be provided to the mutex or gate 764. The exclusive OR gate 764 performs XOR (in other words, multiplication) of IPN and QPN sampling and provides the output to the selected input of each multiplexer 762a and 762b. Each multiplexer 762 will select I_A_D_COr Q_A_D_CSampling depends on the value of the selected input, and the selected sample is provided to the input of the individual mutex or gate 766. The mutual exclusion or gates 766a and 766b use IPN and QPN to perform mutual exclusion or function (in other words, multiplication) on the received samples, and provide the output samples to the sum gates 768a and 768b, respectively. Each gate 768 will also receive the control signal ZERO_x and provide a received sample or value "0" based on the control signal ZERO_x. The output of gates 768a and 768b includes complex solution expansion I_D_E_SAnd Q_D_E_Ssampling.

Referring again to FIG. 7A, the solution expansion I from multipliers 720a to 720d_D_E_SAnd Q_D_E_SThe sampling system is selectively combined using adders 722a to 722d to generate a set of combined I_CAnd Q_Csampling. In particular, the adder 722a combines the solution expansions from the multipliers 720a and 720c._D_E_SSampling to generate the first combination I corresponding to the first half of the wafer_C₁Sampling, the adder 722b will combine the solution expansion I from the multipliers 720b and 720d_D_E_SSampling to generate the second combination I corresponding to the second half of the chip_C₂Sampling, the adder 722c will combine from the multiplier 720a and 720c solution expand Q_D_E_SSampling to produce the first combination Q_C₁Samples, and the adder 722d combines the solutions from the multipliers 720a and 720c to expand Q_D_E_SSampling to produce the second combination Q_C₂sampling. Before interpolation, the adder 722 can be used to combine the samples from different chips to simplify the design of the interpolator. And gate 718 and ZERO_0 and ZERO_1 signals can be used to sum up the samples from the two chips and turn them off when they are not in use, so that each chip can include a complex or higher order in the forward connection symbol demodulation. Modulation symbol.

In the specific example shown in FIG. 7A, the correlator 522 includes an interpolator 730 that can generate sampled values under various time compensations. For example, if two complex data samples are provided for each chip (in other words, in the time compensation 0T_CAnd 0.5T_C, Where T_CBased on the chip cycle), the interpolator 730 can be used to compensate at other times, for example, 0.125T_C, 0.25T_C, 0.37T_C, 0.625T_C, 0.75T_C, 0.875T_CAnd so on to generate interpolated data. The time resolution of the interpolation depends on the special design of the interpolator 730. The interpolator 730 can be used, for example, to use a finer density than the sampling period (e.g., finer 0.5T_C) Time resolution to identify a multiple path.

The graph shown in Fig. 7C is a linear interpolation scheme. As shown in FIG. 7C, the amplitude of the sample at the sampling index (n) is A, and the amplitude of the sample at the following sampling index (n+1) is B. The sampling period will be normalized to a value of 1.0. The sampling at the sampling index (n) and (n+1) can be used to predict the sampling value at other time compensations such as 0.25, 0.50, 0.75, etc. For linear interpolation, the sampling amplitude at time compensation 0.25 can be predicted as 0.75A+0.25B, and the sampling amplitude at time compensation 0.5 can be predicted as 0.50A+0.50B, and the sampling amplitude at the time compensation of 0.75 can be predicted to be 0.25A+0.75B. The sample is scaled by a factor of four, and the sample amplitude at time compensation 0.0, 0.25, 0.5, 0.75, and 1.0 can be expressed as 4A, 3A+B, 2A+2B, A+3B, and 4B, respectively.

FIG. 7D shows a block diagram of a specific example of the interpolator 730. In this specific example, the interpolator 730 serves as a linear interpolator that can provide interpolation samples at three different time compensations (for example, 0.25, 0.50, and 0.75). The interpolator 730 can also be designed to have (1) provide a zero-value output, (2) receive a sample feed (feed), (3) provide an interpolated sample, or a combination thereof.

Combination I from adders 722a to 722d_C₁, I_C₂, Q_C₁, And Q_C₂Symbols are provided to zoom elements 770a to 770d, respectively. Within each zoom element 770, the sample is provided to the X1 input of a multiplexer 772, an input of a times-two element 774, and an input of an adder 776. The multiplying element 774 scales the received samples by a factor of two and provides the scaled output to the X2 input of the multiplexer 772 and the other input of the adder 776. The adder 776 sums the input samples and the X2 scaled samples and provides the summed output to the X3 input of the multiplexer 772. The multiplexer 772 will also receive a zero ("0") signal at its X0 input. Then the multiplexer 772 will select one of the input samples, according to the control signal OFFSET, and provide the selected sample to the latch 780.

As shown in FIG. 7D, the zoom elements 770a and 770b may be complementary forms, and the zoom elements 770c and 770d may also be complementary forms. For special time compensation of 0.25, 0.50, or 0.75 (using the control signal OFFSET said), the value 3I_C₁, 2I_C₁, Or 1I_C₁, Will be provided from the zoom element 770a to the latch 780a, and the value I_C₂, 2I_C₂, Or 3I_C₂, Are respectively provided from the zoom element 770b to the latch 780b. Then the samples from the latches 780a and 780b are provided to the adder 782a, and the samples from the latches 780c and 780d are provided to the adder 782b. The output from the adder 782a includes interpolated I samples, and the output from the adder 782b includes interpolated Q samples. The interpolated samples from the adders 782a and 782b are used as the correlation I from the correlator 522_C_O_RAnd Q_C_O_R. The outputs from latches 780a to 780d also include (non-interpolated) correlation I_C_O_R₁, I_C_O_R₂, Q_C_O_R₁, And Q_C_O_R₂sampling.

The interpolator 730 can operate in one of several different structures. For example, as described above, the interpolator 730 can output zeros, provide interpolated samples, or a combination of the above via the received sample feed. The zero value at the X0 input of the multiplexer 772 will be selected to output zero, and the sample at the X1 input will be selected to be fed through the received sample. To perform the interpolation, the multiplexer 772 will select the X1, X2, or X3 value and the other multiplexer 772 in the complementary pair will select the complementary value X3, X2, or X1.

In a specific example as described above, two data samples are provided for each chip cycle and processed by the correlator 522 (for example, de-expansion). The two samples per wafer cycle can be combined in the interpolator 730 to provide a single de-expanded sample in each wafer cycle. To combine the I samples for each chip, the samples at the X1 input of the multiplexer used to scale elements 770a and 770b are selected and summed using adder 782a to provide combined I samples. Similarly, to combine the Q samples of each chip to scale element 770c and The samples at the X1 input of the 770d multiplexer are selected and summed using the adder 782b to provide a combined Q sample.

In the HDR CDMA system, the transmission flow data is divided into several data strings, and each data string is covered by a special Walsh code. As defined in the HDR CDMA system, each Walsh code is equivalent to a Walsh symbol with a length of 16 chips. To channel the data, 16-chip Walsh symbols assigned to the channel of the transmission bit are used to cover each data bit. For each Walsh symbol period, 16 Walsh symbols of 16 data bits transmitted on 16 channels are generated and combined. The 16 Walsh symbol systems are orthogonal to each other and, without distortion, because the cross-correlation between orthogonal sequences is (ideally) zero, they can be individually restored in the receiver unit .

FIG. 8A shows a block diagram of a specific example of the symbol demodulator and combiner 524 in the data processor 230. The paired correlated samples from the correlator 522 are provided to a de-covering element 820 which uses channelization (eg, Walsh) symbols to de-cover the samples to provide de-covering samples. The uncovered data symbol and the complex preamble symbol are provided to a preamble demodulator 850, which uses the preamble to simultaneously demodulate the data to generate demodulated symbols. The demodulated symbol is then provided to a symbol accumulator 870 and can be combined with other demodulated symbols from other signal paths or other repetitive transmissions. The output from the symbol accumulator 870 includes the processed symbols, which are then provided to the buffer/deinterlacer 234 (see Figure 5).

The symbol demodulator and combiner 524 can be designed to perform operations on several samples (for example, four, eight, sixteen, etc.) in each clock cycle. The several samples that the symbol demodulator and combiner 524 can process at the same time are usually related to some coefficients. For example, the sampling rate that can be provided to the symbol demodulator and combiner 524, the symbol demodulator and combiner 524 The width of the elements inside, etc.

The system shown in FIG. 8B is a block diagram of a specific specific example of the Fast Hadamard Transformation (FHT) element of the de-covering element 820 that can be realized. In a specific example, the I of the association_C_O_RAnd Q_C_O_RThe samples are provided to the FHT element 820 in a sequential and alternating manner, with one sample per clock cycle. In a specific example, the FHT element 820 is designed to use one or more Walsh symbols with a length of N and N is programmable, and perform Walsh de-covering of received sampling. ability.

The FHT element 820 can be designed to operate under some different structures. For example, the FHT element 820 can use a special Walsh symbol of a special length N to uncover the input sample. In this structure, FHT element 820 will receive N I_C_O_RSampling and N Q_C_O_RSampling (in other words, N-chip I_C_O_RAnd Q_C_O_RVector pair) and use this special Walsh symbol to perform N-chip Walsh de-covering on the receiving sampling block to generate a pair of uncovered I_D_E_CAnd Q_D_E_Csymbol.

In addition, the FHT element 820 can use all N Walsh symbols to uncover the received samples. In this structure, the FHT element 820 will use N to I_C_O_RAnd Q_C_O_RThe sampled vector performs the N-by-N Hadamard matrix multiplication function (equivalent to N Walsh symbols Number, each Walsh (Walsh) symbol has the length of N chips) to produce N pairs of solutions cover I_D_E_CAnd Q_D_E_Csymbol. Using all N Walsh symbols to de-cover has considerable benefits. For example, the HDR CDMA system can transmit more than one channel to a special terminal.

In a specific example, in order to send I_C_O_RAnd Q_C_O_RProcessing of sampling and minimizing the number of circuits, FHT element 820 is used to process I on alternate clock cycles_C_O_RAnd Q_C_O_Rsampling. In this way, a single FHT element 820 can be used to provide de-coverage in alternate clock cycles._D_E_CAnd Q_D_E_CThe symbol is given to the subsequent processing unit, and the Q_D_E_CSymbol and corresponding I_D_E_CThe symbol will have a single clock cycle delay. Then the subsequent processing unit can be designed to cover the solution provided by the FHT element 820 I_D_E_CAnd Q_D_E_CSymbol to perform operations without waiting for all I to be processed in the block_C_O_RSymbols and Q to be processed_C_O_Rsymbol. The FHT element 820 can appropriately manage the memory elements in the FHT element 820 for alternate I_C_O_RAnd Q_C_O_RPerform calculations on sampling.

The FHT element 820 is a serial processing engine for serially receiving samples, one sample per clock cycle, and after a special processing delay, each clock cycle provides a de-covering symbol. The solution coverage symbol of the special sampling block is delayed by several special clock cycles, and the delay part is determined by the length of the Walsh symbol. For each block with N data samples, the FHT element 820 serially provides N uncovered symbols corresponding to N Walsh symbols. The solution from FHT element 820 covers the association between input samples and Walsh symbols.

Fast Hadamard conversion elements can use L bufferfly The length of the converted element pair is N=2^LThe Walsh (Walsh) symbol for uncovering. In the specific example shown in FIG. 8B, in order to uncover the 16-chip Walsh symbol, the FHT element 820 includes four bufferfly conversion elements 830a to 830d connected in series. Each bufferfly conversion element 830 performs the required subset of addition and subtraction operations. Each continuous bufferfly conversion element 830 will be further cross-coupled with the result of the previous bufferfly conversion.

In each bufferfly conversion element 830, the input samples are provided to the input of the multiplexer 832, the subtracting input of the adder 834, and the first summing input of the adder 836. The multiplexer 832 also receives the output of the adder 834 and alternately provides the output or input samples of the adder 834a to the memory element 838. The output of the memory element 838 is provided to the summation input of the adder 834, the second summation input of the adder 836, and an input of the multiplexer 840 which also receives the output of the adder 836. The multiplexer 840 alternately provides the output of the memory element 838 and the output of the adder 836 to the latch 842. The output of the latch 842 will be provided to the input of the next bufferfly conversion element 830. The output of the last bufferfly conversion element 830d includes the uncovering symbol.

The design and calculation of an FHT element is described in US Patent No. 5,561,618, titled "METHODS AND APPARATUS FOR PERFORMING A FAST HADANARD TRANSFORM," with further details. The patent is assigned to the assignee of the present invention and is hereby granted. Reference citation.

In the specific example shown in Figure 8B, the FHT element 820 can be programmed To perform fast Hadamard conversion (in other words, de-cover) of variable length (for example, 1, 2, 4, 8, or 16). The maximum FHT length supported by the FHT element 820 is determined by the number of bufferfly conversion elements 830 used, and a shorter length FHT can be performed by skipping one or more bufferfly conversion elements 830. Longer length FHT can also be performed using an additional bufferfly conversion element 830.

In the specific example shown in Figure 8B, I_C_O_RAnd Q_C_O_RThe sampling is provided to the FHT element 820 on the same bus in alternate clock cycles. The time division multiplexing is achieved by using a Walsh counter (not shown in FIG. 8B), and the counter is cleared when the first associated sample reaches the front of the FHT element 820. The time division multiplexing can share hardware, so FHT element 820 can perform I_C_O_RAnd Q_C_O_RSample solution coverage. In another specific example, I_C_O_RAnd Q_C_O_RSampling will be provided to two FHT elements in a side-by-side manner, and each FHT element is used to perform an individual I_C_O_ROr Q_C_O_RSample solution coverage.

FIG. 8C is a block diagram of a specific example of the preamble demodulator 850. Solution Covering I from FHT Element 820_D_E_CAnd Q_D_E_CSign and plural leading P_IAnd P_QThe symbol is provided to the preamble demodulator 850, which simultaneously uses the preamble to demodulate the uncovered symbol. The preamble demodulation can be expressed as:<maths><img file="TW595149B_D0004.tif" /></maths>The demodulation I_D_E_MAnd Q_D_E_MThe symbol can be expressed as:<maths><img file="TW595149B_D0005.tif" /></maths><maths><img file="TW595149B_D0006.tif" /></maths>In the demodulator 850, de-coverage I will be provided separately_D_E_CAnd Q_D_E_CSymbols (for example, in alternating clock cycles) are given to latches 852a and 852c. The output of the latch 852a will be further locked by the latch 852b for time-align I_D_E_CAnd Q_D_E_Csymbol. The outputs of the latches 852b and 852 include plural data symbols. Similarly, the P_IAnd P_QThe leading symbol will be locked by latches 854A and 854B respectively. The output of the latches 854a and 854b is provided to each of the multiplexers 856a and 856b. Each multiplexer 856 will select P_IOr P_QThe leading symbol depends on the execution point or cross product. The complex leading symbols of the multiplexers 856a and 856b are provided to the multipliers 860a and 860b, respectively, which also receive the complex data symbols from the latches 852b and 852c, respectively. Each multiplier 860 will execute one element of the complex data symbol (in other words, I_D_E_COr Q_D_E_C) And one of the leading symbols of the plural (in other words, P_IOr P_Q) And provide the resulting product to the respective latch 862.

The output of the latch 862a is provided to the mutex or gate 864 which also receives the control signal CROSS. The output of the latch 862b and the output of the exclusive OR gate 864 are provided to the adder 866 that performs sign summation and the summed output is provided to the sign accumulator 870.

From equation (4), the demodulation change I_D_E_MThe symbol can be used to perform I with the multiplier 860a_D_E_CData symbol and P_IMultiplication of the leading symbol, Q with multiplier 860b_D_E_CData symbol and P_QThe multiplication of the leading symbol is generated by using the adder 866 to combine the results of the multipliers 860a and 860b. same Ground, from equation (5), the demodulation change Q_D_E_MThe symbol can be used to perform I with the multiplier 860a_D_E_CData symbol and P_QMultiplication of the leading symbol, Q with multiplier 860b_D_E_CData symbol and P_IThe multiplication of the leading symbol inverts the result of the multiplier 860a, and uses the adder 866 to combine the inverse result of the multiplier 860b and the exclusive OR gate 864 to produce. Therefore, to generate the demodulation Q_D_E_MSymbol, multiplexers 856a and 856b will provide P to multipliers 860a and 860b_IAnd P_QThe leading symbol is exchanged, and the mutex OR gate 864 reverses the result of the multiplier 860a.

Fig. 8C also shows a block diagram of a specific example of the symbol accumulator 870. Demodulation of preamble demodulator 850 I_D_E_MAnd Q_D_E_MThe symbols are provided to the adder 872 in tandem. I calculated previously_P_R_EAnd Q_P_R_EThe symbols are retrieved from the buffer/despacing inserter 234 (for example, in pairs) and provided to the latch 874. The multiplexer 876 will be coupled to the latch 874 and select I_P_R_EOr Q_P_R_ESymbol to provide to and gate 878. The gate 878 will also receive the control signal FIRST, if there is no sign accumulation to be executed, it will make the output of the gate 878 zero. The output of the gate 878 will be provided to the adder 872 and the received I_D_E_MOr Q_D_E_MSymbols add up. The output of the adder 872 includes the accumulation (in other words, processed) provided by the back buffer/de-interval inserter 234_P_R_OOr Q_P_R_Osymbol.

9 is a block diagram of a specific specific example of the accumulator 526 in the data processor 230, which can be used to process flow data, preamble reference, and other signal data. At the user terminal, the accumulator 526 can be used to search for strong instances of the received signal, restore the leading reference, capture the power control bit, and so on. At the base station, the accumulator 526 can be used to perform The above functions can also be used to process other signal information such as data request information (DRC).

In the specific example shown in FIG. 9, the correlation I of the associator 522 is_C_O_RAnd Q_C_O_RThe sampling will be provided to a set of eight uncovered and accumulated elements 910a to 910h. Different numbers of de-covering and accumulating elements 910 can be used within the scope of the present invention. In each solution covering and accumulating element 910, the correlation I_C_O_ROr Q_C_O_RThe samples will be provided to the mutex or gate 912 which will also receive the Walsh symbols from the Walsh generator 914. The Walsh generator 914 can be programmed to use the corresponding Walsh code loaded in the associated latch 916 to generate a special Walsh symbol. Therefore, the eight uncovered and accumulated elements 910a to 910h can be programmed to use eight different Walsh symbols for a special I_C_O_RAnd Q_C_O_RThe sampling block is uncovered.

On the forward connection, a solution overlay element will be used to process the power control data. On the reverse connection, eight uncovering elements can be used to demodulate data rate control (DRC) data and treat FHT as DFT (in other words, non-fast).

In each de-covering and accumulating element 910, the mutex or gate 912 will use the Walsh symbol to de-cover the data sample and provide the de-cover sample to one of the inputs of the multiplexer 922. The other input of the multiplexer 922 will receive the individual correlated samples from the correlator 522 (in other words, I_C_O_R₁, I_C_O_R₂, Q_C_O_R₁, Or Q_C_O_R₂). Depending on the specific tasks performed, the multiplexer 922 will provide the de-cover sampling or correlation sampling of the multiplexer 922 to the adder 924. The adder 924 will also receive from the ADD gate 926 The samples were previously locked, and accumulated outputs are provided to the first set of registers 928a and 928b (coupled in series) and the second set of registers 930a and 930b (also coupled in series). The latched output of the latch 928b and the control signal FLUSH/ will be provided to the input of the gate 926. If the control signal FLUSH/ is low, it will provide a value of zero to the adder 926, and if the control signal FLUSH/ is high, it will provide a latched output . The lock output of the latch 930b includes the accumulation sign and is provided to one of the inputs of the multiplexer 940.

The multiplexer 940 will receive the accumulation symbols from all eight de-covering and accumulation elements 910a to 910h and provide the received symbols to the latch 942 in sequence, which will be further coupled to the data bus 510. The controller 240 can then be used to extract the accumulated symbol from the latch 942.

As shown in Figure 9, the association I_C_O_RAnd Q_C_O_RThe samples are also provided to the squarer 952 in the de-covering and accumulating element 910b. The squarer 952 squares the extracted sample and provides the squared sample to one of the inputs of the multiplexer 954, which also receives the de-covering sample from the mutex or gate 912b. The multiplexer 954 then provides the square sample or de-covering sample to the multiplexer 922b, depending on the control signal SQUARE. The squarer 952 supports the estimation and calculation of the carrier-to-interference energy, which is used to evaluate the quality of the signal connection.

The accumulator 526 can be programmed to perform some tasks. For example, the accumulator 526 can be programmed to decover eight different channels simultaneously. In the specific example shown in Figure 9, the association I_C_O_RAnd Q_C_O_RSampling will be done in a time-sharing manner (in other words, I_C_O_R, Q_C_O_R, I_C_O_R, Q_C_O_R, Etc.) are provided for each solution covering and accumulating element 910. The two bolts 928a in the first group of bolts and 928b support I_C_O_RAnd Q_C_O_RTime-sharing and multiplexing of sampling are accumulated.

The accumulator 526 can also be programmed to help search for strong instances in the received signal. For example, the accumulator 526 can accumulate I and Q vectors of different compensations in each of the eight accumulators of the following energy squared. If the leading reference frame is covered with Walsh coded zeros, there is no need to decover at the receiver unit. In the specific example shown, the accumulator 526 can be programmed to process four different time compensations at the same time, each time compensation being processed by a pair of individual de-covering and accumulating elements 910.

In some specific examples of the present invention, the microcontroller 232 is used to receive the work sent by the controller 240 and direct the calculation of various elements of the receiver unit 200 to perform the sent work. Each work can be defined as including a series of calculation steps or some other work. For example, you can send a job to process a special multipath in special time compensation, search for strong signal instances in a special time window, etc. The search can use the guidance correlator 522 and the accumulator 526 to correlate the preamble signals at a specific PN compensation in a special time interval (for example, 96 chips). You can also send a job to process all specified multiple paths, search for strong signal examples at multiple time compensations, etc. In a specific example, the microcontroller 232 triggers an appropriate working state machine for each received job and maintains the working state machine for the duration of the job. Depending on the particular work to be processed, the microcontroller 232 can also trigger one or more additional work state machines for lower-level work. When the special work is completed, the microcontroller 232 will notify the controller 240.

Search jobs, data processing jobs, signal processing jobs, and other jobs The processing to be executed is described in further detail in the following patents and patent applications, which are assigned to the assignee of the present invention and are fully referenced here: 1) U.S. Patent Nos. 5,644,591 and 5,805,648, The titles are "METHOD AND APPARATUS FOR PERFORMING SEARCH ACQUISITION IN A CDMA COMMUNICATIONS SYSTEM"; 2) U.S. Patent Nos. 5,867,527 and 5,867,527, the titles are "METHOD OF SEARCHING FOR A BURSTY SIGNAL"; 3) U.S. Patent Nos. 5,764,687, the title is " MOBILE DEMODULATOR ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM"; 4) US Patent No. 5,577,022, titled "PILOT SIGNAL SEARCHING TECHNIQUE FOR A CELLULAR COMMUNICATIONS SYSTEM"; 5) U.S. Patent No. 5,654,979, titled "CELL SITE DEMODULATION ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEMS"; 6) U.S. Patent Application Serial No. 08/987,172, titled "MULTI CHANNEL DEMODULATOR", on December 9, 1997 Filing; and 7) US Patent Application Serial No. 09/283,010, titled "PROGRAMMABLE MATCHED FILTER SEARCHER", filed on March 31, 1999.

FIG. 10 shows a block diagram of a specific specific example of the microcontroller 232 that can be used to control the operations of the elements of the receiver unit 200 (for example, the buffer 224 and the data processor 230). The microcontroller 232 includes a sequence controller 1012 coupled to the counter 1014 and latches 1016a and 1016b. The counter 1014 and the latch 1016a are further coupled to the latches 1016c and 1016d, respectively, which are further coupled to the data bus 510.

The latch 1016b stores the state of the microcontroller 232 and can be integrated in the serial controller 1012. The latch 1016d receives the work word group sent by the controller 240 from the data bus 510. The latch 1016c receives from the data bus 510 one or more parameter values applied in the sent job. Such parameter values specify, for example, the time interval for performing the search function. During the execution of the work, the counter 1014 counts down the specified time interval and provides a signal indicating the end of the time interval to the sequence controller 1012.

In a specific example, in order to simplify the design and reduce circuit complexity and cost, the sequence controller 1012 is implemented by using combined logic. The logic will implement the work state machine needed to serially transmit the sent work. Each working state opportunity provides guidance for the operation of various elements in the receiver unit, such as buffer 224, correlator 522, symbol demodulator and combiner 524, accumulator 526, and buffer/deinterlacer 234 Appropriate control signal. The control sequence transmits signals for various functions and controls the buffer and processing elements to perform the sent work. For example, the control signal controls each multiplexer in FIG. 6C (for example, multiplexers 612, 622, and 546) to select appropriate input to the multiplexer to provide the buffer Buffer 224 and buffer/de-interval inserter 234. The sequence controller 1012 will further direct the operations of the address generators 512 and 542 to generate the required addresses.

FIG. 11A is a time chart of the data sampling process of the data processor 230 when the time compensation is zero. In this example, two data samples are available per chip cycle and each data sample has a resolution of four bits. For each 32-bit read operation, 16 complex numbers of 8-chip cycles can be retrieved from the buffer 224_P_NAnd Q_P_NSampling or four complex data sampling in 2-chip cycles.

In the first clock cycle, the complex PN samples of eight chips are retrieved from the buffer 224 and provided to the latch 732 in the correlator 732 (see FIG. 7A). In the second clock cycle, the data samples of the first two chips corresponding to time compensation 0.0, 0.5, 1.0, and 1.5 are retrieved from the buffer 224 and locked by the latches 712a, 712b, 712c, and 712d, respectively. In the third clock cycle, the samples in the latch 712 will be re-locked by the latch 714, and the data samples of the next two chips corresponding to time compensation 2.0, 2.5, 3.0, and 3.5 will be retrieved from the buffer 224 and respectively It is locked by latches 712a, 712b, 712c, and 712d. In the fourth time cycle, the first chip data samples corresponding to time compensations of 0.0 and 0.5 are correlated by the multipliers 720a and 720b in the correlator 522, respectively. In the fifth clock cycle, the correlator 522 is idle. In the sixth clock cycle, the second chip data samples corresponding to time compensations of 1.0 and 1.5 are correlated by multipliers 720c and 720d, respectively. The processing performed in the seven to ten and clock cycles will be the same as the processing performed in the clock cycles three to six. The data processing also It will continue in the same way until the next set of PN samples is needed and captured.

FIG. 11B shows a time chart of the data sampling process of the data processor 230 with a time compensation of 1.5. In a specific example, the data samples retrieved from the buffer 224 will start at an even chip index (eg, 0, 2, 4, etc.). Therefore, the time compensation for a particular multipath can be divided into an integer part and a fractional part. The integer part will identify the special even chip index from which the data sample can be retrieved. The fractional part will identify the special half-chip compensation in the captured data sample.

As shown in FIG. 11B, PN samples and data samples are retrieved from the buffer 224 in the same manner as the time compensation zero. However, in the third clock cycle, the data processing is performed on the data sampling corresponding to the time compensation of 1.5. In particular, the data samples of time compensation 1.5 and 2.0 will be correlated by multipliers 720d and 720a, respectively. Similarly, in the fifth clock cycle, the data samples of time compensation 2.5 and 3.0 will be correlated by multipliers 720b and 720c, respectively. Then the data processing will continue in the same way.

The receiver unit as described above can be beneficially used in a user terminal or base station in a communication system. The signal processing of the forward and reverse connections can be different and generally depends on the particular CDMA standard or system implemented. At the same time, the necessary conditions for the user terminal will be different from that of the base station. For example, usually a user terminal must process a single transmission from a base station or redundant transmissions from multiple base stations. On the contrary, a base station must process multiple user terminals at the same time ( And different) transfer. Therefore, usually the receiver unit will be A special design for a special application.

The above-mentioned elements of the receiver unit 200 (for example, the address generator 220, the input data interface 222, the buffer 224, the data processor 230, the microcontroller 232, the controller 240, etc.) can be implemented in one or more applications Circuit (ASIC), digital signal processor, controller, microcontroller, microprocessor, or other electronic unit designed to perform the functions described herein, or a combination thereof. The buffer 224 and the buffer/de-interpolator 234 can be implemented in one or more random access memory (RAM), dynamic RAM (DRAM), FLASH memory, or other memory technology devices. At the same time, the buffer 224 and the buffer/despacing inserter 234 can also be implemented in the same integrated circuit used to implement other elements of the receiver unit 200.

For the sake of clarity, many viewpoints and specific examples of the present invention have been specifically described in the content transmitted to the connection data before the HDR CDMA system. However, the present invention can also be applied to reverse connection data transmission and other communication systems (for example, IS-95 CDMA system, W-CDMA system, etc.).

The foregoing preferred specific examples have been presented, so that those who are familiar with the art can use and utilize the present invention. Those who are familiar with the art can easily make various modifications to these specific examples, and the general principles defined here can be applied to other specific examples that do not use the functions of the present invention. Therefore, the present invention is not limited to the specific examples shown here but covers the widest range consistent with the principles and novel features disclosed herein.