Method and device to process received signal in communication system
Abstract
FIELD: radio engineering. SUBSTANCE: device to process received signals comprises the first facility, which receives and stores samples transformed into digital form, with specific repetition rate of samples, and the second facility, which extracts segments of samples, transformed into digital form, from the first buffer, and processes extracted segments with the help of a certain specific set of parameter values, besides, the frequency of clock signal of the second facility processing exceeds the repetition rate of samples. Multiple copies of received signals may be processed by extraction and processing of multiple segments of samples, transformed into digital form, from the first facility. In a typical case the receiving facility also includes a buffer, which receives and processes the received signal to produce samples transformed into digital form, a processor and a controller, which sets tasks for a data processor. EFFECT: increased efficiency of processing. 36 cl, 19 dwg
Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
36 claims: 2 independent, 34 dependent
- 1A device for processing received signals, comprising:first means for receiving and storing the digital samples with a specific sampling frequency, ivtoroe means associated with the first means for extracting from the first means segments the digital samples and processing the extracted segments using a particular set of parameter values, wherein the second means operates based on the clock signal processing having a frequency exceeding the sampling frequency, wherein the second means comprises a correlator that provides compression retrieved segments of digitized samples with corresponding segments of PN sequences compression for correlated samples, the correlator includes an interpolator adapted to receiving and interpolating the despread samples to generate interpolated samples that are output as the correlated samples, wherein the interpolator includes one or more pairs of scaling elements, each of which is designed to receive and scale respective despread samples with a particular gain to generate scaled samples, and one or more adders each connected to a respective pair of scaling elements and is designed to receive and sum the scaled samples from the pair of scaling elements to generate the interpolated samples. 1. Устройство для обработки принимаемых сигналов, содержащее:первое средство для приема и сохранения цифровых выборок с конкретной частотой выборок, ивторое средство, связанное с первым средством, для извлечения из первого средства сегментов цифровых выборок и обработки извлеченных сегментов, используя конкретный набор значений параметров, причем второе средство функционирует на основе тактового сигнала обработки, имеющего частоту, превышающую частоту выборок,при этом второе средство содержит коррелятор, обеспечивающий сжатие извлеченных сегментов цифровых выборок с использованием соответствующих сегментов псевдослучайных шумовых последовательностей сжатия для получения коррелированных выборок, причем коррелятор содержит интерполятор, предназначенный для приема и интерполирования сжатых выборок для формирования интерполированных выборок, которые выдаются в качестве коррелированных выборок, при этом интерполятор содержит одну или более пар масштабирующих элементов, каждый из которых предназначен для приема и масштабирования соответствующих сжатых выборок с использованием конкретного коэффициента усиления для формирования масштабированных выборок, и один или более сумматоров, каждый из которых соединен с соответствующей парой масштабирующих элементов и предназначен для приема и суммирования масштабированных выборок от пары масштабирующих элементов для формирования интерполированных выборок. 1. Устройство для обработки принимаемых сигналов, содержащее:первое средство для приема и сохранения цифровых выборок с конкретной частотой выборок, ивторое средство, связанное с первым средством, для извлечения из первого средства сегментов цифровых выборок и обработки извлеченных сегментов, используя конкретный набор значений параметров, причем второе средство функционирует на основе тактового сигнала обработки, имеющего частоту, превышающую частоту выборок,при этом второе средство содержит коррелятор, обеспечивающий сжатие извлеченных сегментов цифровых выборок с использованием соответствующих сегментов псевдослучайных шумовых последовательностей сжатия для получения коррелированных выборок, причем коррелятор содержит интерполятор, предназначенный для приема и интерполирования сжатых выборок для формирования интерполированных выборок, которые выдаются в качестве коррелированных выборок, при этом интерполятор содержит одну или более пар масштабирующих элементов, каждый из которых предназначен для приема и масштабирования соответствующих сжатых выборок с использованием конкретного коэффициента усиления для формирования масштабированных выборок, и один или более сумматоров, каждый из которых соединен с соответствующей парой масштабирующих элементов и предназначен для приема и суммирования масштабированных выборок от пары масштабирующих элементов для формирования интерполированных выборок.
- 2A device for processing received signals in a radio communication system soderzhascheepervoe means for receiving and storing the digital samples with a specific sampling frequency, second means associated with the first means, for extracting the segments of digitized samples from the first memory means and processing each of the retrieved segments with a particular set of parameter values, wherein the second means using the clock signal processing having a frequency exceeding the sampling frequency, third means associated with said second means and adapted for scheduling tasks for the second means for processing signals from the second means, ichetvertoe means associated with the third means, and for receiving the scheduled tasks and to generate a set of control signals for controlling the operation of said first means and second means to perform the scheduled task, wherein the fourth means comprises a group of latches for securing the dispatched task and one or more parameters for use in the scheduled task at least one counter, each counter is associated with a respective latch and provides grant indication signal based on the value stored in the latch, and a controller setting sequence for receiving the at least one indication signal and the dispatched tasks and to generate a set of control signals. 2. Устройство для обработки принимаемых сигналов в системе радиосвязи, содержащеепервое средство для приема и сохранения цифровых выборок с конкретной частотой выборок,второе средство, связанное с первым средством, для извлечения сегментов цифровых выборок из первого средства и обработки каждого из извлеченных сегментов с использованием конкретного набора значений параметров, причем второе средство использует тактовый сигнал обработки, имеющий частоту, превышающую частоту выборок,третье средство, связанное со вторым средством и предназначенное для диспетчеризации задач для второго средства и для обработки данных сигнализации от второго средства, ичетвертое средство, связанное с третьим средством и предназначенное для приема диспетчеризованных задач и для формирования набора управляющих сигналов для управления работой первого средства и второго средства для исполнения диспетчеризованных задач,при этом четвертое средство включает в себя группу регистров-фиксаторов для фиксации диспетчеризованной задачи и одного или более значений параметров для применения в диспетчеризованной задаче, по меньшей мере, один счетчик, при этом каждый счетчик связан с соответствующим регистром-фиксатором и обеспечивает выдачу сигнала индикации на основе значения, сохраненного в регистре-фиксаторе, и контроллер установления последовательности, предназначенный для приема, по меньшей мере, одного сигнала индикации и диспетчеризованной задачи и для формирования набора управляющих сигналов. 2. Устройство для обработки принимаемых сигналов в системе радиосвязи, содержащеепервое средство для приема и сохранения цифровых выборок с конкретной частотой выборок,второе средство, связанное с первым средством, для извлечения сегментов цифровых выборок из первого средства и обработки каждого из извлеченных сегментов с использованием конкретного набора значений параметров, причем второе средство использует тактовый сигнал обработки, имеющий частоту, превышающую частоту выборок,третье средство, связанное со вторым средством и предназначенное для диспетчеризации задач для второго средства и для обработки данных сигнализации от второго средства, ичетвертое средство, связанное с третьим средством и предназначенное для приема диспетчеризованных задач и для формирования набора управляющих сигналов для управления работой первого средства и второго средства для исполнения диспетчеризованных задач,при этом четвертое средство включает в себя группу регистров-фиксаторов для фиксации диспетчеризованной задачи и одного или более значений параметров для применения в диспетчеризованной задаче, по меньшей мере, один счетчик, при этом каждый счетчик связан с соответствующим регистром-фиксатором и обеспечивает выдачу сигнала индикации на основе значения, сохраненного в регистре-фиксаторе, и контроллер установления последовательности, предназначенный для приема, по меньшей мере, одного сигнала индикации и диспетчеризованной задачи и для формирования набора управляющих сигналов.
Independent claims2
180 paragraphs in 5 sections, as filed
TECHNICAL FIELD OF THE INVENTION
The present invention relates to data communication. More particularly, the present invention relates to a method and apparatus for efficiently processing a received signal in a communication system.
BACKGROUND
In a typical digital communications system, data is processed in the transmitter are modulated, and transmitted in line to the receiving device. Processing data may include, for example, formatting the data to convert them to some particular frame format, encoding the formatted data to provide error detection and correction at the receiver, the encoded data separation channels (i.e., masking) data extension separated through channels within the system bandwidth, etc. Typically, data processing is determined in part implemented by the system or standard being implemented.
In the receiving apparatus is received, matching, demodulation and digital processing of the received signal to recover the transmitted data. Processing at the receiver is complementary to that which is performed in the transmitting device, and may include, for example, compression of the received samples, decovering the despread samples to generate decovered symbols, decoding the decovered symbols, etc. Due to multipath and other phenomena of the transmitted signal can reach a receiver through multiple signal channels. To provide improved performance receiver is typically configured to process multiple (and having a very high (more pronounced)) instances of the received signal.
To perform the required signal processing, some conventional receiver units are made with some amount of processing elements, each of which is specifically designed and selected to perform a specific function. For example, the receiving device may be equipped with a searcher element and a certain number of data processing elements. Searcher element searches the received signal to determine the strongest (pronounced) signal instances and to process specific signal instances having a sufficient signal level, elements are provided for data processing. Implementation of multiple parallel processing elements results in increased circuit complexity and cost. Elements for treatment typically have fixed structure and they are usually not allowed to program (i.e., the processing of the received signal with different sets of parameter values to perform, for example, processing using the pilot signal searching and demodulation Data). Moreover, the number of signal instances that can be processed is limited by the amount of processing elements implemented.
To reduce complexity, some other receivers equipped with a number of parallel blocks pretreatment processor connected to the shared data channel. Each pre-processing unit performs partial processing (e.g., compression and masking) the selected signal instance. The processor shared data channel carries the rest of the processing (e.g., demodulation pilot, energy calculation, etc.) partially processed data. Again, a limited number of signal instances that can be processed is determined based on the number of blocks implemented pretreatment and programming is usually not provided.
With respect to the user terminal should be noted that the ability to handle multiple instances of the received signal can provide improved performance. With respect to the base station should be noted that typically requires multiple users simultaneously processing multiple signal instances, further substantiates the need for efficient signal processing techniques. The ability to process signals for multiple users using a small number of signal processing elements is economically and technically desirable for various reasons, such as for example high density arrangement of circuit boards, fewer components, lower costs, etc. Programmability in the elements of the signal processing is also desirable in communications systems that can transmit data using various parameter values (e.g., different code division channels having different lengths) depending on various factors, such as baud rate.
As can be seen, techniques that can provide effective treatment of the received signal in a communications system are highly desirable.
SUMMARY OF THE INVENTION
The present invention provides an elegant demodulator design having numerous advantages over conventional designs. In accordance with some aspects, the invention provides a data processing unit for tracked many computationally intensive operations and a controller is provided for solving other tasks needed to process (e.g., demodulate) a received signal. This controller architecture provides the ability to manage multiple copies of the signal processing and support many users simultaneously. In some designs, the microcontroller can be provided for the implementation of "micromanagement" data processing unit and the controller release of some management responsibilities associated with the establishment of a sequence of instruction execution low (ordering at a low level), the data processing unit. These various features allow to develop a simplified design having improved performance over conventional designs.
The data processor and controller can be designed to work with handling synchronization signals which may be asynchronous with respect to the repetition frequency of the received samples and typically receives more often mentioned samples. More frequent arrival timing signals enables the processing of more instances of the received signal with no additional increase in circuit complexity, and provides an increase in processing capacity proportional to the frequency synchronization signals. The data processing unit may also be configured to allow the processing of data based on programmable parameter values, which provides increased flexibility and enhanced functionality. For example, it can be made programmable search time interval, code division channels (e.g., Walsh codes), the time shift, and other parameters. The data processing unit may also be configured to combine the processing elements to reduce the complexity and cost of the circuit.
In one embodiment, the invention provides a receiver for use in either a user terminal or the base station radio system (e.g., multiple access, code-division multiplexing (CDMA system (CDMA))). The receiving apparatus includes a first buffer connected to the data processing unit. This first buffer receives and stores digitized samples and transmitted with a specific repetition frequency samples (and may also store sample pseudorandom (PN sample) used to compress the digitized samples). The data processor retrieves segments of digitized samples from the first buffer and processes the selected segments via a particular set of parameter values. The operation of the data based on synchronization signals processing having a frequency that is higher (for example, ten or more times higher) chip rate. Multiple copies of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer.
Typically, the receiving device also includes a receiver and a controller. The receiver receives and processes a transmitted signal for issuing digital samples. The controller distributes tasks to the processing unit processes the data and signaling information coming from the data processing unit.
The data processing unit may be configured such that would include a correlator, a demodulation and symbol combining, a first accumulator and a second buffer, or some aggregate. Correlator compresses the selected segments of digitized samples with corresponding segments using a pseudorandom (PN) sequences for compressing correlated samples. And a demodulation symbol combiner receives and further processes the correlated samples to provide processed symbols. The second buffer stores the processed symbols, and can be configured to deinterleaving processed symbols. With such a structure, the second buffer may be partitioned into two or more sections, with one section to store processed symbols for a current packet and another section to store processed symbols for a prior processed packet. The symbols for the current packet can be processed while the symbols for the prior packet are issued in the element for further signal processing.
The correlator may be designed in such a way that would include a despreader, a second accumulator (samples) and the interpolator, or some aggregate. The despreader includes a set of K multipliers that are simultaneously compressed group containing up to K complex digitized samples. The accumulator includes a sample group of K adders connected to a group of K multipliers, each combiner receives and combines samples from respective groups of blocks of multiplication. The interpolator receives and interpolates the compressed samples to form the interpolated samples.
A demodulation and symbol combining may be performed in such a way that would include unmasks element, a demodulation pilot signal and the third accumulator (characters) or some of their totality. Unmasks element receives and decovers the correlated samples them with one or more channelization codes to provide decovered symbols. Codes separation channels may be Walsh codes having a length that is programmable and defined by the parameter values. A demodulation pilot demodulates the decovered symbols with the pilot symbols to provide demodulated symbols. A symbol accumulator sums the demodulated symbols with the accumulation of multiple copies of the signal to obtain the processed symbols.
Unmasks element may be implemented as a FHT element (FHT (FHT)) having L stages, and can be configured in such a way that will fetch and process inphase and quadrature correlated samples on alternating clock cycles throughout. FHT element may be configured to decover using one or more Walsh symbols having a (programmable) length of 1, 2, 4, 8, 16, 32, 64 or 128 or some other length.
The first accumulator receives and processes the correlated samples for issuing the accumulated results. The first accumulator can be configured to accumulation summing the correlated samples over a programmable time interval to provide pilot estimates. The first accumulator may include a number of accumulation summing elements, each summing the accumulation element for producing a control signal evaluation at some particular time offset.
The repetition frequency of sampling may be asynchronous with respect to the clock signal processing. In this case, the controller may be configured to implement synchronization loop delay, which tracks the frequency of the chip digital samples and provides the reset value, which is used to generate a signal subsequently used for recording packets of digitized samples in a first buffer, starting from the intended for that cell.
The controller may be configured to maintain synchronization of a finite state machine for each signal instance being processed. Synchronization of each finite state machine can be maintained using a "wired" programming a digital signal processor (DSP), and it may include a contour tracking time used to (1) monitor the progress signal instance being processed and (2) forming the time shift corresponding to signal replica. This time shift may be used to extract from the first buffer proper segment of samples for processing. The controller may also receive a timing signal, which may be used to initiate processing of the segments of samples. This timing signal can be generated based on the comparison value outputted from the controller.
The receiving device may also include a microcontroller which receives the tasks assigned by the controller, and generates a group of control signals to guide the elements in the receiving apparatus. The microcontroller is able to set the task state machine for each task being processed, and may include a sequencing controller that receives one or more indicator signals and the tasks and generates a group of control signals.
In another embodiment, the invention provides a method of processing a received signal in a wireless communication system. In accordance with this method, the transmitted signal is received, processed, and digitized to provide digitized samples at a particular repetition frequency samples. The samples are then digitally buffered in the first buffer, and segments of digitized samples recovered from the first buffer and processed using the first particular set of parameter values, some of which may be programmable. The treatment is carried out on the basis of the synchronization signal processing having a frequency which is higher than the repetition rate of the samples.
Processing may include a certain set of consecutively provided (1) compressing the extracted selected segments of digitized samples using respective segments pseudorandom despreading sequence to obtain the correlated samples, (2) decovering the correlated samples with one or more channelization codes to provide decovered symbols, (3 ) demodulating the decovered symbols with the pilot symbols to provide demodulated symbols, and (4) summing the accumulation demodulated symbols from multiple signal instances to provide processed symbols.
BRIEF DESCRIPTION OF DRAWINGS
The features, characteristics and advantages of the present invention will become more apparent upon consideration of the detailed description given hereinafter with reference to the drawings, wherein like numerals designate like elements throughout the drawings, and wherein:
1 is a simplified block diagram of a communication system;
2 is a block diagram of a specific embodiment of a receiver apparatus for receiving and processing a modulated signal;
3 is a diagram of a frame format for data transmission on the forward link in accordance with the system of code division multiple access channels (CDMA (CDMA)) with high data rate (HDR (HDR)) (HDR CDMA system);
4 is a block diagram of an embodiment of processing received data which can be used for processing the data on the forward link in the HDR CDMA system;
5 is a block diagram of a specific embodiment of the data processing unit according to the invention;
6A and 6B are diagrams illustrating record data samples in the buffer and reading data samples from the buffer and writing the PN samples into the buffer and reading of PN samples from the buffer, respectively;
6C is a block diagram of a specific embodiment of the data buffering for the receiver design shown in Figures 2 and 5;
7A is a block diagram of a specific embodiment of a correlator in the data processing unit shown in Figure 5;
7B is a block diagram of a specific embodiment of a multiplier that can perform complex compression;
7C is a diagram that illustrates linear interpolation;
7D is a block diagram of a specific embodiment of an interpolator;
8A is a block diagram of a specific embodiment of a symbol demodulator and combiner in the data processing unit shown in Figure 5;
8B is a block diagram of a specific embodiment of a fast Hadamard transform (FHT);
8C is a block diagram of a specific embodiment of a demodulation pilot signal;
9 is a block diagram of a specific embodiment of an accumulator for processing traffic data, pilot reference, and other signaling data;
10 is a block diagram of a specific embodiment of a microcontroller that can be used to control the operation of elements of the receiving device, and
11A and 11B are timing charts of processing the data samples in the data processing unit time offsets equal to zero and 1.5, respectively.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
1 is a simplified block diagram of an embodiment of the signal processing in the transmission of signals in communication system 100. In the transmitting apparatus 110 the data is sent, typically in packets from a data source 112 to the processing unit 114 transmit (TX) data, which formats, codes, and processes the data to generate baseband signals. Then, the baseband signals are supplied to a transmitter (TMTR) 116, quadrature modulation, filtering, amplification and upconversion to generate a modulated frequency signal which is transmitted via antenna 118 to one or more receivers.
At the receiver 130 the transmitted signal is received by antenna 132 and issue it to the receiver (RCVR) 134. Within receiver 134 the received signal is amplified, filtered, subjected to frequency down conversion, quadrature demodulation translated to baseband and converting in for digitized inphase (I) and quadrature (Q) samples. These samples are provided to a processing 136 of the received (RX) data, which are decoded and processed to recover the transmitted data. The decoding and processing at receiver unit 130 are performed in a manner which is complementary to the coding and processing carried out in the transmitting apparatus 110. Then, the recovered data is output to the data receiver 138.
The above-described signal processing supports packet data, messages, video information, voice information, and the link causing other types of transmission in one direction. However, the processing of the signal passing in the other direction is not shown in Figure 1 only for the sake of clarity.
Communication system 100 may be multiple-access system with code division multiple access (CDMA) system that supports voice and data communication between users over a terrestrial link. Using methods MDKR in a multiple access communication system is described in U.S. Patent number 4901307, entitled "SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS" («communications system of multiple access spread spectrum signal that uses SATELLITE OR TERRESTRIAL REPEATERS") U.S. Patent number 5103459, entitled "SYSTEM AND METHOD FOR GENERATING WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM" («A system and method for generating signals in a CDMA cellular telephone"). Another specific CDMA system is described in US patent number 6574211, entitled "METHOD AND APPARATUS FOR HIGH RATE PACKED DATA TRANSMISSION" («A method and apparatus for high speed packet data"), the application for which is filed Nov. 3, 1997
CDMA systems are typically made to ensure compliance with one or more standards such as the "TIA / EIA / IS-95-A Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System" (the standard version and the temporary 1995 released under the auspices of the Electronic Industries Association and the Association of Communications entitled "Compatibility Standard mobile stations and base stations for Dual-Mode Wideband cellular system transmitting a spread spectrum") (in the following text referred to as the IS-95-A), "TIA / EIA / IS-98 Recommended Minimum Standard for Dual-Mode Wideband Spread Spectrum Cellular System "(Interim Standard 1998, issued under the auspices of the Electronic Industries Association and the Association of Communications entitled" Recommended Standard Minimum requirements to dual-mode mobile station broadband cellular communication system spread spectrum signals ") (in the following text referred to as the IS-98 standard), the standard offered by a consortium named" 3rd Generation Partnership Project "(3GPP) (« Partnership Project in establishing communications third generation "(PSvSS3P)), cm. documents №№ 3G TS 25.211, 3G TS 25.212, 3G TS 25.213 and 3G TS 25.214 (in the following text referred to as standard broadband multiple access CDMA (W-CDMA (W-CDMA)), and the "TR-45.5 Physical Layer Standard for cdma2000 Spread Spectrum Systems "(version TR-45.5« Physical Layer Standard for Spread Spectrum Systems Format cdma2000) (in the following text referred to as CDMA-2000 standard). Note that continuously developed and offered to use new standards CDMA. These CDMA standards are mentioned herein for reference.
2 is a block diagram of a specific embodiment of receiver unit 200 suitable for receiving and processing a modulated signal. Receiver unit 200 is a specific embodiment of receiver unit 130 shown in Figure 1. The modulated signal is received by antenna 212 and 214 are provided to a pretreatment. In block preprocessing the received signal is amplified, filtered, subjected to down-conversion and quadrature demodulation to obtain the baseband signal. Then, the baseband signals are digitized by one or more analog-to-digital converters (ADP (ADC)) using the synchronization signal samples (SCLK (SVYB)) for generating in-phase (IADC) and quadrature (QADC) samples, which are given in circuit data interface 222. Preprocessing unit 214 and ADCs 216 may be implemented in the receiver 134 shown in Figure 1.
Depending on the particular design of receiver unit 200, an analog-to-digital converters 216 and may issue IADC QADC sample with high repetition frequency samples in accordance with signals received from one or more antennas. Data interface circuit 222 may be decimated (i.e., remove) unnecessary samples, and placed (i.e., sort) samples corresponding to each antenna, and collect samples into words suitable for efficient storage in buffer 224. In one particular embodiment, each word comprises 32 bits of data, and each IADC and QADC sample comprises 4 bits of data, wherein each word is placed in four pairs of IADC and QADC samples. It is also possible to use other word widths (e.g., having a width of 16 bits, 64 bits, 128 bits, etc.), which also falls within the scope of the invention. When there is a word for storage, address generator 220 generates a write address data, DW_ADDR (ADR_ZD), and the cell buffer 224 indicates the generated address is written word.
Next, data processor 230 retrieves samples from buffer 224, processes the extracted samples under the guidance of the controller 240 and outputs the processed characters in the buffer unit 234 and deinterleaving. Data processor 230 can sequentially retrieve symbols from buffer 234 and block deinterleaving and sum-accumulate symbols from multiple signal instances to provide accumulated symbols that are then provided back to buffer unit 234 and deinterleaving. When there is a demodulation symbol to be retrieved from the buffer unit 234 and the deinterleaving address generator 236 generates read address data, SR_ADDR (ADR_SD) which is used to issue the symbol to a decoder 260. Data processor 230 may also provide processed signaling data directly to controller 240. The decoder 260 decodes the demodulated symbols in accordance with a decoding algorithm, which is complementary with respect to the encoding algorithm used at the transmitter, and outputs the decoded data to a data receiver 262.
Data processor 230 typically includes a correlator, an accumulator, a demodulation (multiplication) and the combined symbols, or some aggregate, depending on the particular design of the data processing unit. Data processor 230 performs many of the functions required to demodulate the received samples. The data processing unit may be configured to output a demodulated signal directly to the decoder 260 to decode, and the processed data signal - a controller 240 for further processing. Such processed signaling data may include, for example, the accumulated amount of the reference symbol of the pilot signal and a data rate control (DRC (DRC)) for processing the uplink signals, and power control symbols for processing the downlink signals.
The controller 240 may be designed to perform various functions, such as filtering pilot detection timing taps RAKE receiver (cake-receiver) tracking time for each signal instance being processed, maintaining timeslip taps RAKE receiver, frequency tracking ( in the case of the forward link processing in a remote terminal) or some aggregate. The controller 240 also manages the data processor 230 and 234 block buffering and de-interleaving, providing performance of the required functions.
In some designs, the microcontroller 232 is provided, which manages the data processor 230. In such designs, micro-controller 232 receives directives or commands from controller 240 to address specific problems (e.g., for correlation with respect to one or more intended for this receiver RAKE taps). In addition, the microcontroller 232 manages the data processor 230 and other units (eg buffer 224, block 234 buffering and deinterleaving), providing a solution to their respective problems. Microcontroller 232 can reduce the amount of control requested by the controller 240, and the amount of interaction between the controller 240 and other elements. Thus, the microcontroller 232 may release the controller 240 to perform some functions and they support additional channels / users.
For the arrangement shown in Figure 2, the number of users that can be supported, generally increases proportionally to the frequency synchronization signals, issued by a data processor 230 and controller 240. These two kinds of synchronizing signals are independent and, depending on their particular frequencies one of the clock signals typically limits the number of copies of a signal and users that can be supported.
Synchronization signal generator 218 generates a sample clock signal SCLK for ADCs 216 and other timing signals for other elements of receiver unit 200. In one embodiment, the synchronization signal generator 218 includes an independent source of clock signals, which generates a master clock signal and one or more counters synchronization signals in real-time (and / or a phase-locked loop) that generate other clock signals used by the elements located in the receiving apparatus 200. The independent source of clock signals can be implemented as a crystal oscillator, voltage controlled generator or any other type. Counters synchronization signals in real time triggered by the main clock signal and generate clock signals at lower frequencies, but are synchronous with the main clock signal. These timing signals include a SCLK signal samples for synchronizing the analog-to-digital converters, signal PCLK (SINPRD) for synchronizing the data processing unit, the timing signals for the generators 220 and 236 addresses etc. In one particular embodiment, the sample clock SCLK is derived from the master clock signal and has a frequency that is close to the chip rate of the received signal (but not necessarily subjected to a phase-locked to this frequency).
In one particular embodiment, address generator 220 includes data write address generator which generates write address data DW_ADDR, and data read address generator which generates read address data DS_ADDR. Address generator 220 may further include address generators for other data (PN sequences) that may be stored in the buffer 224. In one embodiment, address generator 236 includes symbol write address generator that generates the symbol write address, SW_ADDRESS (ADRES_ZS ) and symbol read address generator that generates the symbol read address, SR_ADDRESS (ADRES_SS). Generators 220 and 236 addresses are described in detail below.
Will now be described in greater detail the implementation and operation of the receiving device 200.
In accordance with the invention developed data processor 230 and controller 240 having a combination of features that provides improved performance and improved efficiency over conventional data processing units. Some of these features are described briefly below.
First, data processor 230 performs many computationally intensive operations and thus allows controller 240 the ability to support many users concurrently. Data processor 230 can be configured to carry out the required processing of the received data and provide demodulated symbols directly to decoder 260. Thus, the controller 240 may be relieved of the intensive data processing (e.g., calculation of scalar products), which need to implement in conventional designs usually equates to the need to have more sophisticated controller and traditionally prevents the controller at the same time maintain such a large number of users or processing a large number of copies of the signal. In addition, the microcontroller 232 may be configured to perform the "micro-management" data processing unit 230 and the controller 240 of the release of certain "vain" management responsibilities.
Secondly, and data processor 230 and controller 240 may operate on a clock signal that may be asynchronous with respect to the repetition rate of the samples which received the sample stored in the buffer 224, and may enter them more often. For example, the frequency of the sampling can be chosen twice the chip rate of the received signal (i.e. fSAM = 2,4 million samples per second), and the synchronization signal PCLK may be selected having a frequency which is more than an order of magnitude higher than the frequency samples (e.g., fPCLK = 50 MHz). If data processor 230 and controller 240 are used for the terminal user, often reaching timing signals provide processing of more instances of the received signal. In this case, the data processor 230 and controller 240 may be used to implement and support more fingers rake receiver with no additional complexity schemes. And if data processor 230 and controller 240 are used at the base station, often reaching timing signals provide processing of received signals from a greater number of users and / or processing of more instances of the received signal.
Third, and data processor 230 and controller 240 may be configured to be able to process data based on programmable parameter values. For example, the controller 240 may select the number of samples, which are accumulated during the search operation, and provide the number to the data processing unit 230. As another example, we note that the data processing unit 230 can be configured to decover the samples with one or more channelization codes having programmable length. In contrast, conventional designs receivers typically include dedicated hardware elements that decide specific set of tasks with little programmability level or in the absence thereof. Symptom programmability of the invention may provide improved performance over conventional designs.
Fourth, data processor 230 and controller 240 may be arranged so that they are available in the processing means provide a lower complexity and lower cost circuits. Each of data processor 230 and controller 240 typically includes a group of processing elements that performs various required functions (e.g., compression, decovering summation accumulation and demodulation pilot signal - in the case of data processor 230 and decover using the pilot signal and the tracking of the time - in case the controller 240). In addressing a particular problem on a segment of samples involved only the items to be processed, which are necessary to solve this problem, and other elements can be switched off or moved to backup mode. To further improve performance of processing elements that are in the data processing unit 230 and a controller 240, typically not duplicated, except in instances where parallel processing is desired. In contrast to this conventional construction receivers typically include duplication of many functions, which can lead to increased circuit complexity and increased costs.
Data processor 230 may be configured to process data in accordance with various CDMA standards and systems. For clarity, the invention will now be described with reference to the system, the essence of which is disclosed in the aforementioned U.S. Patent number 6574211 and referred to in the following text Multiple Access CDMA with high data rate (HDR CDMA system).
3 is a diagram of a frame format for data transmission on the forward link in accordance with the HDR CDMA system. The forward link - for data traffic, pilot reference, and signaling data - is carried out time division multiplexing and in frame transmission from a base station to a specific terminal user. Each frame covers a time unit referred to interval (e.g., having a value of 1.67 for a particular design of the HDR system). Each slot includes fields 302a, 302b and 302c of traffic data fields 304a and 304b pilot reference fields 306a and 306b, and signaling data, i.e. overhead (OH certain characters). Traffic data fields 302 and fields 304, a pilot reference used for transmitting traffic data and pilot reference, respectively. Signaling data field 306 are used to send signaling information, such as for example pointers forward link activity (FAC symbols designated), pointers employment reverse link power control commands uplink etc. Pointers FAC indicates whether a base station for sending data over a particular number of slots in the future. Pointers employment uplink indicate whether the limit is reached reverse link capacity of the base station. A power control commands transmitted by the terminals require users to increase or decrease their power re garden.
In accordance with the HDR CDMA system, prior to transmission of traffic data masked by the Walsh codes corresponding to the channels used for transmitting data and power control data for each user terminal are masked by the Walsh codes assigned to that terminal user. The reference pilot signal masked data traffic and power control data is then expanded using a complex PN spreading sequence generated by multiplying the short PN spreading sequences assigned to the particular transmitting base station for a long pseudo-random sequence assigned to a terminal user.
4 is a block diagram of a specific embodiment of the processing unit 400 receives the data, which can be used for processing the data on the forward link in the HDR CDMA system. The digitized IADC and QADC samples from the receiver are issued a number of data correlators 410 (for simplicity Figure 4 shows only one of them). Due to multipath and other phenomena of the transmitted signal can reach a receiver through multiple signal channels. To provide improved performance receiver is typically configured to process multiple (and having a very high level (i.e., the most pronounced)) instances of the received signal. This conventional design provides a number of data correlators 410, with each data correlator 410 commonly referred to as tap RAKE receiver. Each data correlator 410 can be provided for processing a specific copy of the received signal.
The correlator 410 and data IADC QADC samples are provided to a complex multiplier which also receives a complex PN despreading sequence from blocks 414a and 414b multiply. This complex PN despreading sequence is generated by multiplying the short pseudo-phase (PNI) and quadrature long pseudorandom (PNQ) sequences corresponding to the base station from which the signal is received, a long pseudo-random sequence assigned to receiver unit 400. These PN sequences have time offsets corresponding to a particular signal instance being processed by the correlator 410 data.
Block 412 performs a complex multiplication of complex multiplication and IADC QADC samples for complex pseudo-random sequence of compression and provides the integrated compressed-phase and quadrature (IDES and QDES) sample telltale Walsh elements 422 and 442. Compressed IDES sample also issued in unmasking Walsh element 432.
Unmasks Walsh element 422 decovers compressed IDES and QDES samples with the Walsh codes used for masking data at a base station and generates a number of streams of decovered samples, one stream for each channel used for data transmission. Thereafter, sample streams are issued symbol accumulator 424 that sums the accumulation samples in each stream based on the data rate of a channel used for transmitting the stream. For each stream, the accumulator 424 adds to the accumulation of a number of decovered samples to generate decovered symbols. The decovered symbols are then provided to a demodulation block 426 the pilot signal.
Unmasks Walsh element 432 decovers compressed IDES samples with the particular Walsh code WF (e.g., Walsh code equal to 0), is used for masking the pilot reference at the base station. The decovered pilot samples are then provided to an accumulator 434 and added with accumulation over a specific period of time (for example, equal to the duration of the reference pilot signal or the period of the pilot reference) for forming a pilot symbol. Then, the pilot symbols are given to the filter 436 and the pilot signal used for generating a reconstructed pilot signal. The reconstructed pilot signal comprises estimated or predicted pilot signals for the periods of time that pass between the reference pilot signals and outputted to the demodulation unit 426 pilot signal.
Demodulation unit 426 performs pilot coherent demodulation of the decovered data symbols received from the accumulator 424 using the pilot symbols received from the filter 436 the pilot signal and outputs the demodulated data symbols to a symbol combiner 450 unit. Coherent demodulation is carried out by calculating the scalar product and vector product decovered data symbols, pilot symbols, as described below. Scalar and vector product substantially display phase demodulation data and additional scaling of the result from the relative recovery level of the pilot signal. Scaling control signals via leads to the effective "weight" of contributions from different instances of the received signal in accordance with the quality of the copies of the received signal with effective unification. Thus, scalar and vector product of playing the dual role of the characteristics of the coherent RAKE receiver as projection phases and weighing signal.
Symbol combining unit 450 receives the demodulated data symbols from each of the selected data correlator 410, coherently combines the symbols, and provides recovered data symbols 452 into blocks deinterleaving. Block deinterleaver 452 reorders the symbols in a manner which is complementary with respect to the method which is implemented at the base station. The data symbols from the block deinterleaver 452 and then decoded by the decoder 460 and outputted to a data sink.
Design and operation of a rake receiver for a CDMA system is further described in U.S. Patent number 5764687, entitled "MOBILE DEMODULATOR ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM" («Architecture demodulator mobile station for multiple access communication with spread spectrum signals"), and U.S. Patent number 5490165 entitled "DEMODULATION ELEMENT ASSIGNMENT IN A SYSTEM CAPABLE OF RECEIVING MULTIPLE SIGNALS" («Allocation demodulation element in a system capable of receiving multiple signals"). The scalar product of the pilot carrier and the (optimal) weighting channel RAKE receiver fingers further described in U.S. Patent number 5,506,865, entitled "PILOT CARRIER DOT PRODUCT CICRUIT" («scheme for calculating the scalar product of pilot carrier).
In the HDR CDMA system, power control data for a particular user terminal are masked specific Walsh code assigned to the terminal and transmitted in each slot. Thus, in the correlator 410, the data compressed IDES and QDES samples unmasked unmasking Walsh element 442 with the assigned Walsh code. The decovered power control signal samples are then provided to an accumulator 444 and added with the accumulation in the time duration of sending the power control signal for generating a power control bit for the signal instance being processed. The power control bits allocated to all of the data correlators 410 may be coherently combine (for simplicity not shown in Figure 4) to form a combined power control bit that is then used to adjust the transmit power of the user terminal.
5 is a block diagram of a specific embodiment of data processor 230, which is capable of processing data transmissions on the forward and reverse links for various CDMA systems. For example, data processor 230 can be configured to hold the signal processing using a pilot reference for coherent demodulation for data transmission on the forward link in the HDR CDMA system, as described in Figure 4.
Returning to Figure 2, note that IADC and QADC samples from ADCs 216 are formatted data input interface 222 and stored in buffer 224. In one embodiment, buffer 224 is implemented as a circular two-dimensional buffer having a size selected based on a number factors, such as the repetition frequency at the input samples, the frequency of the samples at the output, etc. Buffer 224 is configured to store data samples received over a particular period of time (e.g., for two frames of samples, or some other period). This time period is selected to be sufficiently large to ensure the collection of sufficient data for all processed signal channels, but small enough to prevent the writing of new samples over old, unprocessed samples. The time period during which the collection and storage of samples, may be programmable.
In one embodiment, to erase data stored in the buffer 224, each row of the buffer has a width that matches the width of the output word of input data interface 222 (of for example, 32 bits). When a word becomes available for writing to buffer 224, write address generator 512a generates a data write address data, DW_ADDR, corresponding to the next available row in buffer 224. Then, in the buffer line 224 indicates the generated address is written word. Thereafter, the stored samples are available for retrieval and processing by data processor 230.
Data processor 230 may be prescribed processing of the samples in accordance with a particular set of parameter values. For traffic data processing unit 230 can execute instructions providing: (1) compressing and decover a particular copy of the received signal with a particular timing offset; (2) implementation of a demodulation decoded decovered pilot symbols, and (3) coherent combining demodulated symbols corresponding to different copies of the signal, etc. For data signaling (e.g., pilot signal and power control) data processor 230 can execute instructions providing: (1) compressing and / or decover a particular copy of a received signal; (2) summing the accumulation decovered samples over some specific time interval; (3) combining the accumulated symbols from various signal instances, and the like Data processor 230 can also be operated to search for copies with a high level of the received signal. Data processor 230 may also be configured to be operated and for performing various signal processing, depending on the particular CDMA standard or system and the particular support data transmission (direct or reverse link).
Block 234, and the deinterleaving buffer maintains the processed symbols received from the data processing unit 230. When a symbol is processed by data processor 230 and becomes available for writing to the block 234 buffering and deinterleaving generator 542a write address symbols generates a write address symbol, SW_ADDR, corresponding appropriate cell in block 234 buffering and deinterleaving indicated with the generated write address symbol. Thereafter, the stored symbols may be returned to the data processor 230 for further processing (e.g., summing the accumulation of processed symbols for another signal instance). Thus, the buffer unit 234, and stores the results of interleaving the demodulation pilot signal for the first copy, and stores the results in the accumulation of a demodulation pilot signal for subsequent copies.
By forming the proper read addresses and write characters buffering unit 234 and deinterleaving can be used to reorder the symbols in accordance with a specific deinterleaving algorithm. When the characters are ready to issue the decoder 260, the controller 240 initiates the reading process at the appropriate time. Address generator 542b then generates the proper symbol read addresses to achieve the desired symbol de-interleaving. Subjected deinterleaved (i.e., demodulated) symbols are given to the decoder 260 for decoding.
In the embodiment shown in Figure 5, phase and quadrature samples from buffer 224 are issued to the correlator 522 at block 230 data. The correlator 522 also receives a complex PN despreading sequence, which may also be stored in buffer 224 or generated by a pseudo-random generator of pseudorandom sequences (not shown in Figure 5). For data traffic correlator 522 compresses phase and quadrature samples with the complex PN despreading sequence to provide despread samples. Thus, the correlator 522 performs the compression function, which performs complex multiplication block 412, shown in Figure 4. Correlator 522 may also be designed to perform other functions, such as the accumulation of the accumulation multiple despread samples for each chip interval duration, interpolation despread samples etc. Compressed samples 524 are provided to a symbol demodulator and combiner.
Demodulation unit 524 and the symbol combining can be configured to decovering, coherent demodulation pilot, symbol combining for multiple signal instances, symbol accumulation addition with respect to the repeated symbols in a packet, or perform some set of these operations. Unmasking unit 524 for demodulating and combining symbols received compressed samples from correlator 522 and performs decovering with a set of Walsh symbols. In one particular embodiment, the length of the Walsh symbols is programmable and can be selected equal to 1, 2, 4, 8, 16, or the length may be equal to any other value (e.g., 32, 64, 128, etc.).
For coherent demodulation unit 524 demodulating and symbol combiner receives and coherently demodulates the decovered data symbols with the recovered pilot symbols to generate demodulated symbols that are stored in the buffer 234 and deinterleaving. For symbol combining unit 524 symbol demodulation and combiner receives and combines demodulated symbols corresponding to different copies of the signal to generate recovered symbols that are stored back in block 524 and the symbol combining demodulation. Thus, the control unit 524 and the demodulation symbol combiner may perform those functions that perform data correlator 410 and symbol combining unit 450 shown in Figure 4.
Block 234 buffering and deinterleaving stores intermediate and final results of the accumulation of characters. Processed symbols from unit 524 demodulation and combining characters are written to the cell block 234 buffering and deinterleaving indicated generator 542 addresses writing characters who are in the generator 236 addresses. Recorded characters are extracted from the cell block 234 buffering and deinterleaving indicates read address generator 542b characters. By forming the proper symbol read address buffer unit 234 and deinterleaving can be used to implement the symbol deinterleaving process that is complementary with respect to the method, which is implemented in the transmitter. Characters extracted from the buffer unit 234, and the deinterleaving are demodulated symbols, which are given to a decoder 260.
For signaling data correlator 522 can be configured to provide compression phase and quadrature samples with the complex PN despreading sequence, and outputting the despread samples to an accumulator 526. The accumulator 526 can be configured to decover the despread samples with one or more codes Walsh summing the accumulation of compressed or decovered samples over some specified period of time (e.g., between the reference pilot signal) and output the recovered data (e.g., data, pilot or power control) to the controller 240. An accumulator 526 also may be configured providing transmission of processed symbols used for the search with a high level of copies of the received signal at various time offsets, as described below.
In one embodiment, the controller 240 processes the pilot symbols received from the accumulator 526 and generates the recovered pilot that is used for coherent demodulation of the data symbols. In other embodiments, the processing unit of the pilot signal can be realized in the data processing unit 230 to filter the pilot symbols and generate the reconstructed pilot signal. To process the pilot reference can be provided and other developments that are within the scope of the present invention.
In the particular embodiment shown in Figure 5, data bus 510 interconnects various elements of receiver unit 200, such as address generator 220, data processor 230, microcontroller 232, and controller 240. Data bus 510 supports efficient transfer of data and other information between the elements connected to the data bus. For example, the controller 240 may use a data bus 510 for tasking the microcontroller 232 and to send processed pilot symbols to data processor 230. May be provided other interconnection mechanisms receiver elements 200, which are also within the scope of the invention.
6A is a diagram illustrating recording of data samples in the buffer 224 and reading data samples from the buffer. In a typical digital communications system, data is divided into packets and these are processed in packets that are then transmitted in frames having a certain specific length of time. For example, in the HDR CDMA system, data is transmitted in packets, each of which is transmitted over one or more slots. Each slot represents a certain fraction of a frame and (in the HDR system) includes 2048 chips, each of which has a period TC, which is connected with the total bandwidth of the system (e.g., ratio Tc = 1 / (bandwidth)).
In one embodiment, the received samples are written to buffer 224 starting at designated addresses, which can be selected arbitrarily (for example, this address may be zero, as shown in Figure 6A). In one embodiment, initialization instructions intended address pointer write address data is reset when the event occurs (this event can be, for example, increase in power) and samples are written to buffer 224 starting at location as specified by said pointer. Thus, between the write address pointer and the actual boundary of a frame transmitted over the radio interface and representing a sample has an arbitrary shift, also called the phase shift. Border frame may correspond to any address in the buffer 224. In the process of receiving this shift is calculated by the controller 240. Subsequent data extraction offset this shift calculation - it is added to the read address pointer.
The address generator generates an address of the data recording data recording, DW_ADDR, which indicates the next available slot in the buffer 224. In one embodiment, samples are written into consecutive locations of the buffer 224, and write address data, DW_ADDR, is incremented after each write operation. In one embodiment, buffer 224 is implemented as a circular buffer with a cyclic return from end to beginning. By choosing the size of the buffer 224 equal to a power of two, you can use the binary counter for the issuance of the required write address (or reading). This counter is, of course, makes a wraparound from the end to the beginning, and is reset to zero when the count reached at the end of the buffer 224.
After saving enough samples in the buffer 224 can extract and process the particular segment of samples from the buffer. Such a segment can include data samples for an entire packet or a portion of the packet. In one particular embodiment, each segment of data samples corresponds to a separate pilot reference signal, and the segment size is limited to the length of time during which the channel is coherent over the pilot reference. In one embodiment, as part of the pilot processing within the controller 240 vector pilot signal corresponding to the reference pilot signal undergoes a phase shift corresponding to the estimate frequency error, for generating pilot estimates that are then provided to data processor 230 for demodulating the pilot signal. Thus, the controller 240 samples the pilot reference at the beginning of the segment and uses a control reference signal to generate pilot estimates for the duration of the segment. The phase error in the pilot estimates accumulates along the length of the segment, and thus the segment length is limited to reduce the accumulated phase error in the pilot estimates. In the presence of such a construction is not necessary to have a special complex multiplier chip rate for cyclic shifting the samples themselves, which would increase the complexity of the data processing unit.
Segments of data samples corresponding to different copies of the signal (or multipaths) can be sequentially processed. For example, samples corresponding to the first signal multipath having a time offset of zero may be retrieved from buffer 224 and processed by data processor 230. Upon completion of the processing of the first multipath signal can be extracted from the buffer 224 and process another segment of samples (e.g., corresponding to the second signal multipath effects). For every processed segment in the address generator, read data is loaded initial address that takes into account (1) the arbitrary offset between the alignment samples at zero shift and address pointer entry (2) the address of the segment relative to the package, and (3) the time offset associated with the processed specific multipath signal.
6B is a diagram illustrating recording of PN samples to a buffer 224 and reading of PN samples from the buffer. In one particular embodiment, the complex PN samples used for compression of the received samples are computed pseudo-random sequences generator and stored in the buffer 224. Again, the pseudo-random samples can be stored in the destination address. You can then retrieve some segment of PN samples from buffer 224 and used to compress the corresponding segment of data samples.
Write address generator PN samples used for generating write addresses pseudorandom sampling, PW_ADDR, required for reading a segment of PN samples. For every processed segment data that requires PN samples, in the read address generator is loaded pseudorandom sample address of the first pseudo-random sample in the segment. Each of the address generators writing and reading of PN samples, respectively, is incremented after each read or write operation of pseudo-random samples.
The number of PN samples stored in the buffer 224 may be set based on a number of factors and may be equal to the number of stored data samples. For example, you can save two slots of PN samples for two slots of data samples. The number of PN samples stored may also depend, for example, the size of the buffer 224 is supported by the compensation value of the phase shift and multipath signals etc.
6C is a block diagram of a specific embodiment of the data buffering for the receiver design shown in Figures 2 and 5. IADC and QADC sample from the analog-digital converters are sent to an input data interface 222, which removes redundant samples, packs the samples into words and outputs these words to a multiplexer 612. The generator 614 receives the pseudo-random sequence of pseudorandom (PN) mask from data bus 510, generates a portion of each of the in-phase pseudorandom (IPN) and quadrature pseudorandom (QPN) sequences used for compressing the data samples and outputs the generated pseudo-phase and quadrature pseudorandom sample (in the form of words) to the multiplexer 612. The multiplexer 612 outputs each extracted word consisting either of data samples, or samples of the pseudo-random, in a cell buffer 224, indicates the address of record, issued by the generator 220 addresses.
6C also shows a block diagram of a specific embodiment of address generator 220 used to generate addresses for buffer 224. Address generator 220 includes a write address generator 512a the data read address generator 512b data write address generator 512s PN samples and generator 512d PN samples read address connected to latches 514a, 514b, 514c and 514d respectively. Generators 512a-512d are also connected to the address multiplexer 622, which selects the generated address from one of address generators 512 and provides the selected address to buffer 224.
Each latch 514 stores a value indicating the first address generated by the generator 512 addresses for the processed segment. For example, to read a particular segment of data buffer 224 address of the first data sample in the segment is given to latch 514b at the appropriate time. Read address generator 512b loads the data value stored in latch 514b, and uses this value as the starting address. Subsequent data read addresses can be generated, for example, by making the increments of the counters shown in the read address generator 512b data.
As described above, the data samples can be stored in the buffer 224 starting at an arbitrarily assigned a cell buffer (e.g., zero). Furthermore, a buffer 224 configured to store a specific number of samples. In one embodiment, buffer 224 has a size equal to a power of two. Because of this, you can use the binary counter for generating write addresses (or read) buffer 224. This binary counter usually carries out a cyclical return to zero when it reaches the end of the buffer.
In one embodiment, since data samples are written to buffer 224 in sequential order, the address generator 512b as the read data can be used as the sample counter that counts the number of samples stored in buffer 224. The data write address from address generator 512a is given to the comparator 628 and compared with the comparison value issued by the controller 240. This value comparison indicates that a specific number of stored samples (e.g., one packet), which would have to notify the controller 240. If the data write address equals the comparison value, the comparator 628 outputs the timing signal reflecting this condition. This timing signal is used by controller 240 to initiate the processing of the stored samples.
6C also shows a specific embodiment of the time processing for each selected multipath. In one particular embodiment, the controller 240 maintains synchronization FSM 630 for each processed multipath signal (e.g., received with a rake receiver retraction). Although 6C is shown schematically as a block, each synchronization FSM 630 is typically implemented and maintained by a "hardwired programs" digital signal processing. Data processor 230 may be configured to perform some of the signal processing in order to find among data samples of the instances of the received signal, which has the highest level (e.g., by correlating a segment of PN samples with a number of segments of data samples at various time offsets). Each peak corresponds to a correlation with a high level (ie, pronounced) copies of the signal. If the correlation peak exceeds a particular threshold, the controller 240 sets a new synchronizing finite state machine 630 for the multipath signal corresponding to the peak correlation. Next, the timing offset of the selected multipath signals, and is used for generating addresses for reading samples from buffer 224.
In one embodiment, each synchronized state machine 630 includes a circuit 634 for tracking time, which tracks the movement of the multipath. Time tracking can be achieved by processing samples (e.g., in accordance with a reference pilot) at shifts to +1/2 and -1/2 chip, determining a difference between the accumulated value of the pilot signal during shifts by +1/2 and -1/2 chip, and filtering the difference value to generate a correction factor. Thus, the motion signal of multipath propagation with time tracking loop 634 determines the amount of travel time, and accordingly updates the time offset with the correction factor into account. The time shift is given in block 636 of addresses and data calculating PN samples and used to calculate the starting address of each of the processed data segment. The calculated start address is then provided to latch 514b data bus 510 at the appropriate time.
As noted above, the samples stored in the buffer 224 starting at a designated location in the memory, at an arbitrary time. As a result, the initial samples for each signal instance to be treated may correspond to a cell in the buffer 224. In one embodiment, circuit 634 keeping time is used to determine the starting location of the received data packet for each signal instance being processed. Circuit 634 handles time tracking received samples to determine a particular time offset for the received signal copies. This time shift is then used to generate the starting address for each segment of the processed samples.
Finite state machines 630 may be implemented by the controller 240, which uses a "wired" digital signal processing software and has a basic set of processing elements. For example, a single circuit 634, and time tracking block 636 only data calculating addresses and PN samples can be time-division multiplexed and used to implement all the illustrated state machines 630. Controller 240 can maintain a separate register to store the time offset associated with each end illustrated 630 machine.
In one embodiment, for the forward link processing in a remote terminal, controller 240 also supports the circuit 638 frequency tracking, which specifies the source frequency synchronization signal repetition frequency equal to (transmission speed) of data applied to the data samples. Frequency tracking loop may be configured to determine the cyclic shift of the phase reference pilot signals using phase information to determine the frequency of the clock pulse frequency is above or below the chip, and appropriate adjustment of the frequency source clock. If the frequency of the clock frequency is fixed to the chip, then for each frame is given a specific number of samples (eg, 2048). Thus, when the frequency is fixed, it is possible to interpret the reception of a frame of samples by counting the number of samples stored in the buffer 224.
6C also shows a block diagram of a specific embodiment of address generator 236 used to generate addresses for buffering unit 234 and deinterleaving. Address generator 236 includes a write address generator 542a and symbol read address generator 542b of symbols, connected to latches 544a and 544b respectively. Generators 542a and 542b are also connected to the address multiplexer 546, which selects Shaped address of the generators 542a and 542b of addresses and outputs the selected address in the 234 block buffering and deinterleaving.
Each latch 544 stores a value indicating the first address generated by the generator 542 addresses for the processed segment. The initial values provided to latches 514 are generally related to the values reported in latches 544, but they are issued with a variety of factors, such as the delay processing unit 230 processing data. Read address generator 542a loads the character value stored in latch 544a and uses the loaded value is in the start address. Subsequent symbol read addresses can be generated, for example, by making the increments of the counters shown in the read address generator 542a symbols.
In one embodiment, block 234, and the deinterleaving buffer is used to store intermediate and final results of the summation symbol accumulation for multiple multipaths. First the processing of the samples for a particular multipath propagation and received symbols are stored in specific cells buffering unit 234 and deinterleaving. To simplify the addressing, the symbols for a particular multipath propagation (e.g., from the first processed) may be stored in block 234, and the deinterleaving buffer, since a dedicated cell (e.g., having a zero address NS, etc.). For each subsequent multipath, the demodulated symbols for that multipath can be combined with the corresponding stored symbols for prior processed multipaths. These combined symbols are then stored back into the same cells in the block 234, and the deinterleaving buffer. Thus, symbols for multiple processed multipaths are combined "in situ" from the corresponding previously accumulated symbols. When it is necessary to combine the symbols for multiple multipath signals, the address generator 236 generates the appropriate address reading and writing characters, determined by the values stored in latches 544a and 544b.
In many communications systems including the HDR CDMA system, interleaving is used to provide time diversity in the transmitted data. The interleaving reduces the likelihood of receiving the chain of consecutive errors caused by, for example, impulse noise. At the receiver the received symbol reordering occurs. This reordering can provide effective chain extension symbols received with errors, the entire frame, which could increase the probability of correctly decoding the received symbols. The interleaving performed at the transmitter unit, so that time diversity is achieved before the decoding at the receiver.
In one embodiment, the buffering unit 234, and the deinterleaving is also used to provide processed symbol deinterleaving. In one embodiment, the processing of characters written to the buffer unit 234 and the interleaving in a sequential order and read out in a pseudo-random, but deterministic manner determined by the specific interleaving algorithm implemented. Since the code read is not in sequential order, buffering unit 234 and the deinterleaving first filled with the symbols corresponding to the duration of the interleaver. For example, in the HDR CDMA system, interleaving is performed for each frame. Thus, in the receiving apparatus entire frame of symbols is processed and stored in buffer unit 234, and the deinterleaving. After processing the whole frame symbols for the frame are read in the subsequent decoder. In one particular embodiment, the current frame is processed and stored in one section of the buffer unit 234 and deinterleaving a previously processed frame can be retrieved from another section of the buffer unit 234 and deinterleaving.
Read address generator 542b of symbols includes the circuitry necessary to generate proper addresses symbols output unit 524 demodulation and symbol combining to effect accumulation of characters, then the characters are given to the subsequent decoder 260 for decoding. Read address for said two characters "destinations" can be generated by time division multiplexing. For example, symbols can be provided to unit 524 and a demodulation symbol combiner and decoder 260 during alternate read cycles. In an alternative embodiment, can be provided to a group of characters in the block 524 and the demodulation symbol combiner, and then issue a group of symbols to decoder 260.
7A is a block diagram of a specific embodiment of correlator 522 at block 230 data. In one embodiment, the correlator 522 is configured to support a number of functions including, for example, compression of the data samples by the complex PN despreading sequence, accumulation of multiple despread samples for each chip repetition period, and interpolation. To achieve improved performance correlator 522 can be configured to handle multiple complex samples at a time (e.g., their number up to four). For correlator 522 may be implemented by other structures and functions that are within the scope of the invention.
In one embodiment, for each cycle of data readout from the buffer 224 are extracted four pairs of digitized phase and quadrature samples of QADC IADC and analog-digital converters (i.e., four complex data samples) are fixed latches 712a-712d . In the next cycle, the read sample data from latches 712a-712d are also captured latches 714a-714d, respectively, and the next four pairs of digitized in-phase and quadrature samples IADC and QADC of analog-digital converters are fixed latches 712a-712d. In one particular embodiment, two data samples are issued during each repetition period of the chip (i.e., obtained during the double sampling), and the double locking latches 712 and 714 provides processing or timely (OT) sample or retarded (LT) sample of each chip.
Multiplexers 716a-716d also receive a fixed sample from latches 712a-712d, respectively, and recorded samples from latches 714a-714d, respectively. Each multiplexer 716 provides one of the received samples, depending on whether the sample - prompt or late - to be treated, the corresponding elements of the logical "AND", indicated by reference numeral 718. Logic elements "U" indicated at 718a and 718b, and receive the control signal ZERO_0, and logic elements "AND" designated positions 718s and 718d, also receive the control signal ZERO_1. Each of the AND gates 718 "AND" provides either the received sample or a value of zero ("0") corresponding to the multiplication unit 720, depending on the control signal ZERO_h.
In one particular embodiment, the buffer 224 and is also used to store in-phase and quadrature pseudo pseudorandom sequences used for compressing the data samples. In one particular embodiment, during each read cycle of PN samples having a length of 16 chips segment complex PN despreading sequence, corresponding to the data samples being processed, is retrieved from buffer 224 and holds latch 732 and outputted to the multiplexer 734. Multiplexer 734 selects a portion (e.g. a portion comprising 2 chips) fixed segment complex PN sequence and provides the selected portion to a cyclic shift register 736. Then, the register 736 outputs the appropriate pseudo-phase and quadrature pseudo-random sampling in each of the blocks 718a-718d multiplication.
In one particular embodiment, the data samples are subjected to oversampling analog-to-digital converters may - decimation and issued twice as likely to chip (ie, the frequency of the sampling frequency is twice the chip). Oversampling provides detection with a high level of copies of the received signal at a lower temporal resolution, allowing you to achieve improved performance. In case the correlator architecture shown in Figure 7A, provides four parallel processing channels, and can simultaneously process up to four complex data samples corresponding to the data consisting of two elementary samples during each cycle of the synchronization signal processing. As shown in Figure 7A, the blocks 720a and 720b perform compression multiplication of two complex data samples (i.e., the timely and late samples) corresponding to chip index n, and the blocks 720c and 720d of multiplication of two complex compresses the data samples corresponding to index n + 1 chip. A cyclic shift register 736 outputs the in-phase and quadrature pseudo pseudorandom samples corresponding to chip index n, in blocks 720a and 720b multiply and, and quadrature phase pseudorandom pseudorandom samples corresponding to the index n + 1 chip, - at blocks 720c and 720d of multiplication.
Each block 720 performs a complex multiplication of the complex sample data compression using complex PN samples. The transmitting device in the HDR CDMA system, data is transmitted complex spread with the complex PN sequence. Comprehensive expansion can be expressed as follows:
ITX + j · QTX = (IDAT + j · QDAT) · (IPN + j · QPN). (1)
At the receiver, the data can be restored through complementary integrated compression, which can be expressed as follows:
IDES + j · QDES = (IADC + j · QADC) · (IPN - j · QPN), (2)
where IADC = ITX + noise, QADC = QTX + noise, IDES = IDAT + noise and QDES = QDAT + noise.
7B is a block diagram of a specific embodiment of multiplier 720 that implements the complex compression is expressed by equation (2). In block 720, a complex multiplication sampling data, IADC and QADC, is issued to each of multiplexers 762a and 762b, and the complex PN sample, IPN and QPN, is issued to the AND gate 764 "exclusive OR". The AND gate 764 "exclusive OR" operation performs "exclusive OR" (i.e., multiplication) phase pseudorandom (IPN) and quadrature pseudorandom (QPN) samples and provides an output signal to the selected input of each of multiplexers 762a and 762b. Each multiplexer 762 selects either in-phase or quadrature sampling of the analog-to-digital converters, IADC or QADC, depending on the value of the selected input, and outputs the selected sample at the input of the respective NAND gate 766 "exclusive OR". Logic elements 766a and 766b «EXCLUSIVE OR" function as "exclusive OR" (ie multiplication) of samples obtained from the IPN and QPN, respectively, and provide output samples into logical elements of the "I", respectively, reference numerals 768a and 768b. Each AND gate 768 "AND" also receives a control signal ZERO_x and provides either the received sample or the value "0", based on a control signal ZERO_x. The outputs of gates 768a and 768b «I» is compressed and QDES IDES sample.
Returning to Figure 7A, note that the short-phase and quadrature sampling, IDES and QDES, of the blocks 720a-720d multiply selectively combine adders 722a-722d to form a combined set of samples, IC and QC. Specifically, the adder 722a combines the despread IDES samples from blocks 720a and 720c multiplication to generate a first combined-phase sample IC1, corresponding to the first half of a chip, summer 722b combines the despread in-phase sample IDES of blocks 720b and 720c of multiplication to generate a second combined-phase sample IC2, corresponding to the second half of the chip, an adder 722C combines compressed quadrature sampling QDES of the blocks 720a and 720c multiplication to generate a first combined quadrature sampling QS1 and adder 722d combines compressed quadrature sampling QDES of blocks 720b and 720d multiplication to generate a second combined quadrature QS2 sample. Combiners 722 can be used to combine the half of samples from different chip before interpolation to simplify the design of the interpolator. Logic elements 718 "I" and signals ZERO_0 and ZERO_1 can be used to inhibit association of samples from two chips when this is not applicable, for example, demodulation symbols downlink, where each chip may contain a complex or subjected to a higher order modulation symbol.
In the particular embodiment shown in Figure 7A, correlator 522 includes an interpolator 730 that can be configured to produce a symbol value by different time shifts. For example, if each chip are given two complex data samples (i.e., the time shift is 0 and 0.5 TC TC where TC - the period of a chip), the interpolator may be used to generate interpolated samples at other time offsets, e.g. , TC is 0.125, 0.25 CU, 0,375 CU, 0,625 CU, 0.75 CU 0,875 CU, etc. Time resolution of the interpolation is dependent on the particular design of interpolator 730. The interpolator 730 can be used, for example, to identify a multipath signal with a temporal resolution of less than the repetition period of the sample (e.g., less than 0.5 Tc).
7C is a diagram that illustrates linear interpolation. As shown in Figure 7C, the sample index (n) is the amplitude of the sample A, a sample with the following index (n + 1) sample has an amplitude of B. The repetition period of normalized samples (given) to the value of 1.0. The samples with indices (n) and (n + 1) samples can be used to estimate the values that are acceptable for samples at other time offsets, e.g., such as 0.25, 0.50, 0.75, etc. For the linear interpolation of the amplitude of the sample at the time shift can be estimated as 0.25 0.75A + 0,25V, the amplitude of the sample at the time shift can be estimated as 0.50 0,50A + 0,50V and the amplitude of the sample at a time offset of 0.75 You can estimate the size of 0,25A + 0,75V. Through scaling of samples by a factor of four, the amplitudes of the samples at time offsets of 0.0, 0.25, 0.50, 0.75 and 1.0 values can be expressed 4A, 3A + B, 2A + 2B, A + 3B, and 4B, respectively, .
7D is a block diagram of a specific embodiment of interpolator 730. In this embodiment, interpolator 730 is implemented as a linear interpolator configured to output interpolated samples at three different time offsets (e.g., 0.25, 0.50 and 0 75). Interpolator 730 is also configured to (1) issuing the output signal with the value zero, (2) feeding the received samples, (3) providing of interpolated samples, or a certain set of realization just above operations (1) - (3).
The combined phase and quadrature symbols IC1, IC2, QS1 and QS2 of the adders 722a-722d are issued in scaling elements 770a-770d, respectively. Each Scales the sample 770 is input to X1 of the multiplexer 772, doubling the input element 774 and the input of the adder 776. doubles element 774 scales the received samples by a factor of two, and outputs the scaled output of the input multiplexer X2 772 and the other input of the adder 776. The adder 776 sums the sample submitted to its input, and the scaled sample is input to the multiplexer X2, and provides the summed output to the input of the multiplexer 772. The multiplexer X3 772 also receives a zero ("0") at its input X0. Then, the multiplexer 772 selects the sample at one of its inputs based on a control signal OFFSET (offset), and outputs the selected sample in latch 780.
As shown in Figure 7D, scaling elements 770a and 770b can be configured to their complementary nature, and scale elements 770s and 770d can also be configured to their complementary nature. For a particular time offset of 0.25, 0.50 or 0.75 (a specific value expressed by the control signal OFFSET), the scaling of the element 770a in the latch 780a respectively 3IS1 given value, or 2IS1 1IS1 and from scaling element 770b to latch 780b, respectively, issued the value IC2, 2IS2 or 3IS2. The samples from latches 780a and 780b then issued to the adder 782a, and samples from latches 780s and 780d then issued to the adder 782b. The output from the adder 782a comprises an interpolated in-phase samples and the output from the adder 782b comprises the interpolated quadrature samples. The interpolated samples from summers 782a and 782b is output as the correlated I and Q samples, ICOR and QCOR, from correlator 522. The outputs from latches 780a-780d also include (not interpolated) phase and quadrature correlated samples - ICOR1, ICOR2, QCOR1 and QCOR2 respectively.
The interpolator 730 can be used in a variety of different configurations. For example, as noted above, interpolator 730 can be configured to issue zero output signals, feeding the received samples, samples or interpolated issuing some set of realization just listed. A value of zero at the input X0 multiplexers 772 is selected to give zero output signal, and a sample at input X1 selected for supplying selected samples. In the case of the interpolation value at input X1, X2 or X3 is selected one multiplexer 772, and the added value of the inputs X3, X1, X2, or select another multiplexer 772 in a pair of complementary multiplexers.
As noted above, in one embodiment, issuance is performed two data samples in each repetition period of the chip and processing (e.g., compression) of these samples with the correlator 522. The two samples for each chip can be combined into the interpolator 730 for dispensing a compressed audio sample for the repetition period of each chip. To combine the in-phase sample for each chip, the sample is selected on the inputs X1 multiplexers for scaling elements 770a and 770b, and summarize them by the adder 782a to issue the combined in-phase sampling. Similarly, to combine the Q samples for each chip, the sample is selected on the inputs X1 multiplexers for scaling elements 770s and 770d and summed them via adder 782b for dispensing the combined quadrature sampling.
In the HDR CDMA system, the transmitted traffic data are divided into a number of data streams, and each data stream is masked by using a particular Walsh code. In accordance with the terms of the HDR CDMA system, each Walsh code corresponds to a respective Walsh symbol having a length ranging up to 16 chips. To separate data channels, each data mask bit Walsh symbol having a length of 16 chips and assigned a channel that carries said bits. For each repetition period of Walsh symbols are generated and combined up to 16 Walsh symbols for transmission of up to 16 bits of data channels, the number of which reaches 16. The 16 Walsh symbols are orthogonal to each other and in the absence of distortions can be recovered separately in the receiver, because the cross correlation between orthogonal sequences (ideally) zero.
8A is a block diagram of a specific embodiment axes uschestvleniya unit 524 demodulation and symbol combining at block 230 data. Pairs of correlated samples from correlator 522 are issued unmasks element 820 that decovers the sample by separating the channels of symbols (e.g., Walsh symbol) to obtain decovered symbols. The decovered data symbols and the complex pilot symbols 850 are provided to a demodulation pilot signal, performing a coherent demodulation of the pilot signal data to obtain demodulated symbols. Thereafter, the demodulated symbols are given a symbol accumulator 870 and may be combined with other demodulated symbols from other signal channels or other - redundant - transmissions. The output from symbol accumulator 870 comprises the processed symbols that are then issued at block 234, and the deinterleaving buffer (see. Figure 5).
Demodulation unit 524 and the symbol combining may be designed to handle a certain number (e.g., four, eight, sixteen, etc.) samples per clock cycle. The number of samples that can be handled simultaneously unit 524 demodulation and symbol combining is typically dependent on a number of factors, such as the frequency with which the sample can flow into the unit 524 demodulation and symbol combining, the width of the elements in the unit 524 demodulation and symbol combining etc.
8B is a block diagram of a specific embodiment of a fast Hadamard transform (FHT), which can be used to implement unmasking element 820. In one embodiment, phase and quadrature correlated ICOR and QCOR samples sequentially and alternately issued in item 820 FHT, one sample per clock cycle. In one embodiment, the element 820, FHT is adapted to Walsh decover exercised over the received signal by using one or more Walsh symbols of length N, where N - number of programmable.
Element FHT 820 may be designed to operate in one of a plurality of configurations. For example, element 820, FHT can be configured to decover the input symbols using a particular Walsh symbol having a certain specific length N. In this configuration, element 820 receives the FHT block of N samples of the in-phase correlated ICOR and N quadrature correlated samples QCOR (e.g., block, display vector pair ICOR and QCOR, having a length of N chips), and conducts an operation demasking Walsh over N chips on the received block of samples with a particular Walsh symbol to generate a pair of I and Q decovered symbols IDEC and QDEC.
In an alternative embodiment the element 820, FHT can be configured to decover the received samples using all N Walsh codes. With this configuration, the element 820 FHT performs a function equivalent to multiplication of a Hadamard matrix having a size of NxN (which corresponds to the presence of N Walsh symbols, each of length of N chips) by a vector comprising the N pairs of correlated in-phase and quadrature samples ICOR and QCOR, to form decovered phase and quadrature symbols IDEC and QDEC. Decovering using all N Walsh symbol is especially advantageous, for example, in the HDR CDMA system, wherein data can be transmitted at a certain specific terminal by more than one channel.
In one embodiment for performing the processing phase and quadrature correlated ICOR and QCOR samples and to minimize the number of required circuit element 820, FHT be configured to process phase and quadrature correlated ICOR and QCOR samples in alternating clock cycles. This allows one single element of the FHT 820 issuing phase and quadrature decovered IDEC and QDEC symbols in the unit for further processing in alternating clock cycles and delayed inphase symbols decovered IDEC one clock cycle with respect to respective quadrature decovered QDEC symbols. Then block for subsequent processing can be configured to process the decovered phase and quadrature symbols IDEC and QDEC as they issue from the element 820, FHT without having to wait for completion of processing, first of all the correlated in-phase symbols ICOR block for processing correlated quadrature symbols QCOR. Element 820 FHT can also be configured to work with the possibility of alternating-phase and quadrature correlated samples ICOR and QCOR through proper management of storage elements in your element 820 FHT.
Element FHT 820 is a mechanism for sequential processing, which receives the samples sequentially, one sample per clock cycle, and after a particular processing delay provides unmasked symbol for each clock cycle. The decovered symbols for a particular block of samples are delayed by a particular number of clock cycles, and the delay is determined, inter alia, the length of a Walsh symbol. For each block of N data samples element FHT 820 sequentially provides N decovered symbols corresponding to the N Walsh symbols. Decovered symbols of element 820 FHT represent the correlation between the input samples and Walsh symbols.
FHT element can perform decovering for Walsh symbols of length N = 2L using L bufferfly transform elements. In the particular embodiment shown in Figure 8B, to decover Walsh symbols of length 16 chips element FHT 820 includes four serially connected elements 830a-830d buffer conversion. Each element of the conversion buffer 830 performs a subset of the necessary addition and subtraction. Every subsequent conversion of the buffer element 830 also performs cross-linking of the results of the prior conversion buffer.
Each bufferfly transform element 830 input sample is supplied to the input of the multiplexer 832, the subtracting input of adder 834 and a first summing input of summer 836. Multiplexer 832 also receives the output from the adder 834 and alternately provides the output from the adder 834a or the input sample to a memory element 838. The output of storage element 838 is supplied to a summing input of summer 834, a second summing input of the adder 836 and to one input of multiplexer 840 which also receives the output from adder 836. Multiplexer 840 alternately provides the output from memory element 838 and the output signal from the adder 836 to latch 842. The output latch is issued to the input of the next bufferfly transform element 830. The output of the last bufferfly transform element 830d is decovered symbols.
Design and operation of fast Hadamard transform element are described in detail in U.S. Patent number 5561618, entitled "METHODS AND APPARATUS FOR PERFORMING A FAST HADAMARD TRANSFORM" («methods and apparatus for performing fast Hadamard transform"), issued October 1, 1996, assigned to the assignee to the present invention.
In the embodiment shown in Figure 8B, the element 820, FHT can be programmed to perform a fast Hadamard transform (i.e. decovering) with variable length (e.g., 1, 2, 4, 8 or 16). The maximum FHT length supported by the element 820, FHT, determined by the number of elements used transform buffer 830, and a shorter length FHT can be implemented by bypassing one or more bufferfly transform elements 830. It is also possible to carry out fast Hadamard transform and a greater length, applying additional bufferfly transform elements 830.
In the embodiment shown in Figure 8B, the correlated and quadrature-phase sample ICOR and QCOR issued in item 820, FHT on the same bus in alternating clock cycles. Using Walsh counter (not shown in Figure 8B), which is reset when the first correlated sample arrives at the input element 820, FHT is obtained with time division multiplexing. This time division multiplexing provides sharing of hardware, so that the element 820, FHT can perform decovering of both samples, i.e. correlated in-phase and quadrature correlated - ICOR and QCOR. In yet another embodiment, the correlated phase and quadrature sampling ICOR and QCOR received in parallel on two elements of the FHT, each of them be configured to block the implementation of the appropriate unmasking correlated in-phase and quadrature correlated samples ICOR and QCOR.
8C is a block diagram of a specific embodiment of the demodulation unit 850 pilot signal. Phase and quadrature decovered IDEC and QDEC symbols from the element 820 and FHT code phase and quadrature components of the complex pilot signal, PI and PQ, 850 are provided to a demodulation pilot signal, which coherently demodulates the decovered pilot symbols. Demodulation of the pilot signal can be expressed as follows:
IDEM + j · QDEM = (IDEC + j · QDEC) · (PI + j · PQ) =
= (IDEC · PI + QDEC · PQ) + j · (-IDEC · PQ + QDEC · PI) =
= [Scalar product (IQ, P) -
- J · cross product (IQ, P)] (3)
The demodulated phase and quadrature symbols IDEM QDEM and can be expressed as follows:
IDEM = (IDEC · PI + QDEC · PQ) (4)
QDEM = (-IDEC · PQ + QDEC · PI) (5)
In block 850 the demodulation and quadrature-phase decovered IDEC and QDEC symbols are issued (for example, in alternating clock cycles) to latches 852a and 852s, respectively. The output from latch 852a is then secured to the latch 852b to time-align the IDEC and QDEC symbols. The outputs from latches 852b and 852s are complex data symbols. Similarly, the code-phase and quadrature components of the pilot signal, PI and PQ, are fixed respectively latches 854a and 854b. The outputs from latches 854a and 854b received in each of multiplexers 856a and 856b. Each multiplexer 856 selects either the symbol of the real component PI pilot symbol PQ or quadrature component of the pilot signal depending on whether the product - scalar or vector - is calculated. Complex pilot symbols from multiplexers 856a and 856b, respectively, are given in blocks 860a and 860b, which also receive the complex data symbols, respectively, from latches 852b and 852s. Each block 860 performs the multiplication by multiplying one component (i.e., IDEC and QDEC) complex data symbol on one component (i.e., PI or PQ) complex pilot symbol, and outputs the resulting product to the corresponding latch 862.
The output from latch 862a is supplied to the AND gate 864 "exclusive OR", also receives a control signal CROSS. The output of latch 862b and the output of NAND gate 864 "XOR" adder 866 receives that sums the symbols and provides the sum output signal to an accumulator 870 characters.
From equation (4) shows that the demodulated symbol IDEM can be generated by multiplying the symbol IDEC data symbol PI in-phase component of the pilot signal at block 860a multiplication, multiplication symbol QDEC data symbol PQ quadrature component of the pilot signal at block 860b multiplication and summation of the results obtained from blocks 860a and 860b multiplication to adder 866. Similarly, from equation (5) that the demodulated symbol QDEM can be generated by multiplying the IDEC data symbol per symbol PQ quadrature component of the pilot signal at block 860a multiplication, multiplication QDEC data symbol symbol PI in-phase component of the pilot signal at block 860b multiplication, inversion of the result obtained from the block 860a multiplication and summing the result obtained from unit 860b multiplication c inverted result obtained from the NAND gate 864 "exclusive OR" in the adder 866. Thus, to generate demodulated symbols QDEM multiplexers 856a and 856b pumped PI and PQ symbols constituting the pilot issued in blocks 860a and 860b multiply and AND gate 864 "exclusive OR" inverts the result obtained from the multiplication unit 860a.
8C also shows a block diagram of a specific embodiment of accumulator 870 characters. The demodulated IDEM and QDEM symbols from unit 850 demodulation pilot signal are issued sequentially to an adder 872. The IPRE and Symbols QPRE, resulting from previous computations are retrieved (e.g., pairs) of the buffering block 234, and interleaving and outputted to the latch 874. The multiplexer 876 connected to the latch 874, selects either character IPRE, a symbol QPRE, for extradition in logic element 878 "AND". The AND gate 878 "AND" also receives a control signal FIRST, which zeros the output of NAND gate 878 "and" should not be performed if the accumulation of symbols. The output of NAND gate 878 "I" is given to the adder 872 and summed with the received IDEM or symbol QDEM. The output signal from the adder 872 is accumulated (ie processed) symbol IPRO or QPRO, which is given back to the buffer unit 234 and interleaving.
9 is a block diagram of a specific embodiment of the present in the data processing unit 230 of the accumulator 526 which can be used for processing traffic data, pilot reference, and other signaling data. The user terminal accumulator 526 can be used to search for instances of the received signal having a high level to recover the pilot reference, to extract the power control bit, etc. At base station accumulator 526 can be used to perform the above functions and can also be used for processing other signaling information, for example, such as a data request message data rate control (DRC (DRC)).
In the particular embodiment shown in Figure 9, phase and quadrature correlated ICOR and QCOR samples from correlator 522 are given to a group of eight unmasking accumulation and summing elements 910a-910h. Within the scope of the invention may be used, and a different number of unmasking and added to the accumulation of elements 910. Each unmasks and adds to the accumulation element 910 correlated phase and quadrature sampling ICOR and QCOR issued in logic element 912 "exclusive OR", which also receives a symbol Walsh from Walsh generator 914. Walsh generator 914 can be programmed to the formation of a particular Walsh symbol, downloading the appropriate Walsh code generator associated with this latch 916. Thus, eight unmasking and added to the accumulation of elements 910a-910h can be programmed to perform specific unmasking in a block of samples, and ICOR QCOR with eight different Walsh symbols.
On the forward link may use one unmasks element for processing of power control data. On the reverse link can use eight unmasking elements for demodulating data rate control (DRC (DRC)) and of the FHT as a direct Fourier transform (DFT (PPD)), i.e. transformation is not rapid.
Each unmasks and adds to the accumulation element 910 of logic element 912 "exclusive OR" unmasking carries data samples using a Walsh symbol, and outputs decovered samples to one input of the multiplexer 922. The other input of the multiplexer 922 receives the corresponding correlated samples (ie ICOR1, ICOR2, QCOR1 or QCOR2) of the correlator 522. Depending on the particular problem being solved multiplexer 922 provides either the decovered samples from NOR gate 912 "exclusive OR" or correlated samples to the adder 924. The adder 924 also receives a previously fixed sample of a NAND gate 926 ' And "sums received samples and provides the accumulated output to a first set of registers 928a and 928b (coupled in series) and a second group of registers 930a and 930b (also coupled in series). A latched output signal of the latch 928b and a control signal FLUSH applied to inputs of NAND gate 926 "I", which outputs zero value to the adder 924 if the control signal FLUSH is low, and outputs the latched output signal from the latch 930b when the master FLUSH signal is high. A latched output signal from the latch 930b is accumulated symbol is given to one input of multiplexer 940.
Multiplexer 940 receives the accumulated symbols from all eight unmasking accumulation and summing elements 910a-910h and provides the received symbols in the latch 942, which is also connected to the data bus 510. Thereafter, the accumulated code retrieved from latch 942 by the controller 240.
As shown in Figure 9, correlated phase and quadrature sampling ICOR and QCOR also enter the 952 block squaring and summing to unmask the accumulation element 910b. Block 952 builds squaring the received samples and provides the squared squared samples to a first input of multiplexer 954, which also receives the decovered samples from the NAND gate 912b «EXCLUSIVE OR». Then the multiplexer 954 outputs to the multiplexer 922b or squared samples or the decovered samples, depending on a control signal SQUARE. Block 952 maintains squaring computation ratio estimates of energies of the pilot carrier signal and interference, and this estimate is used to estimate the quality of signal transmission lines.
An accumulator 526 can be programmed to solve a number of problems. For example, accumulator 526 can be programmed to simultaneously decover up to eight different channels. In the embodiment shown in Figure 9, correlated phase and quadrature sampling ICOR and QCOR issued every unmasks and adds to the accumulation of element 910 in the implementation of time division multiplexing (ie, in this order: ICOR, QCOR, ICOR, QCOR and so on). Both latch 928a and 928b in the first group of latches support summation accumulation phase and quadrature samples ICOR and QCOR, time division multiplexed.
An accumulator 526 can also be programmed to assist in the search for copies of the received signal having a high level. For example, accumulator 526 can be configured to sum the accumulation vector I, Q for the various shifts in each of eight accumulators for subsequent squaring. If the reference pilot signal is masked by the Walsh code zero, decovering at the receiver is not required. In the depicted embodiment, accumulator 526 can be programmed for the simultaneous processing of up to four different time offsets, each of which is processed by a respective pair of unmasking the accumulation and summing element 910.
In some embodiments, the microcontroller 232 is provided to solve the problems set controller 240, and to guide the various elements of receiver unit 200 with a view to solving the problems. Each task may be characterized as including a sequence of steps of operation or a number of other tasks. For example, the task may be assigned to process a particular multipath propagation with a certain specific time offset, the search of a signal instance having a highest level in a specific time window, etc. Search the task can be solved by prescribing the correlator 522 and accumulator 526 implementing correlation pilot signal over a particular time interval (e.g., 96-chip length) with precisely predetermined pseudo shear. It may also be tasked to handle all assigned multipaths reflection to find copies of signals having a high level at numerous time offsets, etc. In one embodiment, the microcontroller 232 sets the required task state machine for each received task and maintains the task state machine for its solutions. Depending on the particular task processed micro-controller 232 may also ask one or more additional problem of finite automata for some tasks a lower hierarchical level. The microcontroller 232 can be configured to inform the controller 240 of the completion of solving a particular problem.
The processing carried out in the process of solving problems search processing tasks, signaling processing tasks, and other tasks described in more detail in the following patents and patent applications, all of which are assigned to the assignee as the present application in their entirety:
1) U.S. Patents 5,644,591 and 5,805,648 №№, both having the title "METHOD AND APPARATUS FOR PERFORMING SEARCH ACQUISITION IN A CDMA COMMUNICATION SYSTEM" («A method and apparatus for collecting information when searching in a CDMA communication system");
2) US Patent number 5,867,527, having the name of "METHOD OF SEARCHING FOR A BURSTY SIGNAL" («A method of searching a signal packet");
3) U.S. Patent number 5,764,687, entitled "MOBILE DEMODULATOR ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM" («demodulator architecture mobile station for multiple access communication with spread spectrum signals");
4) U.S. Patent number 5,577,022, entitled "PILOT SIGNAL SEARCHING TECHNIQUE FOR A CELLULAR COMMUNICATIONS SYSTEM" («search method using a pilot signal for a cellular communication system");
5) U.S. Patent number 5,654,979, entitled "CELL SITE DEMODULATION ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEMS" («Architecture demodulation units for cellular communication systems with multiple access spread-spectrum signal");
6) Application № 08/987172 US patent entitled "MULTI CHANNEL DEMODULATOR" («multi-channel demodulator"), filed December 9, 1997 now US patent number 6,639,906, issued on 28 October 2003 .; and
7) Application № 08/283010 US patent entitled "PROGRAMMABLE MATCHED FILTER SEARCHER" («The programmable matched filter searcher"), filed March 31, 1999 now US patent number 6,363,108, issued March 26, 2002.
10 is a block diagram of a specific embodiment of microcontroller 232 that can be used to control the operation of elements (e.g., buffer 224 and data processor 230) of the receiving device 200. The microcontroller 232 includes a controller 1012 for sequencing connected to the counter 1014 and to the latches 1016a and 1016b. Counter 1014 and latch 1016a are also connected to the latch 1016s and 1016d, respectively, which are also connected to the data bus 510.
Latch 1016b stores the state of the microcontroller 232 and may be embedded in the controller 1012 for sequencing. Latch 1016d receives data from the bus 510 words, describing the task set by the controller 240. Register-fiksator1016s receives data from the bus 510, one or more values of the parameters used for the task. Such parameter values may specify, for example, the time interval over which a search function to be performed. While solving the problem of the counter 1014 performs countdown selected time interval, and outputs a sequencing controller 1012 a signal indicating the end of said time interval.
In one embodiment, to simplify the design and reduce circuit complexity and cost of sequencing controller 1012 to implement combinatorial logic. Combinatorial logic provides the appropriate control signals that direct the operation of various elements in the receiving device 200, such as the buffer 224, correlator 522, the control unit 524 demodulation and combiner symbol accumulator 526 and buffering unit 234, and the deinterleaving. Control signals sequentially pass through the various functional blocks and control buffers and elements for processing, providing solution to the problem. For example, the control signals control various multiplexers illustrated in Figure 6C (e.g., multiplexers 612, 622 and 546) to select appropriate input signals fed to the multiplexer, the output signals which should be supplied to the buffer 224 and buffering unit 234, and the deinterleaving . Controller 102 sequencing also directs the operation of various generators 512 and 542 addresses in order to create the desired address.
11A is a timing diagram of the data processing unit 230 samples data in the case of a zero time shift. In this example, for each period of a chip has two data samples and each data sample has four bits of resolution. For each read operation, thirty-two bits of the buffer 224 may be retrieved or 16 integrated in-phase pseudorandom (IPN) and quadrature pseudorandom (QPN) samples for a period of 8 chips, or four complex data samples for a period of two chips.
In the first clock cycle, the pseudo-random samples for eight chips are selected from the buffer 224 and outputted to the latch 732 (see. 7A) in the correlator 522. In the second clock cycle, the data samples for the first two chips corresponding to time offsets of 0.0 0.5, 1.0 and 1.5 are retrieved from buffer 224 and the fixed latch 712a, 712b, 712c and 712d respectively. In the third clock cycle, the sample being in latch 712, again fixed latch 714 and the data samples for the next two chips corresponding to time offsets of 2.0, 2.5, 3.0 and 3.5 are retrieved from buffer 224 and the fixed latch 712a, 712b, 712c and 712d respectively. In the fourth clock cycle, the data samples for the first chip corresponding to time offsets of 0.0 and 0.5, respectively, correlated blocks 720a and 720b multiply located in the correlator 522. In the fifth clock cycle, correlator 522 is idle. In the sixth clock cycle, the data samples for the second chip corresponding to time offsets of 1.0 and 1.5 are correlated units 720c and 720d respectively. Processing carried out during clock cycles from the seventh to the tenth, similar to the processing carried out during clock cycles from the third to the sixth. Next, processing continues in a similar manner as long as no need to find and retrieve the next group of PN samples.
11B is a timing diagram of the data processing unit 230 samples data in the case of time shifting is 1.5. In one embodiment, data samples are retrieved from buffer 224 starting at even chip indices (e.g., 0, 2, 4, etc.). Thus, the time offset for a particular multipath propagation can be divided into the integer part and a fractional part. The integer part indicates the specific even chip index at which to begin extracting data samples. The fractional part shows a specific shift in the half-chip samples in the recoverable data.
As shown in Figure 11B, sample pseudo-random sequences and data samples are retrieved from buffer 224 similarly to the case when the time shift is zero. However, in the third clock cycle, data processing is performed on data samples corresponding to time offsets of 1.5. More specifically, the data sample at time offsets of 1.5 and 2.0 respectively correlated blocks 720a and 720d of multiplication. Similarly, in the fifth clock cycle, the data samples at time offsets of 2.5 and 3.0 respectively correlated blocks 720b and 720c multiplication. Then processing proceeds similarly to the above procedure.
The above-described receiver may advantageously be used in a user terminal or a base station of a communication system. Signal processing may be different for the forward and reverse links, and is typically dependent on the particular system or standard being implemented CDMA. Furthermore, the user terminal typically must process a single transmission from one base station or redundant transmissions from multiple base stations, whereas the base station typically must simultaneously process multiple (and different from each other) transmissions from multiple user terminals. Thus, the receiver is typically designed especially for the particular application of the system in which it is used.
Elements described above as included in the receiving device 200 (e.g., address generator 220, input data interface 222, buffer 224, data processor 230, microcontroller 232, controller 240, etc.) may be implemented within one or more application specific integrated circuits (ASIC), as well as one or more digital signal processors, controllers, microcontrollers, other electronic units designed to perform the functions discussed herein, or some set of these means. The buffer 224 and buffering unit 234, and the deinterleaving can be realized in the form of one or more random access memory (RAM), dynamic RAM (DRAM), flash memory types or units embodying other principles of instruments memory. Furthermore, the buffer 224 and buffering unit 234 and deinterleaving can also be realized within the same integrated circuit used to implement other elements of receiver unit 200.
For clarity, many aspects and embodiments of the invention are described in the context of intentionally transmitting data on the forward link in the HDR CDMA system. However, the invention can also be applied for data transmission on the reverse link and other communications systems (e.g., CDMA system complying with the standard IS-95 CDMA system compliant W-CDMA, etc.).
The foregoing description of the preferred embodiments is provided in order to provide those skilled in the art to make or use the present invention. Those skilled in the art will appreciate that within the scope of the invention various changes may be made to said embodiments and that the generic principles characterized herein can be applied to other embodiments. Thus, one should not consider the present invention consisting in the above embodiments, but should be interpreted in its broadest sense in accordance with the principles and novel features presented above.
Contents5
Every citation, both waysCites: the store holds 4 of 5
| Document | Relation | Office |
|---|---|---|
| EP998052A2 | Cites | European Patent Office (EPO) |
| EP1017183A2 | Cites | European Patent Office (EPO) |
| RU2154913C2 | Cites | Russian Federation |
| US5930704A | Cites | United States of America |
35 members in 18 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 09723795 | United States of America | – | |
| 72379500 | United States of America | A | |
| 72379500 | United States of America | A | |
| 09723795 | – | – | – |
| US20000723795 | – | – | – |
Members35
| Document | Office | Kind | |
|---|---|---|---|
| CA2430128A1 | Canada | A1 | |
| WO0245288A2 | World Intellectual Property Organization (WIPO) | A2 | |
| AU3645902A | Australia | A | |
| WO0245288A3 | World Intellectual Property Organization (WIPO) | A3 | |
| NO20032352D0 | Norway | D0 | |
| KR20030048481A | Republic of Korea | A | |
| NO20032352L | Norway | L | |
| EP1338097A2 | European Patent Office (EPO) | A2 | |
| IL155850A0 | Israel | A0 | |
| IL155850D0 | Israel | D0 | |
| BR0115638A | Brazil | A | |
| CN1481621A | China | A | |
| MXPA03004636A | Mexico | A | |
| TW595149B | Taiwan Province of China | B | |
| JP2004527930A | Japan | A | |
| HK1063541A1 | Hong Kong, China | A1 | |
| UA74397C2 | Ukraine | C2 | |
| US6985516B1 | United States of America | B1 | |
| CN1264283C | China | C | |
| RU2301493C2 | Russian Federation | C2 | |
| JP4119247B2 | Japan | B2 | |
| RU2007108199A | Russian Federation | A | |
| EP1338097B1 | European Patent Office (EPO) | B1 | |
| AT410833T | Austria | T | |
| ATE410833T1 | Austria | T1 | |
| DE60136092D1 | Germany | D1 | |
| EP2073395A2 | European Patent Office (EPO) | A2 | |
| KR100938022B1 | Republic of Korea | B1 | |
| IL155850A | Israel | A | |
| EP2278726A2 | European Patent Office (EPO) | A2 | |
| EP2285008A2 | European Patent Office (EPO) | A2 | |
| EP2073395A3 | European Patent Office (EPO) | A3 | |
| RU2425442C2This record | Russian Federation | C2 | |
| EP2278726A3 | European Patent Office (EPO) | A3 | |
| EP2285008A3 | European Patent Office (EPO) | A3 |
Numbers
- Publication
- 2425442
- Publication, DOCDB
- 2425442
- Publication, EPODOC
- RU2425442
- Application
- 10819909
- Application, DOCDB
- 2007108199
- Application, EPODOC
- RU20070108199
Titles3
- English
- METHOD AND DEVICE TO PROCESS RECEIVED SIGNAL IN COMMUNICATION SYSTEM
- Russian
- СПОСОБ И УСТРОЙСТВО ДЛЯ ОБРАБОТКИ ПРИНИМАЕМОГО СИГНАЛА В СИСТЕМЕ СВЯЗИ
- Russian
- ?????? ? ?????????? ??? ????????? ???????????? ??????? ? ??????? ?????
Classification
- CPC, 5
- H04B1/707
- H04B1/7115
- H04B1/709
- H04B2001/70935
- H04B1/7085
- IPC, 4
- H04B1 707
- H04B1 709
- H04B1 7093
- H04Q7 38