System and process for electro-deposition, etching or removal of material on wafer or semiconductor substrate

System and method for electrodepositing, etching, or removing material on semiconductor substrate or wafer

<p>10. . . Substrate</p><p>12. . . Insulator layer</p><p>14. . . Through hole</p><p>16. . . ditch</p><p>18. . . Barrier</p><p>20. . . Seed layer</p><p>twenty two. . . Conductive material layer</p><p>30. . . Electrodeposition system</p><p>32. . . Wafer</p><p>34. . . Wafer holder</p><p>36. . . Ring fixture</p><p>38. . . Electrical contact</p><p>40. . . Electroplating bath</p><p>42. . . Electroplating electrolyte</p><p>44. . . anode</p><p>46. . . shield</p><p>50. . . Electrodeposition system</p><p>51. . . top</p><p>52. . . bottom</p><p>53. . . Wafer carrier</p><p>54. . . Wafer</p><p>55. . . Carrier arm</p><p>56. . . anode</p><p>57. . . Anode cup</p><p>58. . . Holes</p><p>59. . . Peripheral sidewall</p><p>60. . . bottom</p><p>61. . . Upper edge frame</p><p>62. . . Electrolyte</p><p>63. . . Liquid inlet</p><p>64. . . Anode connector</p><p>65. . . front</p><p>66. . . Electrical contacts</p><p>67. . . Contact zone</p><p>68. . . Connector</p><p>69. . . back</p><p>70. . . Holding ring</p><p>71. . . Shaft</p><p>72. . . turn around</p><p>73-76. . . Sidewall</p><p>77. . . Concave edge</p><p>78. . . Side edge</p><p>79. . . District 1</p><p>80. . . Second district</p><p>81-82. . . arrow</p><p>82. . . shield</p><p>99. . . hole</p><p>100. . . Electrodeposition system</p><p>102. . . Upper part</p><p>104. . . Lower part</p><p>106. . . Wafer carrier</p><p>108. . . Wafer</p><p>110. . . Carrier arm</p><p>112. . . anode</p><p>114. . . Forming plate</p><p>116. . . Anode cup</p><p>118. . . Anode plate</p><p>119. . . Upper surface</p><p>120. . . Opening</p><p>121. . . Liquid inlet</p><p>122. . . arrow</p><p>124. . . Anode connector</p><p>126. . . Electrical contacts</p><p>128. . . Contact zone</p><p>129. . . Connector</p><p>130. . . back</p><p>131. . . lower surface</p><p>132. . . front</p><p>133. . . Holding ring</p><p>134. . . Shaft</p><p>135. . . turn around</p><p>136-142. . . Sidewall</p><p>144. . . Concave edge</p><p>146. . . Lateral edge</p><p>148. . . District 1</p><p>149. . . Second district</p><p>150. . . Inner wall</p><p>152. . . Top opening</p><p>154. . . Lower opening</p><p>156. . . Underside</p><p>157-158. . . Uneven area</p><p>159. . . hole</p><p>160. . . Electrolyte channel</p><p>162. . . Inner cavity</p><p>164. . . arrow</p><p>166. . . Surface part</p><p>168. . . Through hole structure</p><p>170. . . ditch</p><p>172. . . Insulator layer</p><p>174. . . Substrate</p><p>176. . . Active device location</p><p>178. . . Copper seed layer</p><p>180. . . Sedimentary layer</p><p>182. . . Planarization layer</p><p>264. . . arrow</p>

1A is a schematic diagram of a semiconductor substrate. The semiconductor substrate has an isolation structure formed on the top surface of the substrate, wherein the isolation structure is etched to form trenches and through-hole structures in the substrate;

1B is a partial cross-sectional view of the substrate shown in FIG. 1A, in which the barrier layer and the seed layer are formed on each structure and the isolation layer or insulating layer;

FIG. 1C is a schematic diagram of the structure shown in FIG. 1B, in which the conventional contour layer is partially deposited on the seed layer;

Figure 1D is a schematic diagram of the structure shown in Figure 1C, in which the layer has been completely deposited;

FIG. 1E is a schematic diagram of the structure shown in FIG. 1D, in which a more planar layer has been formed;

Figure 2A is a schematic diagram of the prior art electrodeposition system;

Figure 2B is a schematic diagram of another prior art electrodeposition system using shielding;

Figure 3 is a schematic diagram of a specific embodiment of the system of the present invention, which is used to deposit conductive material on the entire surface of the wafer without excluding any edge regions;

4 is a schematic diagram of the system shown in FIG. 3, showing the position of electrical contacts and contact areas on the wafer relative to the width of the peripheral sidewall of the anode cup of the present invention;

Figure 5 is a partial plan view of the system shown in Figure 3, showing intermittent and continuous deposition areas on the wafer;

Fig. 6 is a schematic diagram of the system of the present invention shown in Fig. 3, including a shield provided between the anode and the cathode of the system;

7 is a schematic diagram of another embodiment of the system of the present invention, the system is used to deposit conductive material on the entire surface of the wafer without excluding any edge regions;

FIG. 8 is a partial schematic diagram of the system shown in FIG. 7, showing the wafer carrier assembly and forming plate of the present invention;

FIG. 9A is a plan view of a forming board with a wafer positioned on the forming board, where the wafer has continuous and intermittent deposition areas;

Figure 9B is a schematic cross-sectional view of the forming plate, showing continuous unevenness through the forming plate;

9C is a schematic diagram of another specific embodiment of the forming plate of the present invention, wherein the forming plate has two regions, which have different opening densities;

10A is a schematic side view of the electrodeposition system of the present invention, showing the position of the wafer electrical contact on the contact area relative to the width of the forming plate of the present invention;

10B is another schematic side view of the electrodeposition system of the present invention, showing the position of the wafer along the length of the forming plate of the present invention;

11A is a highly enlarged cross-sectional view of a wafer with a through hole and trench structure covered with a seed layer before the deposition method of the present invention;

FIG. 11B is a schematic diagram of the structure shown in FIG. 11A, in which the deposition layer has been electrodeposited according to the present invention; and

Fig. 11C is a schematic diagram of the structure shown in Fig. 11B, in which the deposition layer is deposited in a planar manner.

This case claims the priority of the previous U.S. Provisional Application 60245,211, filed on November 3, 2000, and the entire disclosure of the case is expressly incorporated herein by reference.

Field of invention

The present invention generally relates to electrodeposition processing technology, and particularly relates to the electrodeposition process for obtaining uniform and flat deposits.

Prior technical description

The conventional semiconductor device usually includes a semiconductor substrate, and usually a silicon substrate, a multilayer dielectric intermediate layer formed in sequence, such as silicon dioxide, and conductive paths or interconnections made of conductive materials. Interconnects are usually made by filling conductive materials in trenches etched into the dielectric interlayer. In an integrated circuit, the multi-level connection network extends laterally with respect to the surface of the substrate. The interconnection lines formed in different layers can be electrically connected using through holes or contact lines. The conductive material filling process for filling these structures, that is, via openings, trenches, pads, or contact lines, can be performed by depositing conductive materials on the substrate including these structures. The excess conductive material on the substrate can then be removed using planarization and polishing techniques such as chemical mechanical polishing (CMP).

Copper (Cu) and copper alloys have recently gained considerable attention as connecting materials due to their excellent electromigration characteristics and low resistivity characteristics. The preferred copper deposition method is electrodeposition. During the manufacturing process, copper is electroplated or electrodeposited on the substrate previously coated with the barrier layer and the seed layer. Typical barrier materials generally include tungsten (W), tantalum (Ta), titanium (Ti), their alloys and their nitrides. The typical copper seed material is usually a thin layer of copper, which is CVD or PVD deposited on the aforementioned barrier layer.

There are many different designs of copper plating systems. For example, US Patent No. 5,516,412 issued to Andricacos et al. on May 14, 1996 discloses a vertical paddle electroplating element, which is configured to electrodeposit thin films on flat objects.

U.S. Patent No. 5,985,123 issued to Koon on November 16, 1999 discloses another vertical electroplating device which aims to overcome the non-uniform deposition problem associated with changes in the size of the substrate.

During the copper electrodeposition process, a specially formulated electroplating solution or electrolyte is used. These electroplating solutions or electrolytes contain copper ion species and additives to control the texture, morphology, and coating performance of the deposited material. Additives are needed to make the deposited layer smooth and slightly shiny.

There are many different types of copper electroplating solution formulations, some of which are commercially available. One of the formulations includes copper sulfate (CuSO ₄ ) As a source of copper (refer to James Kelly et al., Journal of The Electrochemical Society, Issue 146, pp. 2540-2545, (1999)) and include water, sulfuric acid (H ₂ SO ₄ ) And a small amount of chloride ions. As is well known, other chemicals commonly known as additives can be added to the copper plating solution to obtain the predetermined properties of the deposited material (for example, refer to Robert Mikkola and Linlin Chen "Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistry used for Adranced Interconnect Metallization", Proceedings of the International Interconnect Technology Conference, pages 117-119, June 5-7, 2000).

Figures 1 to 2 illustrate conventional electrodeposition methods and apparatuses. Figure 1A illustrates a substrate 10 having an insulator layer 12 formed thereon. Using conventional etching techniques, a structure such as a row of small through holes 14 and wide trenches 16 is formed on the insulating layer 12 and on the exposed area of the substrate 10. In this example, the through hole 14 is narrow and deep; in other words, it has a high aspect ratio (that is, the ratio of depth to width is large). Typically, the width of the through hole 14 is sub-micron in size. In other respects, the trench 16 shown in this example is wide and has a small aspect ratio. The width of the trench 16 is 5 to 15 times or more larger than the depth.

Figures 1B-1C illustrate the conventional method of filling the structure with copper material. FIG. 1B shows that the barrier/adhesive or adhesion layer 18 and the seed layer 20 are sequentially deposited on the substrate 10 and the insulator 12. The barrier layer 18 may be tantalum, tungsten, titanium, alloys thereof, nitrides, or combinations thereof. The barrier layer 18 is usually deposited using various sputtering methods, chemical vapor deposition (CVD), or electroless plating methods. Subsequently, the seed layer 20 is deposited on the barrier layer 18. If the conductor to be electroplated is also copper and can be deposited on the barrier layer 18 using various sputtering methods, CVD or electroless deposition or a combination thereof, the seed layer 20 is typically copper.

In FIG. 1C, after the seed layer 20 is deposited, a conductive material layer 22 (for example, a copper layer) is partially electrodeposited on the seed layer 20 by using a suitable plating bath or plating bath compounding agent. During this step, electrical contact is made to the copper seed layer 20 and/or the barrier layer 18, so a cathode (negative) voltage can be applied to the anode (not shown in the figure). Subsequently, as discussed above, the copper material layer 22 is electrodeposited on the surface of the substrate using an electroplating solution. By adjusting the amount of additives such as chloride ions, suppressors/inhibitors, and accelerators, bottom-up copper film growth can be obtained in small structures.

As shown in FIG. 1C, the copper material 22 completely fills the through hole 14 and is usually equal in shape to the large trench 16 because the additives used cannot exert an effect on the large structure. For example, it is believed that because the suppressor/inhibitor molecule itself adheres to the top of the through hole 14 and inhibits the growth of the surrounding material, a bottom-up deposition enters the through hole 14. These molecules cannot effectively diffuse to the bottom surface of the through hole 14 through the narrow opening. The preferential absorption of the accelerator on the bottom surface of the through hole 14 will lead to bottom-up growth and obtain the copper deposition side curve as shown in FIG. 1C. Here, the copper thickness t1 on the bottom surface of the trench 16 is approximately equal to the copper thickness t2 above the insulator layer 12.

As expected, in order to completely fill the trench 16 with copper material, further plating is required. Figure 1D illustrates the structure obtained after additional copper plating. In this example, the copper thickness t3 above the insulator layer 12 is quite large, and there is a step S from the top of the copper layer on the insulator layer 12 to the top of the copper layer 22 in the trench 16 ₁ . For integrated circuit (IC) applications, the copper layer 22 must be subjected to chemical mechanical polishing or other material removal treatments. Therefore, the copper layer 22 and the barrier layer 18 on the insulator layer 12 are removed, leaving only the inside of the structures 14 and 16 Copper layer. It is known that such a removal process will cost a lot.

The method and apparatus to achieve the schematic planar copper deposit shown in FIG. 1E is of no value in terms of processing efficiency and cost. In this example, the copper thickness t5 on the insulator layer 12 is smaller than the conventional example shown in FIG. 1D, and the step S ₂ The height is far lower. In FIG. 1E, chemical mechanical polishing or other methods are used to remove the thinner copper layer, which is easier and saves the cost.

In the jointly examined U.S. Patent Application No. 09/201,929, titled "Method and Apparatus for Electrochemical Mechanical Deposition", the filing date was December 1, 1998, and was jointly owned by the assignee of the present invention. The case discloses a Technology, which can achieve the deposition of conductive material on the cavity on the surface of the substrate. At the same time, by polishing the electric field area with a pad when the conductive material is deposited, the deposition of the electric field area is minimized, thus obtaining a flat surface. Copper deposits.

FIG. 2A shows a schematic diagram of a prior art electrodeposition system 30. In this system, the wafer 32 is clamped by the wafer holder 34 by means of a ring clamp 36 covering the peripheral edge of the wafer 32. The electrical contact wire 38 is also shaped in a ring shape and connected to the (one) end of the power supply for cathode plating. The wafer holder 34 descends into the electroplating bath 40 filled with the electroplating electrolyte 42. The anode 44 contacting the electrolyte 42 is placed on the opposite side of the wafer and connected to the (+) end of the power supply. The anode 44 may be made of a material to be deposited, such as copper, or a suitable inert anode material, such as platinum, titanium-plated platinum, or graphite. The plating method starts with power supply. In this plating system, the electrical contact wire 38 is sealed with electrolyte, and the plating current is passed through the periphery of the wafer 32. However, the contact lines 38 and clamps 36 existing on the periphery of the wafer are the main advantages of this system and increase the edge removal range, as indicated by "EE" in FIG. 2A. As a result of edge removal, the extremely valuable primer area on the surface of the wafer 32 is lost.

Figures 1A to 1E show how the structures on the surface of the wafer are filled with copper. In order for this filling process to be effective and uniform across the entire wafer, it is important to deposit a uniform thickness of copper on the entire wafer surface. The thickness uniformity must be excellent, because the uneven copper thickness will cause problems in the CMP process. As shown in FIG. 2B, in order to improve the uniformity of the deposited layer, the prior art electroplating system may include a shield 46, as shown in FIG. 2A. In this system, either the wafer 32 or the shield 46 can be rotated. Such shielding is described in, for example, US Patent No. 6,027,631 by Broadbent, US Patent No. 6,074,544 by Reid et al., and US Patent No. 6,103,085 by Woo et al.

In view of the foregoing description, other electrodeposition methods and systems are needed, which can minimize the problem of edge removal range and deposit a uniform conductive film.

Summary of the invention

The present invention relates to the deposition of conductive materials on the entire surface of a semiconductor wafer via an electrodeposition method. In particular, the present invention provides a method and system for forming a substantially flat conductive material film on the entire surface of a semiconductor wafer without losing any space on the surface for electrical contact, in other words, there is no edge removal phenomenon of the wafer.

One aspect of the present invention is a method for depositing material on the surface of a wafer without excluding any area for electrical contact on the surface, wherein the wafer has the largest lateral dimension. The method includes the following steps: setting an anode, supporting the forming plate between the anode and the surface of the wafer, the electrolyte flowing through the forming plate and between the anode and the surface of the wafer, the contact area of the wafer surface contacts the contact, and applying a potential difference to the anode Between and contacts.

The forming plate is supported between the anode and the surface of the substrate so that the upper surface of the forming plate faces the surface of the wafer. The forming plate includes a plurality of openings, and each opening allows the surface of the wafer to be in fluid communication with the anode. The lateral dimension of the formed plate is longer than the maximum lateral dimension of the wafer. The contact piece contacts the contact area on the surface of the wafer outside the edge of the "recess" of the forming plate, and thereby makes electrical contact with the surface of the wafer. When a potential difference is applied between the anode and the contact, and when the wafer is in the first position, deposition of material on the surface of the wafer through the forming plate occurs in the deposition area. By moving the wafer to the second position while the contact area is in contact with the contact, material deposition occurs in both the contact area and the deposition area.

According to another aspect of the present invention, a system for depositing materials on the surface of a wafer with the largest lateral dimension is provided. The system includes an anode, a forming plate defining a recessed edge, a liquid electrolyte contained between the anode and the surface of the substrate, and electrical contacts for contacting a contact area on the surface of the substrate outside the recessed edge of the forming plate.

The forming plate can be supported between the anode and the surface of the wafer, so the upper surface of the forming plate faces the surface of the wafer. The forming plate includes a plurality of openings. The lateral dimension of the upper surface of the forming plate is longer than the maximum lateral dimension of the wafer. The electrolyte flows through the openings of the forming plate and flows against the wafer surface, so the electrolyte often contacts the first area of the wafer surface. The electrical contact is in electrical contact with the second area of the wafer surface outside the recessed edge of the forming plate. When the wafer rolls on the forming plate, the second zone will intermittently contact the electrolyte.

According to yet another aspect of the present invention, there is provided a system whereby a conductive material can be deposited on the surface of a semiconductor substrate from an electrolyte. The system includes an assembly whereby the assembly supplies the electrolyte to the surface of the substrate during material deposition. , And the anode contacted by the electrolyte during the deposition process. At least one contact line is electrically interconnected with the selected area on the surface during the deposition process. The deposition of the material is discontinuous on the selected area and continuously on the rest of the surface. The reason is that during the application of the potential difference between the anode and the contact line, one of the contact line and the surface moves relative to each other.

It can provide a device for improving the uneven deposition of materials on selected areas and other surfaces. The device includes a shield with an opening defined therein and arranged between the anode and the surface to change the electric field distribution. In addition, the device may include a perforated plate, which is arranged between the anode and the surface, has uneven areas and each has a different degree of open area.

The electrolyte supply assembly includes a cup, which defines a cavity through which the electrolyte flows during the deposition of the conductive material. The anode is accommodated in the cavity, and the contact line is arranged outside the cavity. The assembly further includes an inlet for supplying electrolyte to the cavity.

The rotatable and preferably translatable carrier clamps the substrate during the deposition of the conductive material so that the surface of the substrate can be moved relative to the contact line.

During the deposition of the conductive material, the forming plate is placed between the anode and the surface. The shaped plate is porous and allows electrolyte to flow through it.

If the polarity of the system is reversed, the system can replace the deposited material by electro-etching the wafer or substrate in a consistent manner to remove material. In this case, the electroplating electrolyte can be replaced by commonly known electro-etching or electro-polishing solutions. In this example, the anode can be replaced by an inert electrode made of an inert material.

These and other features, aspects and advantages of the present invention will be more apparent with reference to the drawings, descriptions and the scope of the patent application.

Detailed description of the invention

The present invention relates to depositing conductive materials on the entire surface or entire surface of a semiconductor substrate or wafer through an electrodeposition method. As will be described in detail later, the present invention provides a method for forming a substantially flat conductive material layer on the entire surface of a semiconductor substrate without losing any space on the surface for electrical contact, in other words, without removing the edge of the wafer, and system. The overall deposition method of the present invention can advantageously achieve the deposition of conductive materials on multiple cavities, such as trenches, through holes, contact holes, etc., on the entire surface of the semiconductor wafer.

In a specific embodiment, the present invention adopts forming cups or anode cups, and directly transporting electrolyte to the wafer surface, while depositing conductive material on the wafer surface. In another embodiment, the conductive material is deposited via a perforated plate. In this embodiment, the perforated plate facilitates the consistent deposition of conductive materials. In yet another specific embodiment, the present invention achieves that the conductive material is deposited on the surface structure of the wafer through the perforated plate, and the surface is contacted, wiped and polished by using the perforated plate of the present invention to deposit on the top surface area between the structures. The deposition is minimized.

The method of the present invention has enhanced deposition characteristics, and as a result, the obtained layers have flatness that could not be achieved before, and have material properties that surpass the conductive layers of the prior art layers manufactured by the devices of the prior art methods.

The description will now be made with reference to the drawings, in which similar component numbers indicate similar parts in each figure. As shown in FIG. 3, in a specific embodiment, the electrodeposition system 50 of the present invention preferably includes an upper portion 51 and a lower portion 52. In a preferred embodiment, the system 50 is used to deposit conductive materials such as copper on semiconductor wafers such as silicon wafers. It should be noted that although copper is used as an example, the present invention can be used to deposit other common conductors, such as nickel, palladium, platinum, gold and their alloys. The upper portion 51 of the electrodeposition system 50 may be composed of a carrier assembly with a wafer carrier 53 attached to the carrier arm 55, as shown in FIG. 3, the wafer carrier clamps a typical wafer 54.

The lower part 52 of the system 50 may be composed of an anode assembly, which includes an anode 56 which is preferably arranged in an enclosure such as an anode cup 57 or a shaped cup. The anode cup 57 includes an inner cavity 58 or shell defined by a peripheral side wall 59 raised on the bottom wall 60. The upper edge frame 61 of the peripheral side wall 59 forms the upper end of the anode cup 57. In this embodiment, the upper edge frame 61 is preferably a rectangular shape. When the wafer carrier 53 descends toward the edge frame 61, the plane of the edge frame is substantially parallel to the wafer. As shown in Figure 5, the rim has a maximum lateral dimension D. The copper-plated electrolyte 62 is pumped into the anode cup 57 through the liquid inlet 63 formed in the bottom wall 60 in the direction of the arrow 264. In this way, the anode cup and the inlet form at least a part of the assembly through which the electrolyte 62 is supplied to the front surface of the semiconductor wafer or substrate. During the electrodeposition process, the anode cup 57 is completely filled with electrolyte 62 to the edge frame 61. The anode 56 is electrically connected to the positive terminal of a power source (not shown in the figure) via an anode connector 64. During the electrodeposition process, the wafer 54 remains substantially parallel to and closely adjacent to the edge frame 61 and is rotated. By controlling the flow rate of the electrolyte 62, the electrolyte contacts the front face 65 of the immediately adjacent wafer. Excess electrolyte flows downward through the peripheral side wall 59 and is collected for recycling.

In this embodiment, it is necessary to understand that the electrical contacts 66 contact or otherwise electrically interconnect the contact areas 67 of the wafer 54 on the front surface 65 of the wafer. The position of the contact area 67 changes circularly with respect to the rim 61 when the wafer 54 rotates on the anode cup 57. The contact 66 is connected to a negative power source (not shown in the figure) using a connector 68.

As shown in FIG. 4, the wafer carrier 53 clamps the wafer 54 by the back 69 of the wafer 54 and abuts against the chuck surface of the wafer carrier 53. The wafer 54 can be held by a vacuum extraction or holding ring 70 (shown in FIG. 4) or both, so that the front surface 65 and the contact area 67 of the wafer 54 are completely exposed. According to the principles of the present invention, the wafer 54 defines a maximum lateral dimension d, which in this example is the diameter of the wafer. In addition, the holding ring 70 may be an essential part of the wafer carrier 53. During the processing, the wafer carrier 53 and the associated wafer 54 can rotate the carrier arm 55 in the rotation direction 72 by using the rotating shaft 71 or the longitudinal axis of the wafer carrier 53 as an axis. As will be described in detail later, the rotating movement moves the contact area 67 on the electrolyte 62, exposing the contact area 67 to the electrolyte. The combined effect of the complete exposure of the front side 65 of the wafer 54 and the ability to expose the contact area 67 to the electrolyte 62 by moving the contact area 67 on the anode cup 57 will result in zero edge exclusion of the wafer 54.

As shown in FIGS. 4 and 5, in this embodiment, the peripheral side wall 59 of the forming cup or anode cup 57 is roughly shaped as a rectangular side wall, including a first side wall 73, a second side wall 74, a third side wall 75 and a fourth side wall 76 . In this embodiment, the lengths of the first and second side walls 73, 74 are longer than the lengths of the third and fourth side walls 75, 76, and the "recessed" edge 77 of the peripheral side wall 59 is formed, in other words, relative to the wafer 54 The outer edge of the circumference is sunken. The third and fourth side walls 75 and 76 form the side edges 78 of the peripheral side walls of the anode cup 57. In this embodiment, the width of the anode cup 57 or the distance between the recessed edges 77 is suitably shorter than the diameter of the wafer 54, and the wafer diameter is the maximum lateral distance d of the wafer; at the same time, the maximum lateral distance D of the edge frame 61 is also That is, the anode cup length or the side edge spacing is suitable to be longer than the wafer diameter.

Due to the difference between the maximum lateral distance d and the width of the upper edge frame, this configuration exposes the contact area 67 on the wafer 54 and allows the electrical contact 66 to be disposed on the contact area 67. Although the recessed edge 77 is straight in this embodiment, within the scope of the present invention, the recessed edge 77 may be formed into a recess, a V-shape, or other possible configurations that may allow electrical contacts to be provided on the front surface 65 of the wafer. It should be noted that in any particular case, when the contact area 67 is attached to the electrolyte 62 and rotates, the contact area 67 on the wafer 54 can only be plated with copper. In this regard, when the wafer 54 rotates, the first region 79 shown in the dashed circle in FIG. 5 is constantly maintained on the anode cup and continuously electroplated. However, the selected second area 80 on the surface is located outside the first area 79 and is defined by the contact area, and the deposition process is performed in a discontinuous manner. Therefore, the deposition rate of the first region 79 is different from the deposition rate of the second region 80, so that the deposition layer of the second region 80 is thinner.

FIG. 6 shows how to improve the non-uniformity of the deposited layer by using the mask 82. The shield 82 is immersed in the electrolyte in the manner shown in FIG. 6 and positioned adjacent to the first region 79, but if the distance from the anode to the cathode (wafer) is shortened, the shield can rest on the anode 56. The shield 82 has holes 99 or openings. Shielding changes the electric field distribution between the anode and the first area 79 (refer to FIG. 5) or the contact area 67 of the wafer 54, and changes the deposition rate of the first area 79, thereby modifying the electrodeposited copper across the front surface 65 of the wafer Thickness changes. In this embodiment, the shield 82 may be made of a non-conductive material such as a polymer material.

Referring back to FIGS. 4 and 6, in use, the electrolyte is pumped into the anode cup 57 in the direction of arrow 264. Whenever the electrolyte fills the anode cup 57 by applying pressure, the electrolyte will reach the front surface 65 of the wafer 54 in the direction of the arrow 81. As mentioned above, the front face 65 of the wafer 54 is held next to the electrolyte. The gap between the front surface 65 of the wafer 54 and the electrolyte surface is adjusted by vertically moving the carrier assembly 53 along the shaft 71. After adjusting the distance between the front surface 65 and the electrolyte, the electrodeposition process is initiated by applying a potential difference between the anode 56 and the contact 66. At this stage, the potential difference is selected so that the contact becomes more cathodic (-) than the anode. Furthermore, since the contact piece contacts the front surface 65 of the wafer 54, the front surface 65 also becomes cathodic. As the deposition process proceeds, copper is uniformly deposited on the front surface 65. As mentioned above, the contact area on the wafer 54 is electroplated only when the contact area 67 rotates on the electrolyte 62 and is therefore exposed to the electrolyte. Arrow 82 indicates that the overflow electrolyte can be collected and recycled.

As shown in FIG. 7, in another specific embodiment, the electrodeposition system 100 of the present invention preferably includes an upper portion 102 and a lower portion 104. In a preferred embodiment, the system 100 is used to deposit conductive materials such as copper on semiconductor wafers such as silicon wafers. As in the previous specific embodiment, although copper is used as an example, the present invention can be used to deposit other common conductors such as nickel, palladium, platinum, gold and their alloys. The upper portion 102 of the electrodeposition system 100 may be composed of a carrier assembly. The carrier assembly has a wafer carrier 106 attached to the carrier arm 110 and clamps a typical wafer 108 as shown in FIG. 7. The carrier arm can rotate or move the wafer 108 in a horizontal or vertical direction.

The lower part 104 of the system 100 is composed of an anode assembly, which includes an anode 112, preferably a consumable copper anode, and a shaped plate 114. The anode is preferably placed in an enclosure such as the anode cup 116, and when the forming plate 114 is placed, it is sealed by the anode plate 118. The forming plate 114 and the anode plate 118 are preferably perforated plates. The forming plate 114 includes a plurality of openings 120 or uneven. The opening 120 is suitable for roughly matching the opening of the anode plate 118 (refer to FIGS. 10A and 10B), so when they are attached together, the corresponding openings form channels allowing the electrolyte to flow through the plates 114 and 118 and wet the wafer 108 during the electrodeposition process. front. During the electrodeposition process, the wafer 108 remains substantially parallel to the upper surface 119 of the forming plate 114 and rotates. The wafer can also move laterally. The copper-plated electrolyte is pumped into the anode cup 116 through the liquid inlet 121 in the direction of the arrow 122. Therefore, the anode cup and the inlet again constitute at least a part of the assembly, whereby part of the electrolyte can be supplied to the front surface of the semiconductor wafer or substrate. The anode 112 is connected to the positive terminal of a power source (not shown in the figure) via an anode connector 124. It should be noted that if the forming plate 114 is made of rigid material, the anode plate 118 does not need to be used.

As will be described in detail later, in this embodiment, the electrical contact 126 contacts or electrically interconnects the wafer 108 with the contact area 128 in other ways. When the wafer 108 rotates or moves on the forming plate 114, the position of the contact area 128 relative to the forming plate 114 changes in a circular manner. The contact is connected to the negative end of the power supply (not shown in the figure) using the connector 129.

As shown in FIG. 8, the wafer carrier 106 clamps the wafer 108 by the back 130 of the wafer 108. The wafer 108 can be fixed on the lower surface 131 or the chuck surface of the wafer carrier 106 as shown in FIG. 8. In this embodiment, the wafer is clamped by a vacuum extraction or holding ring 133 (as shown in FIG. 8) or both, thereby completely exposing the front surface 132 of the wafer 108 to the electrolyte. In addition, the holding ring 133 may be a necessary component of the wafer carrier 106. During the processing, the wafer carrier 106 and thus the wafer 108 can be rotated by rotating the carrier arm 110 in the rotation direction 135 with the rotation axis 134 or the longitudinal axis of the wafer carrier 106 as the center. As will be described in detail later, the rotational movement is preferable to moving the contact area 128 above the forming plate 114, and exposing the contact area 128 to the full exposure of the front surface 132 of the wafer 108 and moving the contact area through the electrolyte flowing through the forming plate (refer to FIG. 7). The combined effect of the ability to continuously expose the contact area 128 to the electrolyte on the forming plate 114 results in zero edge rejection of the wafer 108.

As shown in FIGS. 9A-9B, in this specific embodiment, the forming plate 114 of the present invention is generally shaped into a rectangle defined by the first side wall 136, the second side wall 138, the third side wall 140, and the fourth side wall 142. In this embodiment, the lengths of the first and second side walls 136, 138 are longer than the lengths of the third and fourth side walls 140, 142, and form the "recessed" edge 144 of the forming plate 114, in other words relative to the wafer 108 A concave edge on the outer periphery. The third and fourth side walls 140 and 142 form the lateral edge 146 of the forming plate 114. The width of the forming plate 114 or the distance between the recessed edges is configured to be smaller than the diameter d of the wafer 108. Similar to the previous embodiment, the distance between the lateral edges 146 is the maximum lateral distance D of the forming plate 114. Further, the diameter of the wafer is the maximum lateral distance d of the wafer 108. Although in the preferred embodiment, the shaped plate 114 is shaped as a rectangle, the shaped plate can have any geometric form.

As shown in FIG. 9A, the difference between the lateral distance d and the width of the forming plate exposes the contact area 128 on the wafer 108, and further allows the electrical contact 126 to be disposed in the contact area 128 (refer to FIG. 7). Although the shape of the recessed edge in this embodiment is straight, within the scope of the present invention, the recessed edge can be shaped as a recess, a V-shape or any other possible configuration that allows electrical contacts to be provided on the front surface of the wafer. By selecting the width and length of the forming plate 114 as described above, when the wafer 108 is moved on the forming plate 114 in the first direction 147, the contact area 128 can contact or electrically connect the electrical contacts 126 in other ways. In FIG. 9A, the electrical contact is shown as a linear strip contacting the contact area 128. It should be noted that in any particular case, the contact area 128 of the wafer is only plated with copper when the contact area rotates over the unevenness of the forming plate 114. In this regard, when the wafer is rotating, the first region 148, shown as a dashed circle in FIG. 9A, often stays on the forming plate 114 and is continuously electroplated. However, in the second selected area 149 outside the first area 148 and defined by the contact area, the deposition process is performed in a discontinuous manner. Therefore, the deposition rate of the first region 148 is different from the deposition rate of the second region 149, so the deposition layer of the second region 149 is expected to be slightly thinner. As will be detailed later, this thickness difference can also be eliminated by other uneven designs. In addition, the mask 82 described above and shown in FIG. 6 can use this embodiment to provide a uniform deposition layer across the front side 132 of the wafer 108.

9B, the unevenness 120 is defined by the inner side wall 150, and the inner side wall 150 extends between the opening 152 on the upper surface 119 and the opening 154 on the bottom surface 156 of the forming plate 114. As mentioned above, during the electrodeposition process, the electrolyte solution passes through the unevenness 120 to reach the front surface of the wafer. According to the function of the forming plate 114, the forming plate 114 can be made of insulating material or conductive material. If only electrodeposition is performed, the forming plate can also be made of conductive material. However, if electrodeposition and polishing are performed together, insulating materials such as polymer materials or ceramic materials are better. Although the unevenness 120 in this embodiment is a rectangular shape, the unevenness can be formed into a variety of geometric forms such as oval, square, circular, and so on. The shape and volume space and density of the unevenness 120 define the uniformity of the deposited film. The inner side wall 150 of the unevenness 120 does not need to be perpendicular to the upper surface 119 and the bottom surface 156. In other words, the inner side wall may be an inclined surface, a curved surface, or other forms or shapes.

FIG. 9C shows an alternative embodiment of the forming plate 114. In this embodiment, the forming plate 114 includes first and second uneven regions 157 and 158, respectively. Due to the design of the uneven area, the second uneven area 158 has a higher degree of open area than the first uneven area 157, resulting in higher copper deposition on the wafer. When the copper is electroplated by swinging around the position A in the first region 157, a certain thickness of the deposited layer can be obtained, and the thickness of the deposited layer along the contact region 128 can be slightly thinner. In order to increase the thickness along the contact area 128, the wafer can be moved to position B and partially located above the second area 158, thereby exposing the contact area 128 to a higher copper deposition rate. This step can be performed in part of the electrodeposition process, so a consistent deposition situation for the deposited copper layer is achieved. Such high-density regions can be formed at one or more positions of the forming plate 114, and the thickness variation of the deposited layer can be arbitrarily changed or controlled, which is also within the scope of the present invention. In other words, the curve drawn across the thickness side of the front surface of the wafer becomes concave, convex or completely flat. In this embodiment, the edge exclusion can be reduced to zero. In other words, the front surface of the complete wafer can be evenly electroplated to the edge of the wafer.

As shown in FIGS. 10A and 10B, the forming plate 114 is disposed on the anode plate 118 with porous 159. The holes 159 of the anode plate 118 and the unevenness 120 of the forming plate 114 form a continuous electrolyte channel 160, which connects the inner cavity 162 of the anode cup 116 (the cavity is filled with electrolyte during processing) to the upper surface 119 of the forming plate 114. The electrolyte enters the anode cup in the direction of arrow 122 and flows through the channel 160 in the direction of arrow 164. A filter (not shown in the figure) can be provided in the inner cavity 162 to capture particles generated by the dissolution of the anode 112 during electroplating. The anode plate 118 may be made of an insulating material or a conductive material. For systems that do not use consumable anodes, the anode plate 118 can be used as an anode, or another inert cathode can be placed in place of the anode 112. In such a system, the anode plate can be made of a metal such as titanium, and is preferably coated with an inert metal such as platinum. In this way, the positive voltage is connected to the anode plate rather than to the consumable anode, such as the copper anode in the example of the present invention.

FIG. 10A also shows the position of the contact member 126 in contact with the contact area 128. Contacts can be manufactured in a variety of configurations such as brushes, pins, rollers, flat surfaces, and so on. The contact must be clearly separated from the anode, preferably fixed and the contact area slides on it. The contacts can also move with the wafer. The contact is preferably made of or coated with a flexible corrosion-resistant conductive material, such as platinum, ruthenium, rhodium, and heat-resistant metal nitride. As mentioned above and as shown in FIG. 10A, since the conventional fixture is not used to establish electrical contact with the front surface 132 of the wafer 108, the edge exclusion during deposition can be excellently reduced to zero. Scratching the contact area by the contact element can be prevented or minimized by ensuring that the force applied by the contact element to the contact area is minimized.

Referring back to FIG. 10A, in the method of the preferred embodiment, the electrolyte is pumped in the direction of arrow 122 into the cavity 162 of the anode cup 116 of the electrodeposition system 100. Once the electrolyte fills the cavity 162, the electrolyte flows through the holes 159 of the anode plate 118 and then through the unevenness 120 of the forming plate 114 to reach the front side 132 of the wafer 108. Referring now to FIGS. 10A-10B, the front side 132 of the wafer 108 can be clamped at a first position along the axis 134, preferably immediately adjacent to the forming plate 114, for example, at a distance of 0.25-5 mm. The gap between the front surface 132 of the wafer 108 and the forming plate 114 can be adjusted by vertically moving the carrier assembly 102 along the axis 134. After adjusting the distance between the front surface 132 and the upper surface of the forming plate 114, the electrodeposition process is initiated by applying a potential difference between the anode 112 and the contact 126. In this way, at this stage, the potential difference is selected so that the contact becomes more cathodic than the anode (-). Further, since the contact piece contacts the front surface 132 of the wafer 108, the front surface 132 also becomes cathodic.

At this time, the details of the electrodeposition method using the system 100 of the present invention will be further explained with reference to FIGS. 11A and 11B. FIG. 11A illustrates the surface portion 166 of the front surface 132 of the wafer 108 before the electrodeposition process (refer to FIG. 8). The surface portion 166 includes through-hole structures 168 or shallow holes and trenches 170 or larger holes. The via structure 168 and the trench structure 170 can be formed on the insulator layer 172. The insulator layer is formed on the substrate 174 and can be used as part of the wafer 108 or formed on the wafer 108. The structures 168 and 170 expose the location 176 of the active device of the substrate 174.

10B, once the potential difference is applied, when the wafer 108 rotates in the rotation direction 135 and moves linearly on the forming plate 114 in the first direction 147, as shown in FIG. 10B, the copper plating layer is on the front surface 132. The first direction 147 is preferably parallel to the recessed edge 144 and perpendicular to the side edge 146. Although the linear movement in the first direction 147 is preferably from about 5 mm to 100 mm depending on the wafer size, longer-distance linear movement is also within the scope of the present invention and can be applied. In this regard, the rotation speed of the wafer 108 is about 1 rpm to 250 rpm. Although it is better to move the wafer laterally, it must be understood that the wafer can be rotated and the anode assembly can be moved laterally to achieve similar movement between the wafer and the forming plate. As shown in FIG. 11B, as the deposition process progresses, the deposition layer 180 is uniformly formed on the copper seed layer 178 and fills the via and trench structures 168 and 170. As mentioned above, the copper seed layer 178 may be formed on top of the barrier layer. As mentioned above, by rotating the wafer 108, the non-uniformity of the deposited layer can be minimized. The contact area 128 on the wafer is electroplated only when the contact area 128 rotates above the unevenness 120 of the forming plate 114 and is therefore exposed to the electrolyte.

10B, in order to deposit a flat film, the gap between the forming plate 114 and the front surface of the wafer 108 can be reduced to zero. By vertically moving the carrier assembly 102 and the wafer 108 along the axis 134 to the second position, the front surface 132 is formed into contact The upper surface 119 of the board 114. In this example, the forming plate can be made of a polishing pad. In addition, if the anode assembly 104 is equipped to move vertically along the axis 134, the anode assembly can move vertically along the axis 134. In this second position, when the wafer 108 rotates and moves in the first direction 147, as the deposition process continues, the wafer 108 touches and rubs the forming plate 114. As shown in FIG. 11C, the planarization layer 182 can be formed by reducing the thickness of the deposited layer 180 on top of the insulating layer 172 to a minimum while the material is deposited on the structures 168 and 170 without being hindered.

If the polarity of the system is reversed, the system 100 can be used to remove material from the wafer surface in a consistent manner (electro-etching) instead of depositing material in a consistent manner. In this case, the electroplating electrolyte can be replaced by conventional electro-etching or electro-polishing solutions. The copper anode can be replaced by an inert electrode made of an inert material such as platinum, titanium or titanium-plated platinum material.

Of course, it is necessary to understand that the foregoing description is related to the preferred specific embodiments of the present invention, but modifications can be made without departing from the essence and scope of the present invention as stated in the following patent scope.

Symbol description of main components

10. . . Substrate

12. . . Insulator layer

14. . . Through hole

16. . . ditch

18. . . Barrier

20. . . Seed layer

twenty two. . . Conductive material layer

30. . . Electrodeposition system

32. . . Wafer

34. . . Wafer holder

36. . . Ring fixture

38. . . Electrical contact

40. . . Electroplating bath

42. . . Electroplating electrolyte

44. . . anode

46. . . shield

50. . . Electrodeposition system

51. . . top

52. . . bottom

53. . . Wafer carrier

54. . . Wafer

55. . . Carrier arm

56. . . anode

57. . . Anode cup

58. . . Holes

59. . . Peripheral sidewall

60. . . bottom

61. . . Upper edge frame

62. . . Electrolyte

63. . . Liquid inlet

64. . . Anode connector

65. . . front

66. . . Electrical contacts

67. . . Contact zone

68. . . Connector

69. . . back

70. . . Holding ring

71. . . Shaft

72. . . turn around

73-76. . . Sidewall

77. . . Concave edge

78. . . Side edge

79. . . District 1

80. . . Second district

81-82. . . arrow

82. . . shield

99. . . hole

100. . . Electrodeposition system

102. . . Upper part

104. . . Lower part

106. . . Wafer carrier

108. . . Wafer

110. . . Carrier arm

112. . . anode

114. . . Forming plate

116. . . Anode cup

118. . . Anode plate

119. . . Upper surface

120. . . Opening

121. . . Liquid inlet

122. . . arrow

124. . . Anode connector

126. . . Electrical contacts

128. . . Contact zone

129. . . Connector

130. . . back

131. . . lower surface

132. . . front

133. . . Holding ring

134. . . Shaft

135. . . turn around

136-142. . . Sidewall

144. . . Concave edge

146. . . Lateral edge

148. . . District 1

149. . . Second district

150. . . Inner wall

152. . . Top opening

154. . . Lower opening

156. . . Underside

157-158. . . Uneven area

159. . . hole

160. . . Electrolyte channel

162. . . Inner cavity

164. . . arrow

166. . . Surface part

168. . . Through hole structure

170. . . ditch

172. . . Insulator layer

174. . . Substrate

176. . . Active device location

178. . . Copper seed layer

180. . . Sedimentary layer

182. . . Planarization layer

264. . . arrow

Schematic description

1A is a schematic diagram of a semiconductor substrate. The semiconductor substrate has an isolation structure formed on the top surface of the substrate, wherein the isolation structure is etched to form trenches and through-hole structures in the substrate;

1B is a partial cross-sectional view of the substrate shown in FIG. 1A, in which the barrier layer and the seed layer are formed on each structure and the isolation layer or insulating layer;

FIG. 1C is a schematic diagram of the structure shown in FIG. 1B, in which the conventional contour layer is partially deposited on the seed layer;

Figure 1D is a schematic diagram of the structure shown in Figure 1C, in which the layer has been completely deposited;

FIG. 1E is a schematic diagram of the structure shown in FIG. 1D, in which a more planar layer has been formed;

Figure 2A is a schematic diagram of the prior art electrodeposition system;

Figure 2B is a schematic diagram of another prior art electrodeposition system using shielding;

Figure 3 is a schematic diagram of a specific embodiment of the system of the present invention, which is used to deposit conductive material on the entire surface of the wafer without excluding any edge regions;

4 is a schematic diagram of the system shown in FIG. 3, showing the position of electrical contacts and contact areas on the wafer relative to the width of the peripheral sidewall of the anode cup of the present invention;

Figure 5 is a partial plan view of the system shown in Figure 3, showing intermittent and continuous deposition areas on the wafer;

Fig. 6 is a schematic diagram of the system of the present invention shown in Fig. 3, including a shield provided between the anode and the cathode of the system;

7 is a schematic diagram of another embodiment of the system of the present invention, the system is used to deposit conductive material on the entire surface of the wafer without excluding any edge regions;

FIG. 8 is a partial schematic diagram of the system shown in FIG. 7, showing the wafer carrier assembly and forming plate of the present invention;

FIG. 9A is a plan view of a forming board with a wafer positioned on the forming board, where the wafer has continuous and intermittent deposition areas;

Figure 9B is a schematic cross-sectional view of the forming plate, showing continuous unevenness through the forming plate;

9C is a schematic diagram of another specific embodiment of the forming plate of the present invention, wherein the forming plate has two regions, which have different opening densities;

10A is a schematic side view of the electrodeposition system of the present invention, showing the position of the wafer electrical contact on the contact area relative to the width of the forming plate of the present invention;

10B is another schematic side view of the electrodeposition system of the present invention, showing the position of the wafer along the length of the forming plate of the present invention;

11A is a highly enlarged cross-sectional view of a wafer with a through hole and trench structure covered with a seed layer before the deposition method of the present invention;

FIG. 11B is a schematic diagram of the structure shown in FIG. 11A, in which the deposition layer has been electrodeposited according to the present invention; and

Fig. 11C is a schematic diagram of the structure shown in Fig. 11B, in which the deposition layer is deposited in a planar manner.