D/A conversion method and apparatus

Digital/analog conversion method and device

Technical field

The present invention relates to a digital/analog conversion method and device suitable for DMT (Discrete Multitone) systems, such as ADSL (Asynchronous Digital Subscriber Line) system and VDSL (Very High Frequency Digital Subscriber Line) system, or OFDM (Orthogonal Frequency) Divide the multiplexed transmission) system.

background

A well-known problem in digital/analog conversion is that the digital sampling points for digital/analog conversion often have a higher resolution (more bits) than the digital/analog converter used for conversion.

One solution to this problem is to simply ignore the least significant bit of the digital sampling point and use only the bits suitable for the digital/analog converter. Therefore, the sampling points are truncated before the actual digital/analog conversion. However, this method has the disadvantage of increasing the noise level of the generated analog signal, because this interception is equivalent to further digital signal quantization.

Another solution, described in [1] on the audio processing system, is to test whether the most significant bit is set to 0 at the sampling point. If so, shift this sampling point before digital/analog conversion. In this method, the least significant bit will be shifted to the conversion range of the digital/analog converter. After the digital/analog conversion, the generated analog signal is attenuated to a considerable degree to restore the correct signal level. However, as mentioned in [1], if this method is used on a sampling point with a sampling point basis, it will introduce distortion due to the transients generated during the attenuator transition between attenuated and non-attenuated states. In [1] this problem is achieved by requiring that a weak signal must exist for a certain period of time (predetermined number of sampling points) before the subsequent sampling points of translation and attenuation. This avoids switching back and forth too frequently between the two digital/analog conversion modes. However, the remaining mode conversions will still produce distortion when they occur because this mode conversion will become more frequent at higher digital/analog conversion rates, and this distortion will increase with the digital/analog conversion rate. Because the digital/analog conversion rate used in DMT (such as ADSL or xDSL) systems is at least one order higher than the digital/analog conversion rate used in audio signal processing, this method is not suitable for such applications.

Summary

The purpose of the present invention is to provide a digital/analog conversion method and device suitable for DMT systems, such as xDSL systems, for example, ADSL and VDSL systems, or OFDM systems, which use bit shifting/attenuation or similar technologies but avoid Or reduce the distortion caused by the transient state during the mode transition to a minimum.

This objective is achieved in accordance with the scope of the attached patent application.

Simply put, the exemplary embodiment of the present invention uses a guard time period (cyclic prefix) between frames to perform mode switching. If there is a sampling point with the highest intensity in a frame that needs to be shifted, shift the entire frame. Therefore, the mode conversion will only be performed at the border of the frame. This limits the transients to the protection time period, where they will not distort the useful signal.

A detailed description

Figure 1 is a block diagram of a typical DMT system, such as an ADSL system. A serial data string is divided into frames or symbols sent to the serial/parallel converter 10. The generated parallel data frame is sent to the encoder 12, which encodes the frame bits to a set of complex vectors. These complex vectors are understood as Fourier transform and sent to the inverse Fourier transform block 14. The result is an array of real sampling points. These sampling points are sent to the parallel/serial converter 16 to generate a serial sampling point array. A cyclic prefix adder 18 adds a predetermined number of the last sample points to the beginning of the array. The result is a string of serial real data frames, each providing a cyclic prefix. These frames are sent to the digital/analog converter 20. The generated analog signal is filtered and amplified in block 22, transmitted through channel 24, filtered by analog filter 26 at the receiving end, and then digitized by analog/digital conversion a28. In block 30, the loop prefix is removed. The remaining serial sampling points are converted in the serial/parallel converter 32 and processed in the Fourier conversion block 34. The generated complex Fourier coefficients are sent to the decoder 36, which retrieves the original symbols (frames). Finally, this symbol is converted into serial form in block 38.

The present invention is mainly related to digital/analog conversion and its result. As mentioned above, the sampling points sent to the digital/analog converter 20 often have a higher resolution (more bits) than the digital/analog converter processes. The traditional solution to this problem is to simply ignore the least significant bit of the digital sampling point and use only the bits suitable for the digital/analog converter. Therefore, the sampling points are truncated before the actual digital/analog conversion. However, this method has the disadvantage of increasing the noise level of the generated analog signal, because this interception is equivalent to further digital signal quantization. This will be interpreted as having to do with a hypothetical digital/analog converter with only 2-bit intensity resolution. Assume that the sampling point of the digital input signal has a resolution of 3 bits of intensity (assuming this sampling point is represented by 1 symbol bit and 3 intensity bits). Although the resolution of both is much smaller than the actual resolution (typical resolution is 12 bits for digital/analog converters and 14 bits for sampling points), it shows that the interception result at such a low resolution is The simpler.

Fig. 2 is a time representation diagram illustrating the original signal before interception. This figure illustrates the sampling points of two frames, each frame contains 16 sampling points. It is worth noting that the cyclic prefix is included in each frame and repeats the last 4 useful signal sampling points at the beginning of the frame. It is worth noting that the sampling point intensity has 8 possible values (3 bits). In fact, a frame contains more sampling points, for example, 512 sampling points at a sampling frequency of 2.208 MHz (MHz) plus 32 sampling points at the beginning of the cycle. The resolution is also higher, for example 13-14 bits.

FIG. 3 is a time representation diagram illustrating the interception of the digital signal generated by the digital/analog converter in FIG. 1. FIG. In this example, assume that the digital/analog converter has only 4 intensity levels (2 bits). From Figure 3, it is obvious that the result of ignoring (cutting) the least significant set element is the distortion of the signal. This distortion is particularly clear in frame 2, where all signal sampling points in this frame are very small.

The principles of the present invention will now be described in relation to Figures 4-6.

The simplest embodiment of the present invention is essentially based on 3 steps:

1. Determine the maximum sampling point intensity of a frame.

2. If the maximum intensity makes the most significant bit 0, all sampling points of this frame are shifted by one bit to double their intensity.

3. If the sampling point of a frame has been shifted, the part of the analog signal corresponding to this frame is attenuated by 50%.

Fig. 4 is a time chart of the digital signal of Fig. 1 after steps 1 and 2 are executed. It is worth noting that frame 1 is not affected, because its maximum intensity sets the most significant bit to 1. In the frame 2 of the original signal in FIG. 2, all the sampling points are under the dashed line indicating the boundary between the level with the most significant bit set to 1 and the level with the most significant bit set to 0. Therefore, all sampling points of this frame are shifted, as described in the right frame of FIG. 4.

Figure 5 is a time representation of the signal of Figure 4 after interception. It is worth noting that the untranslated left frame is exactly the same as frame 1 in Figure 3, which is expected because it has been processed in the same way. It is also worth noting that the second right frame whose sampling point has been shifted is not affected by interception. This can be understood by noting that the translation operation sets the least significant bit to 0 at all sampling points. Ignoring this bit will not change this sampling point. Then digital/analog converts the signal in Figure 5, and uses attenuation in the analog domain to restore the signal part intensity corresponding to the second frame.

Another method of looking at the present invention is illustrated in FIG. 6. FIG. 6 is a time block diagram of the "valid" digital signal corresponding to the signal of FIG. 2. FIG. This is a signal with intercepted sampling points in the first frame and unchanged sampling points in the second frame. If the signal is digitally/analogously converted in the digital/analog converter with the maximum intensity resolution (3 bits), this signal is obtained as if the digital/analog converter according to the present invention has only 2 bits of intensity resolution digital/ The analogy conversion of Figure 2 has the same result as the original signal. Obviously, it is more accurate to deal with weak signal frames than in traditional converters (compare Figure 3, 6 and Figure 2).

A basic feature of the present invention is that bit shift/attenuation is only performed on the entire frame. This allows the distortion transients generated by the mode conversion to occur during the cyclic prefix anyway later. However, although it is better to have a cyclic prefix, it is not absolutely necessary for the present invention. This basic feature is the protection time period that can accommodate transients. For example, such a protection time period can also be filled with zeros.

In the above description, it is assumed that only 1 bit is intercepted by the digital/analog converter. However, the number of bits that can be intercepted by a digital/analog converter is detectable. In such an instance, it is possible to determine different shifts and attenuations based on how many most significant bits are set to 0 at the sampling point of the frame. For example, if the 2 most significant bits of the intensity of all sampling points in a frame are all 0, this sampling point will be shifted by 2 bits and the analog signal will be reduced to 1/4. However, the translation/attenuation is still performed on a frame using the frame base.

FIG. 7 is a block diagram of an exemplary embodiment of the digital/analog converter according to the present invention. The sampling points from the cyclic prefix adder 18 are sent to a translation and intercept unit 50. For example, this unit may include a translation recorder. A control unit 52 also receives useful sampling points and determines the maximum intensity sampling point for each frame. According to the most significant bit of the value of the maximum optimal sampling point, the control unit 52 instructs the translation and interception unit 50 to shift or not to shift during the frame period. As mentioned above, a translation can span several bit positions. A frame period can be indicated by the frame end indicator from the cyclic prefix adder 18. Another possibility is to count the number of sampling points in the control unit 52 and reset the counter when a complete frame has been received (all frames are assumed to be of equal length). The possible translation and intercept signal sampling points are then sent to the digital/analog converter 20. After the digital/analog converter, the attenuator 54 controlled by the control unit 52 attenuates the analog signal part of the corresponding bit translation frame. If the system includes an amplifier as indicated in mention 1, a suitable embodiment is to integrate the attenuator in the amplifier and control the amplification instead.

For example, the function of the control unit 52 is provided by a microprocessor.

Other measurements besides the maximum intensity sampling point of the frame are also possible. For example, it is possible to determine whether the frame sampling point has a strength lower than a certain threshold with a certain ratio, such as 90%, to perform frame translation and interception. Another possible measurement is frame energy. Although these optional measurements may result in the reduction of some powerful sampling points, the overall results can still be improved.

FIG. 8 is a flowchart of an exemplary embodiment of the digital/analog conversion method according to the present invention. This embodiment can be implemented by the digital/analog converter in FIG. 7. Step S1 obtains the next frame. Step S2 determines the maximum sampling point intensity of the frame. Step S3 tests whether the maximum intensity is lower than a predetermined threshold. If yes, perform steps S4-S6. Step S4 Shift the sampling points in the frame. Step S5 is the translational sampling point of the digital/analog conversion frame. Step S6 attenuates the analog signal part corresponding to this frame. If the maximum occupancy does not fall below the threshold, the frame uses unchanged sampling points for digital/analog conversion. In these two examples, the procedure then returns to step S1 to process the next frame.

The embodiment of Figure 8 only includes a single threshold. However, several thresholds related to translation/attenuation are possible.

FIG. 9 is a block diagram of another exemplary embodiment of the digital/analog converter according to the present invention. This implementation is based on the observation that only sending the least significant bit to the digital/analog converter and detecting overflow in the frame is possible as an alternative. If overflow occurs, the frame sampling points are shifted to reduce the intensity, and compensation amplification is performed after the digital/analog conversion. Therefore, this embodiment is different from the embodiment of FIG. 7 where the control unit 52 detects overflow and the attenuator 54 is replaced by the amplifier 54A. If the system already includes an amplifier as indicated in Figure 1, this amplifier can be directly controlled instead of providing an independent amplifier 54A.

FIG. 10 is a flowchart of another exemplary embodiment of the digital/analog conversion method according to the present invention. This embodiment can be implemented using the digital/analog converter of FIG. 9. This embodiment is different from the embodiment of FIG. 8 in which step S3 is replaced by step S3A of detecting overflow. In addition, step S6 is replaced by a compensation amplification step S6A.

FIG. 11 is a block diagram of another exemplary embodiment of the digital/analog converter according to the present invention. This embodiment is a combination of the embodiments of FIGS. 7 and 9. If a frame is weak, its sampling points are shifted/attenuated, if it overflows, they shift in the opposite direction and zoom in. If the sampling point of the frame falls within the "window" between these extreme cases, the signal is converted to digital/analog without modification. In this embodiment, the control unit 52 tests whether the sampling point of the frame exceeds the boundary of the window, and if so, which one should be performed in this direction for translation and amplification or attenuation. In addition, the attenuator 54 of FIG. 7 is replaced by an amplifier/attenuator block 54B. If the system includes an amplifier as indicated in Figure 1, a suitable embodiment is an integrating amplifier/attenuator 54B at the end of the amplifier.

As an example to illustrate this embodiment, consider a sampling point of 14-bit intensity resolution and a 12-bit resolution digital/analog converter. From the point of view of the digital/analog converter, the most significant bit is assumed to be an "overflow bit", as shown in the embodiment in Figure 9, and the second most significant bit is used for weak frame detection, as shown in Figure 9. 7 examples. Therefore, if both bits are 0 for all sampling points of the frame, the frame should be shifted to increase its intensity and then attenuate. On the other hand, if the frame contains one or more sampling points with the most significant bit set to 1, this can be understood as overflow. In this example, the box is translated in the opposite direction and then zoomed in. If no frame sampling point has its most significant bit set to 1 and at least one sampling point has its second most significant bit set to 1, this frame is within the allowable "window" without modification.

FIG. 12 is a flowchart of another exemplary embodiment of the digital/analog conversion method according to the present invention. This embodiment can be implemented via the digital/analog converter of FIG. 11. This embodiment is different from the embodiment of FIG. 8 in which step S3 is replaced by step S3B of detecting whether the frame sampling point falls within the "window" or not. In addition, step S6 is replaced by a compensation amplification/attenuation step S6B.

Although the present invention has been explained about the ADSL system, it can be ascertained that it is suitable for any system based on the guard time between the sampling frame and the frame.

Various modifications and changes can be made in the present invention without departing from the field defined in the scope of the additional patent application, which can be understood by those familiar with the art.

references

[1] US Patent No. 4818996 (Kimura), Trustee: Yamaha Corporation (Yamaha Corporation)

The present invention, together with its further objects and advantages, can be used with reference to the following

The above description and drawings are best understood, here:

Figure 1 is a block diagram of a typical DMT system, such as an ADSL system;

Figure 2 is a time representation diagram illustrating a digital signal;

FIG. 3 is a time diagram illustrating the interception of the digital signal generated by the digital/analog converter in FIG. 1;

4 is a time representation of the digital signal after the first modification step of FIG. 1 according to the present invention;

Figure 5 is a signal time representation diagram after the interception of Figure 4;

Figure 6 is a time representation of the "valid" digital signal corresponding to the signal of Figure 1;

FIG. 7 is a block diagram of an exemplary embodiment of the digital/analog conversion method according to the present invention;

FIG. 8 is a flowchart of an exemplary embodiment of a digital/analog conversion method according to the present invention;

9 is a block diagram of another exemplary embodiment of the digital/analog conversion method according to the present invention;

10 is a flowchart of another exemplary embodiment of the digital/analog conversion method according to the present invention;

11 is a block diagram of another exemplary embodiment of the digital/analog conversion method according to the present invention; and

FIG. 12 is a flowchart of another exemplary embodiment of the digital/analog conversion method according to the present invention.