D/a conversion method and apparatus

SWEDEN <«) PATENT (13) C2 (11) 522 440 (19) SE (51)

International class ⁷

H03M 1/66, H04L 27/26

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PATENT AND REGISTRATION (45) (41) (22) (24) (62) (86) (86)

Patent filed Application widely available The patent application was submitted on expiration date

Tribal application number

2004-02-10

2001-08-01

2000-01-31

2000-01-31 (21) Patent Application Number 0000284-0

Application received as:

(83)

International filing day

Filing date for European patent application Deposit of microorganism Swedish patent application completed international patent application with number □ converted European patent application with number (30) Priority information (73) (72) (74) (54) (56) (57)

Assignee

INVENTOR

AGENT

NAME

Telefonaktiebolaget LM Ericsson (publ), 126 25 Stockholm SE

Daniel Strinnholm, Groth &amp; Co KB Converters

Bromma SE

QUOTES PUBLISHED: SUMMARY:

A system for D / A conversion comprises means (18) for arranging a stream of digital samples into frames, each frame comprising a protection period. Means (52) are provided for determining a measure of the total magnitude of digital samples in each frame. Means (50) increase the magnitude of all samples in frames of dimensions that fall below a predetermined threshold by shifting the samples to a common number of bits. A D / A converter converts frames with shifted and frames with non-shifted samples. An attenuator (54) attenuates the D / A transformed samples of shifted sample frames to compensate for the magnitude increase.

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The numbers in brackets indicate international identification code, INID code. Letters in clamps indicate international document code.

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SUMMARY

A system for D / A conversion comprises means (18) for arranging a stream of digital samples to frames, each frame comprising a protection period. Means (52) are provided for determining a measure of the total magnitude of digital samples in each frame. Means (50) increase the magnitude of all samples in frames of dimensions that fall below a predetermined threshold by shifting the samples to a common number of bits. A D / A converter converts frames with shifted and frames with non-shifted samples. An attenuator (54) attenuates the D / A transformed samples of shifted sample frames to compensate for the magnitude increase.

(Fig · 7)

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TECHNICAL FIELD

The invention relates to a method and apparatus for D / A conversion suitable for DMT (Discrete Multi Tone) systems, for example ADSL (Asymmetric Digital Subscriber Line) system and VDSL (Very high frequency Digital Subscriber Line) system, or OFDM (Orthogonal Frequency Division Multiplex) system.

BACKGROUND

A well-known problem in D / A conversion is that the digital samples to be D / A converted often have higher resolution (more bits) than the used D / A converter for conversion15.

One solution to this problem is to simply ignore the least significant bits of the digital samples and use only the bits contained in the D / A converter. Thus, the samples are truncated before the actual D / A conversion.

However, this method has the disadvantage that it increases the noise level of the resulting analog signal, since the truncation corresponds to further quantization of the digital signal.

Another solution, described in [1] with reference to audio processing systems, is testing whether the most significant bits of samples are added to

0th If so, the samples are shifted prior to D / A conversion. In this way, the least significant bits are shifted into the D / A converter's conversion range. After D / A conversion, the resulting analog signal is attenuated accordingly to reintroduce the correct signal level. However, as noted in [1], this method, if used sample by sample, will introduce distortion due to transients formed at the damper's switching between damping and non-damping states. In [1] this is mitigated

522 440 problems somewhat by requiring that a weak signal must exist for a certain period of time (predetermined number of samples) before subsequent samples are shifted and attenuated. This means avoiding too frequent switching back and forth between the two D / A conversion states. However, the remaining mode switches still cause distortion as they occur. This distortion increases with increased D / A conversion rate, as mode changes occur more frequently at higher D / A conversion rates. Since the D / A conversion rate is at least one order of magnitude higher for DMT (for example ADSL or xDSL) systems than for audio signal processing, this method is not suitable for such applications.

SUMMATION

It is an object of the invention to provide a method and apparatus for D / A conversion suitable for DMT systems, such as xDSL systems, such as ADSL and VDSL systems, or OFDM systems that use bit shifting or damping or similar techniques but avoiding or mitigating the distortion due to transients during mod changes to a minimum.

This object is achieved in accordance with the appended claims.

Briefly, a typical embodiment of the invention utilizes the protection time period (cyclic prefix) between frames to perform mode switches. If the sample with the largest magnitude in a frame needs to be changed, the entire frame is changed. Thus, mode switches are only performed at frame limits. This limits transients to the protection period, where they do not interfere with the utility signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further objects and advantages thereof, is best understood by reference to the following description in conjunction with the accompanying figures, in which:

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Fig. 1 is a block diagram of a typical DMT system, for example one

ADSL system;

Fig. 2 is a timing diagram illustrating a digital signal;

Fig. 3 is a timing diagram illustrating the truncation of the digital signal of Fig. 2 caused by a conventional D / A converter;

Fig. 4 is a timing diagram of the digital signal of Fig. 2 after a first modification step in accordance with the invention;

Fig. 5 is a timing diagram of the signal of Fig. 4 after truncation;

Fig. 6 is a timing diagram of an "effective" digital signal corresponding to the signal of Fig. 2;

Fig. 7 is a block diagram of a typical embodiment of the D / A converter according to the invention;

Fig. 8 is a flow chart of a typical embodiment of the D / A conversion method according to the invention;

Fig. 9 is a block diagram of another typical embodiment of the D / A converter according to the invention;

Fig. 10 is a flow chart of another typical embodiment of the D / A conversion method according to the invention;

Fig. 11 is a block diagram of yet another typical embodiment of

The D / A converter according to the invention; and

Fig. 12 is a flow chart of yet another typical embodiment of the D / A conversion method according to the invention.

DETAILED DESCRIPTION

Fig. 1 is a block diagram of a typical DMT system, for example an ADSL system. A serial data stream is divided into frames or symbols which are passed to a series / parallel converter 10. The resulting parallel data frame is passed to an encoder 12 which encodes the frame bits into a set of complex vectors. These complex vectors are interpreted as a Fourier transform and forwarded to a block 14 for inverted Fourier transform. The result is a set of real-value samples. These samples are forwarded to a parallel / serial converter 16 to form a set of serial samples. A cyclic prefix adder 18 adds a copy of a predetermined number of the last samples to the set wave. The result is a stream of serial real-value data frames, each with a cyclic prefix. These frames are forwarded to a D / A converter 20. The resulting analog signal is filtered and amplified in a block 22, transmitted through a channel 24, filtered on the opposite side in an analog filter 26, and then digitized in an A / D converter 28. The cyclic prefix is ​​removed in a block 30. The the remaining serial samples are converted into a series / parallel converter 32 and processed in a fourier transform block 34. The resulting complex fourier coefficients are passed to a decoder 36 which resets the original symbol (frame). Finally, this symbol is converted to serial form in a block 38.

The invention mainly relates to the D / A conversion and the consequences thereof. As noted above, the samples passed to a D / A converter often have higher resolution (more bits) than the D / A converter can process. The conventional solution to this problem is to simply ignore the least significant bits of the digital samples and use only the bits contained in the D / A converter. Thus, the samples are truncated before the actual D / A conversion. However, this method has the disadvantage that the noise level of the resulting analog signal increases, as this truncation corresponds to a further quantization of the digital signal. This will be explained with reference to a hypothetical D / A converter with only bits of magnitude resolution. The samples of the digital input signal are assumed to have bits of magnitude resolution (the samples are assumed to be represented by 1 character bit and 3 magnitude bits). Although both resolutions are much smaller than in practice (typically the D / A converter has 12 bit resolution and the samples 14 bit resolution), it is easier to illustrate the consequences of truncation at such low resolutions.

Fig. 2 is a timing diagram illustrating the original digital signal before truncation. The figure shows two frame samples, each frame consisting of 16 samples. It is noted that cyclic prefixes are included in each frame and repeat in

522 440 the bend of the frame the last 4 samples of the utility signal. It is noted that the sample magnitude can assume 8 possible values ​​(3 bits). In practice, a frame contains more samples, for example 512 samples at a sampling frequency of 2,208 MHz and a cyclic prefix of 32 samples. The resolution is also higher, for example 13-14 bits.

Fig. 3 is a timing diagram illustrating the truncation of the digital signal of Fig. 2 caused by a conventional D / A converter. In this case, it is assumed that the D / A converter has only 4 magnitude levels (2 bits). It is clear from Figure 3 that the result of ignoring (truncating) the least significant bit is a distortion of the signal. This distortion is particularly evident for frame 2, where all signal samples are small.

The principles of the invention will now be described with reference to Figures 4-6.

The simplest embodiment of the invention is essentially based on 3 steps:

1st Determine the maximum sample size of a frame.

2nd If this maximum magnitude is such that the most significant bit is 0, all of the frame's samples are shifted one bit to double their magnitude.

3rd If a frame's sample has been changed, that portion of the analog signal corresponding to the frame is attenuated by 50%.

Fig. 4 is a timing diagram of the digital signal of Fig. 2 after performing steps 1 and 2. It is noted that frame 1 is not affected since its maximum magnitude has the most significant bit set to 1. In frame 2 of the original signal in Figure 2, all samples are below the dashed line representing the boundary between levels whose most significant bit is set to 1 and levels whose most significant bit is set to O. Thus, all of the frames of this frame are shifted, as shown in the right frame of Fig. 4.

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Fig. 5 is a timing diagram of the signal of Fig. 4 after truncation. It is noted that the unshifted left frame is identical to frame 1 in Figure 3, which is to be expected since it has been treated in the same way. It is also noted that the second, right frame, whose sample has been changed, is not affected by the truncation. This can be understood by noting that the shifting procedure sets the least significant bit to 0 in all samples. Ignoring this bit will not change the samples. The signal of Figure 5 is then D / A converted, and the magnitude of the signal portion corresponding to the second frame is restored by attenuation in the analog domain.

Another way of looking at the invention is illustrated by Fig. 6. Fig. 6 is a timing diagram of an "effective" digital signal corresponding to the signal of Fig. 2. This is a signal in which the first frame has truncated samples, while the second the frame has unchanged samples. If this signal is converted D / A into a full-magnitude resolution (3-bit) D / A converter, the same result is obtained as if the original signal in FIG. 2 D / A converters according to the invention in a D / A converter with only 2 bits of magnitude resolution. Obviously, weak signal frames are processed more correctly than in the conventional converter (compare Figs. 3 and 6 with Fig. 2).

An essential feature of the invention is that shifting / damping of bits is performed only on whole frames. This allows the distorted transients formed by the mode switches to be below the cyclic prefix, which is nevertheless removed later. Although a cyclic prefix is ​​preferred, however, it is not absolutely necessary for the invention. The essential feature is a period of protection that accommodates the transients. Such a protection period may, for example, also be filled with zeros.

In the description above, it has been assumed that only 1 bit is truncated by the D / A converter. However, it will be appreciated that several bits can be truncated by the D / A converter. In such a case, it is possible to have different shifts and dampings, depending on how many of the most significant bits of a frame's sample are set to 0. If the 2 most significant bits of mag522,440 the nudity of all of a frame's sample are both 0, for example, the samples will be shifted 2 bits and the analog signal will decrease to 1/4. However, shifting / damping is still performed frame by frame.

Fig. 7 is a block diagram of a typical embodiment of the D / A converter in accordance with the invention. Samples from a cyclic prefix adder 18 are forwarded to a shift and truncation unit 50. This unit may include, for example, a shift register. A control unit 52 also receives the utility samples and determines the sample with maximum magnitude in each frame. Depending on the values ​​of the most significant bits of this sample with maximum magnitude, the controller 52 instructs the shift and truncation unit 50 to either shift or not shift while the frame lasts. As noted above, a shift can include multiple bit positions. The duration of a frame can be indicated by a frame end indicator from the cyclic prefix adder 18. Another possibility is to count the number of samples in the controller 52 and reset a counter when a full frame is received (all frames are assumed to be the same length). The possibly shifted and truncated signal samples are then forwarded to the D / A converter 20. After D / A conversion, attenuator 54 controlled by the controller 52 attenuates the analog signal portions corresponding to bit-shifted frames. If the system includes an amplifier, as shown in FIG. 1, a suitable embodiment is to integrate the damper into the amplifier and control the gain instead.

For example, the functionality of the controller 52 can be provided by a microprocessor.

Dimensions other than the sample with the maximum magnitude of a frame are also conceivable. For example, it is possible to determine that shifting / damping should be performed on a frame if the magnitude of a certain proportion, such as 90%, of a frame's sample is less than a certain threshold. Another possible measure is the frame energy. Although these alternative measures can cause a few strong samples to be truncated, overall performance can still be improved.

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Fig. 8 is a flow chart of a typical embodiment of the D / A conversion method according to the invention. This embodiment can be implemented through the D / A converter of Fig. 7. Step S1 fetches the next frame. Step S2 determines the maximum sample magnitude of the frame. Step S3 examines whether this maximum magnitude falls below a predetermined threshold value. If so, steps S4-S6 are performed. Step S4 shifts the frame's sample. Step S5 D / A converts the frame's shifted sample. Step S6 attenuates the analog signal portion corresponding to the frame. If the maximum magnitude does not fall below the threshold, the D / A transforms the frame with unchanged samples. In either case, the routine then returns to step S1 for processing the next frame.

The embodiment of Fig. 8 included only a single threshold. However, it is possible to have several thresholds associated with corresponding shifts / dampings.

Fig. 9 is a block diagram of another typical embodiment of the D / A converter according to the invention. This embodiment is based on the observation that it is also possible to forward the least significant bits to the D / A converter and detect "overflow" in a frame instead. If overflow occurs, the frame's sample is shifted to reduce the magnitude, and a compensatory gain is then performed after the D / A conversion. This embodiment thus differs from the embodiment of Fig. 7 in that controller 52 detects overcurrent and in that damper 54 is replaced by an amplifier 54A. If the system already contains an amplifier as indicated in Fig. 1, this amplifier can be controlled directly instead of providing a separate amplifier 54A.

Fig. 10 is a flow chart of another typical embodiment of the D / A conversion method according to the invention. This embodiment can be implemented through the D / A converter of Fig. 9. The embodiment differs from the embodiment of Fig. 8 by replacing step S3 with a step S3A which detects overcurrent. Furthermore, step S6 is replaced by a compensatory gain step S6A.

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Fig. 11 is a block diagram of yet another typical embodiment of the D / A converter in accordance with the invention. This embodiment is a combination of the embodiments of Figures 7 and 9. If a frame is weak, the samples are shifted / attenuated, if it flows, they are shifted in the opposite direction and reinforced. If the frame's sample falls within a "window" between these extreme cases, the D / A transforms the frame without modification. In this embodiment, controller 52 tests whether a frame's sample exceeds the window's boundaries, and if so, in which direction a shift should be performed and whether a gain or damping should be performed. In addition, the attenuator 54 of Fig. 7 is replaced by a reinforcement / attenuation block 54B. If the system includes an amplifier, as shown in Fig. 1, a suitable embodiment is to integrate the amplifier / attenuator 54B into this amplifier.

Consider as an example illustrating this embodiment a sample of 14 bit magnitude resolution and a 12 bit resolution D / A converter. From the perspective of the D / A converter, the most significant bit is assumed to be an "overflow bit," as in the embodiment of Fig. 9, and the second most significant bit is used for detection of weak frames, such as in the embodiment of Fig. 7. Thus, if both bits are 0 for all frames of the frame, the frame should be shifted to increase its magnitude and then attenuated. On the other hand, if the frame contains one or more samples with the most significant bit set to 1, it is interpreted as overflow. In this case, the frame is shifted in the opposite direction and then strengthened. If none of the frame's samples has their most significant bit set to 1 and at least 1 sample has their second most significant bit set to 1, the frame is within the allowed "window" and is not modified.

Fig. 12 is a flowchart of yet another embodiment of the D / A conversion method according to the invention. This embodiment can be implemented by the D / A converter of Fig. 11. The embodiment differs from the embodiment of Fig. 8 by replacing step S3 with a step S3B which

522 440 detects whether or not a frame's sample fits within a window. Furthermore, step S6 is replaced by a compensating gain / damping step S6B.

Although the invention has been explained with reference to an ADSL system, it will be appreciated that it is applicable to all systems based on sample frames and protection times between frames.

Those skilled in the art will recognize that various modifications and changes to the invention may be made without departing from the scope thereof, which is defined by the appended claims.

REFERENCE [1] US Patent No. 4,818,996 (Kimura), transferred to: Yamaha Corporation

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