Integrated circuit device with crossed power strap layout

Integrated circuit element and its manufacturing method and three-dimensional integrated circuit element

The present invention relates to an integrated circuit component and a manufacturing method thereof, and particularly relates to an integrated circuit component with bifurcated inner wiring.

Integrated circuits are used to form one or more components (ie, circuit components) on a semiconductor substrate through a manufacturing process. As the manufacturing process and materials improve, the size of the semiconductor device geometry has continued to shrink since it was first manufactured decades ago. For example, Circuit manufacturing processes have been able to produce component geometries smaller than 90 nm. However, the reduction of component geometries often creates many new challenges to be overcome.

When the size of electronic components is less than 90 nm, power efficiency and distribution become issues that affect component performance. The new integrated circuit has a plurality of conductor interconnection layers to provide electrical energy distribution to a plurality of microelectronic components. However, the current interconnection design of microelectronic products cannot achieve ideal component performance.

In view of this, the industry urgently needs to propose an integrated circuit device and method to solve the above-mentioned issues.

In view of this, one of the objectives of the present invention is to provide an integrated circuit device and a manufacturing method thereof to solve the above-mentioned problems.

To achieve the above objective, the present invention provides an integrated circuit device, including: a substrate; a plurality of microelectronic devices, each of the microelectronic devices includes a patterned feature (patterned feature) on the substrate, wherein the patterned feature (patterned feature) includes at least one electrical contact window; a plurality of interconnection layers are used to distribute electrical energy to the above-mentioned plurality of microelectronic components, the plurality of interconnection layers include a plurality of conductor members, and the plurality of conductor members and Each interconnection layer is connected, wherein at least one member of the interconnection layer formed subsequently diverges from at least one member of the interconnection layer adjacent to it; and a plurality of bonding pads and at least one of the above-mentioned plurality of interconnections Layer component connection.

To achieve the above objective, the present invention also provides a method for manufacturing an integrated circuit device, which includes: providing a substrate; forming a plurality of microelectronic devices, each of which includes a patterned feature on the substrate , Wherein the patterned feature includes at least one electrical contact window; a plurality of interconnection layers are formed for power distribution to the above-mentioned plurality of microelectronic components, and the plurality of interconnection layers include a plurality of conductor members , The plurality of conductor members are connected to each interconnection layer, wherein at least one member of the interconnection layer formed subsequently is diverged from at least one member of the interconnection layer adjacent to it; and a plurality of bonding pads and At least one component of the above-mentioned plurality of interconnection layers is connected.

To achieve the above objective, the present invention also provides a three-dimensional integrated circuit device, including: a substrate; a plurality of microelectronic element layers, each layer of the microelectronic element layer includes a plurality of microelectronic elements, and the plurality of interconnection layers are used So far, the electrical energy distribution of the plurality of microelectronic components; an intermediate interconnection layer includes a plurality of conductor interconnections for electrical contact with the microelectronic component layer; and a plurality of bonding pads and at least one of the above-mentioned plurality of microelectronic components The members of the layer are in contact.

The present disclosure relates to an integrated circuit device and its manufacturing method, and particularly relates to an integrated circuit device with bifurcated interconnections. These contents will be understood by the following many different embodiments and examples. The composition and arrangement of the following specific embodiments are intended to simplify the present invention, and are not intended to limit the present disclosure. In addition, the present disclosure will repeatedly use the same symbols and/or words in many examples. This is for the sake of simplification and clarity, and does not mean that there is a relationship between these embodiments and/or components.

FIG. 1 is a cross-sectional view for illustrating a microelectronic integrated circuit device sheet 100 according to an embodiment of the disclosure. The sheet 100 includes an interconnection space 110, a bonding layer 120, a device layer 140 and a substrate 105.

The interconnection space 110 includes a plurality of patterned conductor interconnection layers, and the interconnection layers are made of conductive material, such as Cu, Al, Mo, MoSi, Ni, NiSi, TiN, TaN, Ti, Ta, SiC, CoSi , WSi and/or other materials, and the interconnection layer can also be covered by low dielectric constant materials.

The bonding layer 120 includes a plurality of conductor pads 130, and the conductor pad 130 is surrounded by an insulating material, and the conductor pad 130 is a conductor material, such as Pt, Al, Cu, Ag, Au, Ni, Mo and/or other conductors The conductive pad 130 may also include a plurality of accessory patterned features to reduce the mechanical stress of the surrounding dielectric material. The accessory patterned feature may include a plurality of patterned features than the conductive pad 130. Smaller blocks, the number of conductor pads and the number of microelectronic components 150 in the bonding layer 120, the size of the chip (not shown), the smallest component feature size, the smallest component gate thickness, and/or other Component parameters are related, for example, the chip size can be between 4~100 mm²The number of microelectronic components is about 40-10 billion, and the minimum component feature thickness is about 3~800 angstroms. Therefore, the number of conductor pads 130 is determined by the integrated circuit component 100, among which the conductor pads The number of 130 is between 2 and 512.

The element layer 140 includes a plurality of microelectronic elements 150. The microelectronic elements 150 can be formed from, formed in, or on a common substrate, and the microelectronic elements 150 and the substrate 105 are similar in composition and manufacturing. Of course, the integrated circuit device 100 also includes other types of substrates 105 or composite substrates, which are all included in the scope of the present disclosure. In addition, each microelectronic element 150 includes at least one electrical contact window 160.

Each microelectronic component 150 may include one or more transistors, gates, electronically programmable read-only memory (EPROM) units, and electronically erasable read-only memory (Electrically Erasable Programmable Read Only Memory (EEPROM) unit, Static Random Access Memory (SRAM) unit, Dynamic Random Access Memory (DRAM) unit and/or other microelectronic components ( Collectively referred to as microelectronic components from now on).

The above-mentioned substrate 105 with a plurality of microelectronic elements 150 includes one or more layers of materials, structures or other features, which can be formed by conventional methods, such as immersion photolithography, maskless photolithography, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) and/or other process technologies. In addition, generally and/or future development of lithography, Etching and other processes can also be used to define the deposited layer to form the integrated circuit device 100.

The substrate 105 may be a silicon-on-insulator (SOI) substrate, and may include silicon, gallium arsenide, gallium nitride, strained silicon, silicon carbide, carbide, diamond, and/or other materials.

Please refer to FIG. 2, the layered interlaced strip interconnection structure 200 includes a component layer 140 and a plurality of interconnection layers 220, 230, 240, and 250. The interconnection layers 220, 230, and 240 include a plurality of conductor interconnections. Wiring bars 222, 232, and 242, and each conductor inner wiring bar 222, 232, and 242 includes a plurality of electrical contacts or via plugs 224, 234, and 244 to provide electrical contacts 160 and / Or the contact of the wire strips in other conductors. The conductor interconnecting bars 222, 232, and 242 can be formed in many patterns, such as rectangular, circular, or linear, but these patterns are not used to limit the patterns of the conductor interconnecting bars 222, 232, and 242. The conductor interconnect bars 222, 232, and 242 can provide electronic signals or electric energy (common electric energy) to a plurality of microelectronic components 150, and at least one of the conductor interconnect bars 222, 232, and 242 provides a ground potential V_ssAnd/or external power supply potential V_cc(Not shown), therefore, part of the conductor inner connecting strips 222, 232 and/or 242 can provide the ground potential V_ss, And other conductor inner connecting strips 222, 232 and/or 242 can provide electric energy supply potential V_ccIn addition, the conductor interconnect bars 222, 232, and/or 242 can also provide other internal or external electrical energy. The conductor interconnection bars 222, 232, and 242 can be directly located in the interconnection layers 220, 230, and 240. For example, the conductor interconnection bar 222 can be perpendicular to the conductor interconnection bar 232 and/or the conductor interconnection bar 242 The directions are the same, and each conductor interconnection bar 222, 232, and/or 242 can be in contact with the microelectronic component 150 and/or other conductor interconnection bars. In addition, the conductor interconnection strips 222, 232 and/or 242 can be electrically insulated by being surrounded by a dielectric material. This electrically insulating or dummy conductor interconnection strip can relieve stress and/or be used as a manufacturing process ( Such as chemical mechanical polishing) indicates the index of the completion of the process.

In other embodiments, for the ground potential V_ssAnd/or electric energy supply potential V_ccThe number of conductor pads 130 can be determined according to the structure of the conductor interconnect bars 222, 232, and 242 in the interconnect layers 220, 230, and 240. Therefore, V_ccThe number of conductor pads 130 and/or V_ssThe number of conductive pads 130 can be between 2 and 512, and the ground potential V is increased_ssAnd/or electric energy supply potential V_ccThe number of conductive pads 130 can reduce leakage and noise, and the smallest feature of the microelectronic device 150 is between 1500-3 angstroms.

In an embodiment, the interconnection layer 220 includes a plurality of conductor interconnection bars 222, and the conductor interconnection bars 222 are connected to the electrical contact 160 of each semiconductor element 150 through the interlayer plug 224. The connection In Figure 2 it is represented by a dashed line 226. In addition, the conductor interconnection strips 222 can be alternately connected to the microelectronic components 150, or divergently connected to a plurality of microelectronic components 150, such as the conductor interconnection strips 222 alternately. When the ground is connected to the microelectronic component 150, the connection can be horizontal and/or diagonal to the plane of the component layer 140, that is, the via plugs 224 are alternately connected to the contact windows 160 located on the microelectronic component 150, where There may be 2, 3, 4, 8, 24, 32, 64 and/or other numbers of interposer plugs 224 in each conductor interconnection bar 222, and the width of the conductor interconnection bar 222 is about 1600 ~5 Angstroms.

In one embodiment, the interconnection layer 230 includes a plurality of conductor interconnection bars 232, and the conductor interconnection bars 232 are electrically connected to the conductor interconnection bars 222 through the interlayer plugs 234, and this connection is in the second The figure is represented by a dashed line 236. In addition, the conductor interconnection bar 232 can be alternately connected to the conductor interconnection bar 222, and can also be divergently connected to a plurality of microelectronic components 150 and/or the conductor interconnection bar 222 For example, the conductor interconnection bar 232 can be alternately connected to the microelectronic component 150 and/or the conductor interconnection bar 222, this connection can be in a horizontal and/or diagonal relationship with the plane of the interconnection layer 230, that is to say, The layer plugs 234 can be alternately connected to the conductor interconnecting strips 222, wherein the interposer 234 in each conductor interconnecting strip 232 can have 2, 3, 4, 8, 24, 32, 64 and/ Or other numbers, and the width of the connecting strip 232 in the conductor is about 1800-5 angstroms.

In one embodiment, the interconnection layer 240 includes a plurality of conductor interconnection bars 242. The conductor interconnection bars 242 are connected to the conductor interconnection bars 232 and/or the conductor interconnection bars 222 via the interposer 244. Electrical connection. This connection is represented by the dashed line 246 in Figure 2. In addition, the conductor interconnection strip 242 can be alternately connected to the conductor interconnection strip 232, and can also be divergently connected to a plurality of microelectronic components 150 and /Or the conductor interconnection strips 222 and 232 are connected. For example, the conductor interconnection strip 242 can be alternately connected to the microelectronic component 150 and/or the conductor interconnection strips 222 and 232, and this connection can be connected to the interconnection layer 240 The plane is in a horizontal and/or diagonal relationship, that is, the interposer plugs 244 can be alternately connected to the conductor interconnection bars 232 and/or 222, wherein the interposer plug 244 in the conductor interconnection bar 242 is in each conductor. There may be 2, 3, 4, 8, 24, 32, 64, and/or other numbers, and the width of the interconnecting strip 242 within the conductor is about 2000-5 angstroms.

In one embodiment, the interconnect layer 250 includes a plurality of V_ssPad 252 and V_ccThe pad 254 is electrically connected to the conductor interconnection bar 242 and/or 232, 222, and this connection is indicated by the dashed lines 256 and 258 in FIG. 2.

FIG. 3 shows another embodiment of a layered wavy cross-strip interconnect structure 300, which includes a component layer 140 and a plurality of interconnect layers 320, 330, 340, and 350.

The configuration of the structure 300 is similar to that of the structure 200, except that the interconnection layers 320, 330, and/or 340 may include a plurality of wavy conductor interconnection bars 310, and the wavy conductor interconnection bar 310 includes interconnections. , The composition of the V pattern and/or recess is related to the depth of the integrated circuit device 100, and the wavy conductor interconnection bar 310 can provide a higher density of interlayer plugs 320 to 322, further increasing the size of the chip Can be reduced.

The plurality of interconnection layers 320, 330, 340, and 350 in the structure 300 also have the function of electrical connection. For example, in the interconnection layer 340, each via plug 344 can be connected to the via plugs 334f~334g In the interconnection layer 330, the interposer 334 can be connected to the interposer plugs 324a~324g, and the electrical connection between the interconnection layer 320 and the component layer 140 can use the interposer 324a~324g and The contact windows 160a to 160g are connected, and a plurality of 324d to 324e are connected to the contact windows 160d to 160e.

Figure 4 is one of the cross-sectional views of the integrated circuit component 400, and it combines the microelectronic component 150 with the conductor interconnecting strips 322, 332, and 342. For example, the integrated circuit component 400 includes a plurality of microelectronic components 150. One or more of the microelectronic components 150 are roughly similar, and the substrate 105 may include one or more uniform or complementary doping wells 402. In this embodiment, it is not limited to any specific dopants or combinations, and the doping wells 402 Boron can be used as the p-type dopant and the deuterium boron compound as the n-type dopant. The deuterium-boron compound can be formed by plasma treatment of a boron-doped diamond layer containing deuterium plasma.

In one embodiment, the doping well 402 can be formed by using a high-density plasma source. The high-density plasma source has a carbon to deuterium ratio of 0.1 to 5% in a vacuum environment, and the boron can be doped by mixing boron and carbon. /Hydrogen supply, where boron-containing gas can include B₂H₆, B₂D₆And/or other boron-containing gases, and the boron doping concentration can be adjusted during the process according to the amount of boron-containing gas. The atmospheric pressure of the process is 0.1 mTorr~500 Torr, and the temperature of the substrate 105 can be maintained between 150~1100°C. High-density plasma can be generated by microwave electron cyclotron resonance (ECR) plasma, spiral wave plasma, inductively coupled plasma and/or other high-density plasma sources, such as ECR plasma 800~2500 watts of microwave energy.

As mentioned above, the doped well 402 also includes an n-type deuterium-boron compound region in the substrate 105. This compound region can be formed into a deuterium-boron doped region in the boron-doped region by the above-mentioned deuterium plasma. Or other types of masks cover the selected substrate 105 to expose the boron-doped area, and then use a plasma containing deuterium to treat the boron-doped area, where deuterium ions can terminate the dangling bonds to make p-type boron doped The zone is transformed into an n-type deuterium boron compound zone. In addition, deuterium can be replaced by tritium, hydrogen, and/or other hydrogen-containing gases, and the concentration of the n-type region is generally controlled by the direct current (DC) or radio frequency (RF) bias of the substrate 105. The above process can still be used on the substrate 105. The lightly doped source/drain regions are formed. Of course, other general and/or future development processes can also be used to form the source/drain regions.

The integrated circuit element 400 also includes one or more insulating layers 420, 430 placed on the microelectronic element 150, and the first insulating layer 420, which may include multiple insulating layers, can be planarized to provide on a plurality of microelectronic elements 150 A flat surface.

The integrated circuit device 400 also includes vertical interconnects 440, such as general interposer plugs or contact windows, and horizontal interconnects 450 (the space description in the text is for illustrative reference only, and is not intended to limit the disclosure of the present invention. ), the interconnection line 440 may extend through one or more insulating layers 420, 430, and the interconnection line 450 may extend along the insulating layer 420, 430 or the trench. In one embodiment, one or more interconnection lines 440 , 450 has a dual damascene structure. The interconnections 440, 450 are formed as follows: first process the insulating layers 420, 430 by etching or other patterning processes, and then fill them with refractive and/or conductive materials, such as tantalum nitride , Copper and Aluminum.

Please refer to FIG. 5, which is a cross-sectional view of the integrated circuit 500 in the embodiment of the disclosure. 242 coexist. For example, the integrated circuit component 500 includes a plurality of microelectronic components 150, one or more of the microelectronic components 150 may be substantially similar, and the integrated circuit component 500 also includes a plurality of component layers 510 and 520, and this component layer 510 520 and 520 can be manufactured using a manufacturing method similar to the integrated circuit device 400 and/or 100, which is well-known to those skilled in the art, and the integrated circuit device 500 further includes a stacked layer 530.

The stacked layer 530 includes a plurality of intermediate interconnections 540 and a plurality of insulating layers 510 and 520.

The stacked layer 530 may include a low dielectric constant material such as SiO₂, SiN, SiC and/or other materials may also include silicon and/or semiconductor layers to provide a substrate for the insulating layer 520. For example, the stacked layer 530 may be formed by a metal-induced lateral crystallization (MILC) process , This MILC process can include porous SiO after forming an amorphous silicon layer₂Layer deposition, where a seed metal layer can be formed on porous SiO₂On the layer, the seed metal can form the side crystal of the amorphous silicon layer at a temperature of about 400~600°C. The metal seed layer can include nickel, cobalt, tungsten, titanium, tantalum, molybdenum and/or other materials After crystallization, it can be removed by plasma and/or chemical etching. The stacked layer 530 can still include a plurality of low-temperature polysilicon layers on the MILC crystalline layer, and can also include annealing treatment.

The intermediate interconnection 540 includes a plurality of conductor interconnections and/or conductor interconnection bars in contact with the element layers 510 and 520. In one embodiment, one or more intermediate interconnections 540 may have a dual damascene structure. The intermediate interconnection 540 is formed as follows: first process the stacked layer 530 by etching or other patterning processes, and then fill it with refractive and/or conductive materials, such as tantalum nitride, germanium, doped silicon, copper, and/or aluminum.

Although the present invention has disclosed the above preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this technique can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

<p>100Flake</p><p>105Base</p><p>110Internal Link Space</p><p>120Joint layer</p><p>130Conductor Pad</p><p>140Component layer</p><p>150Microelectronics</p><p>160,160a~160gelectric contact window</p><p>200Layered interlaced ribbon interconnection structure</p><p>220, 230, 240, 250Internal connection layer</p><p>222, 232, 242Conductor inner connecting strip</p><p>224, 234, 244, 322, 324a~324g, 334f~334gIntermediate plug</p><p>226, 236, 246, 256, 258Connect</p><p>252V_sspad</p><p>254V_ccpad</p><p>300Layered wavy cross strip inner connection structure</p><p>310Wave-shaped conductor inner connecting strip</p><p>320, 330, 340, 350Internal connection layer</p><p>400, 500Integrated circuit components</p><p>402Doping well</p><p>420,430Insulation layer</p><p>440Vertical internal connection</p><p>450Horizontal internal connection</p><p>510,520Component layer</p><p>530Stacked layers</p><p>540Intermediate connection</p>

FIG. 1 is a cross-sectional view for explaining the structure of the microelectronic integrated circuit device according to an embodiment of the disclosure.

FIG. 2 is a cross-sectional view for explaining the layered staggered ribbon interconnection structure according to an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view for explaining the layered staggered ribbon interconnection structure according to another embodiment of the present disclosure.

FIG. 4 is a cross-sectional view for explaining the structure of the integrated circuit device according to an embodiment of the disclosure.

FIG. 5 is a cross-sectional view for explaining the structure of the integrated circuit device according to another embodiment of the disclosure.