Sram device having high aspect ratio cell boundary

The present invention relates generally to static random access memory (SRAM), and more specifically to SRAM devices with high aspect ratio cell boundaries.

The physical size of the structure in the chip is called the "feature size". Reducing this machining dimension in chips allows more components to be built into each chip and more chips from each silicon wafer, resulting in one wafer and manufacturing cost per chip. Is reduced. Increasing the number of components in each chip can also improve chip performance because more components can meet functional requirements.

The SRAM device is a type of device capable of realizing such a reduction in manufacturing cost, and its structure and manufacturing method are disclosed, for example, in Patent Document 1. SRAM is a random access memory that keeps data bits in its memory as long as power is supplied. Unlike Dynamic Random Access Memory (DRAM), SRAM does not require periodic refreshes. In addition, SRAM can access data faster than DRAM. Thus, SRAM is often used, for example, in computer cache memory or as part of a video card's RAMDAC (Random Access Memory Digital Analog Converter).

However, SRAM is more expensive than other types of memory. For this reason, SRAM designers and manufacturers are constantly trying to reduce the cost of manufacturing SRAM devices. The above-mentioned reduction in processing dimensions is one of the means for realizing such cost reduction. However, reducing the machining dimensions is not the only means that can be taken to reduce the manufacturing cost of SRAM, for example, by changing the layout of the structure in the SRAM chip, the recording density of the SRAM cell in each chip. It is also possible to reduce the manufacturing cost by increasing the amount.

Therefore, in the technical field, an SRAM device capable of solving the above-mentioned problems and a manufacturing method thereof are required.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 10-199997</text></patcit>

<p> In view of the above, an object of the present invention is to provide an SRAM device capable of solving problems existing in the prior art.</p>

<p> That is, the present invention includes a substrate formed by interposing an n-doped region between the first and second p-doped regions, and a first pass gate located at least partially on the first p-doped region. A transistor, a first pull-down transistor, a first and second pull-up transistor located at least partially above the n-doped region, and a second pull-up transistor located at least partially above the second p-doped region. It consists of a SRAM unit cell including a passgate transistor, a second pull-down transistor, a first and second read port transistor, and the cell boundary of the SRAM unit cell has an aspect ratio of at least 3.2. For static random access memory (SRAM) devices that have primary and secondary dimensions.</p><p> A write port bit line electrically connected to the source / drain contact of the first passgate transistor, a write port inverted bit line electrically connected to the source / drain contact of the second passgate transistor, the first And a read port bit line that electrically connects to at least one of the source / drain contacts of the second read port transistor, a voltage source line that electrically connects to the source contact of the first and second pull-up transistors. In addition, the write port bit line, the write port inverting bit line, and the read include the drain contact of the second pull-down transistor and the ground wire electrically connected to the drain contact of the first read port transistor. The port bit line and the voltage source line are substantially perpendicular to the longitudinal axis of the boundary of the SRAM unit cell within the range created by the boundary of the SRAM unit cell, and the voltage source line is substantially perpendicular to the longitudinal axis. Is located between the write port bit line and the write port inverting bit line, and a part of the ground line is one of the write port bit line or the write port inverting bit line and the read port bit line. It is preferably located in between.</p><p> A write port that electrically connects to the gate contact of the first and second pass-gate transistors, and a read port that electrically connects to the gate contact of one of the first and second read port transistors. The write port word line and the read port word line further include a word line, and the write port word line and the read port word line are substantially parallel to the longitudinal axis of the boundary of the SRAM unit cell within the range created by the boundary of the SRAM unit cell. Is preferable.</p><p> A first transistor active region that is injected into the first p-doped region and extends between the source / drain contacts of the first passgate transistor and the first pull-down transistor, the second p-doped region. Injected into the region, the second transistor active region extending between the source / drain contacts of the second passgate transistor and the second pull-down transistor, and the second p-doped region. A third transistor active region extending between the source / drain contacts of the first and second read port transistors is further included, the first transistor active region and the second transistor active region. And, it is preferable that the third transistor active region extends substantially in parallel in the same direction.</p><p> It is preferable that the first basic dimension is smaller than 0.5 μm and the second basic dimension is larger than the first basic dimension.</p><p> At least one of the first and second passgate transistors and the first and second pull-down transistors is an NMOS transistor, and the active region of the NMOS transistor located in the first p-doped region and the second pull-down transistor. It is preferable that the active region of the NMOS transistor located in the p-doped region of the above n-doped region is separated by an interval of less than 70 nm.</p><p> Further, the present invention is located on a substrate formed by interposing an n-doped region between a first p-doped region and a second p-doped region, and at least partially on the first p-doped region. A first pull-down transistor and a first passgate transistor, at least partially on the n-doped region, first and second pull-up transistors, and at least partially on the second p-doped region. A first consisting of a second pull-down transistor located and a second, third, and fourth passgate transistor, and a SRAM unit cell including the first, such that the boundary of the SRAM unit cell has an aspect ratio of at least 3.5. And for static random access memory (SRAM) devices that have a second base dimension.</p><p> A first port bit line electrically connected to the source / drain contact of the first passgate transistor, a first port inverted bit line electrically connected to the source / drain contact of the second passgate transistor. , A second port bit line electrically connected to the source / drain contact of the third passgate transistor, a second port inverting bit electrically connected to the source / drain contact of the fourth passgate transistor. The first and second pull-up transistors further include a wire, a voltage source wire electrically connected to the source contact of the first and second pull-up transistors, and a ground wire connected to the drain contact of the second pull-down transistor. The longitudinal axis of the boundary of the SRAM unit cell within the range where the second port bit line, the first and second port inversion bit lines, and the voltage source line are created by the boundary of the SRAM unit cell. The voltage source line is located between the first port bit line and the first port inversion bit line, and a part of the ground line is the first. It is preferably located between one of the port bit line or the first port inversion bit line and one of the second port bit line or the second port inversion bit line.</p><p> A first portward wire that electrically connects to the gate contacts of the first and second passgate transistors, and a second that electrically connects to the gate contacts of the third and fourth passgate transistors. A port word line is further included, and within the range created by the boundary of the SRAM unit cell, the first and second port word lines are substantially both on the longitudinal axis of the boundary of the SRAM unit cell. It is preferably parallel.</p><p> Further, the present invention is located on a substrate formed by interposing an n-doped region between a first p-doped region and a second p-doped region, and at least partially on the first p-doped region. A first passgate transistor and a first pull-down transistor, at least partially on the n-doped region, first and second pull-up transistors, and at least partially on the second p-doped region. A second passgate transistor, a second pull-down transistor, a first and second read port transistor located, and the first passgate transistor and the first passgate transistor injected into the first p-doped region. The source / source of the second passgate transistor and the second pull-down transistor injected into the first transistor active region extending between the source / drain contacts of the pull-down transistor and the second p-doped region. A second transistor active region extending between the drain contacts and a second that is injected into the second p-doped region and extends between the source / drain contacts of the first and second read port transistors. It is composed of a SRAM unit cell including 3 transistor active regions, and the 1st transistor active region, the 2nd transistor active region, and the 3rd transistor active region are substantially parallel to each other. It relates to a static random access memory (SRAM) device extending in a direction and having first and second basic dimensions such that the boundary of the SRAM unit cell has an aspect ratio of at least 3.5.</p><p> A write port bit line electrically connected to the source / drain contact of the first passgate transistor, a write port inverted bit line electrically connected to the source / drain contact of the second passgate transistor, and the above. The read port bit line, which electrically connects to at least one of the source / drain contacts of the first and second read port transistors, further includes the write port bit line, the write port inverting bit line, and the read port bit. It is preferable that the lines are substantially perpendicular to the longitudinal axis of the boundary of the SRAM unit cell within the range created by the boundary of the SRAM unit cell.</p><p> A read port word wire electrically connected to the gate contact of the second read port transistor, a read port bit wire electrically connected to the source contact of the second read port transistor, and a read port bit wire of the first read port transistor. Electrically connect to the gate contact and the gate electrode of the second pull-up transistor, and to the drain contact of the first read port transistor and the drain contact of the second pull-down transistor. It is preferable that the source of the first read port transistor and the drain of the second read port transistor are electrically connected by the third transistor active region, which further includes a ground wire.</p><p> A first wiring metal layer composed of a plurality of first wiring layers is further included, and the first wiring layer provides a source contact of the first passgate transistor and a drain contact of the first pull-up transistor. It is preferable to provide a first L-shaped wiring that is electrically connected to the gate contact of the second pull-up transistor.</p><p> The first wiring layer of the plurality of wires electrically connects the source contact of the second pass gate transistor and the drain contact of the second pull-up transistor to the gate contact of the first pull-up transistor. It is preferable to further provide 2 L-shaped wirings.</p><p> It is preferable that the n-doped region and the first and second p-doped regions are surrounded by a relatively deep n-doped region.</p>

<p> According to the present invention, it is possible to provide an SRAM device having a reduced manufacturing cost.</p>

The embodiments of the present invention can be well understood by reading the following detailed description together with the accompanying drawings. Please note that each structure is not shown in actual size according to common sense in the industry. The dimensions of each structure can be expanded or contracted as appropriate to make the description easier to understand.

It should be understood that the following disclosure lists many different embodiments for the purpose of introducing the different features of the various embodiments. Examples of specific components and arrangements described below are provided to simplify the description of the present invention. Of course, these are just examples and do not make any restrictions. In addition, the terms and / or terms may be used repeatedly herein between different embodiments. However, such repetition is for the sake of simplicity and clarity of the description of the present invention, and does not determine the relationship between the above-described embodiments and / or configurations. Further, in the configuration described later in which the first structure is located on the upper surface (on) or above (over) of the second structure, the first and second structures are formed in direct contact with each other. Even if an implementation is included, it may include a form in which additional structures are formed between the first and second structures without direct contact of the first and second structures. ..

FIG. 1 is a layout diagram showing one embodiment of the SRAM device 100 configured based on the aspect of the present invention. The SRAM device 100 includes a substrate 105, an n-doping region 110, a p-doping region 115a, 115b, and SRAM unit cells 120a to i. In the figure, only the SRAM unit cell 120e is described, but each of the other SRAM unit cells 120a to d and f to i also has an active region 130a to e and a gate in the region surrounded by the unit cell boundary 125. It has electrodes 140a to e, respectively.

In one embodiment, the unit cell boundary 125 is shown as approximately intermediate between the components on the outer periphery of adjacent cells 120a-i. For example, in the illustrated embodiment, the upper cell boundary 125 (in the figure) is located approximately midway between the outermost edge of the gate electrode 140c of the cell 120e and the outermost edge of the gate electrode 140b of the cell 120d. The area formed by the unit cell boundary 125 may be proportional to one of the structures in each unit cell 120a to i. As an example, this area is about 500 (W)_GDP²) Can be less than this W_GDP²Is the width of the gate electrodes 140b, 140c or other structure.

Substrate 105 is silicon, gallium arsenide, gallium nitride, strained silicon. It can consist of silicon), silicon germanium, silicon carbide, carbide, diamond, and / or other materials. Further, the substrate 105 is a silicon on insulator (SOI) substrate such as a silicon on sapphire substrate, a silicon germanium on insulator, or another substrate having an epitaxial semiconductor layer on an insulating layer. It may consist of other insulators. In one embodiment, the substrate 105 may have an air gap for insulating the microelectronic elements formed on it. For example, a silicon-on-nothing (SON) structure can be employed to provide the substrate 105 with a thin insulating layer or gap composed of air and / or other insulators. In such an embodiment, the substrate 105 comprises a silicon cap layer above or above the silicon germanium layer. When this silicon germanium layer is removed wholly or partially, an air gap or void is created, resulting in a silicon cap as the active region of the device where microelectronic devices will later be formed. Layers are left.

The n-doped region 110 is formed in the substrate 105 by performing high-energy ion implantation through a patterned photoresist layer. The n-type dopant impurities used to form this n-doped region 110 include phosphorus, arsenic, P31, antimony, and / or other materials. Subsequent processes such as diffusion, annealing, and / or electrical activation may be performed after the injection of impurities is complete. The p-doped regions 115a and 115b can also be formed in the same manner, for example, although it may be necessary to reduce the energy level of the n-type dopant and the p-type dopant depending on their different atomic weights. P-type dopant impurities include boron, boron trifluoride, indium, and / or other materials. Similar to the formation of the n-doped region 110, the formation of the p-doped regions 115a, 115b may include one or more diffusion, annealing, and / or electrical activation processes. Also, within the scope of the present invention, doping designs other than the typical forms shown in FIG. 1 can be adopted. As an example, the n-doped region 110 is a p-doped well (p-doped). Well) or may be configured to include it, and the p-doped regions 115a and 115b may or may be n-doped wells, respectively. It may have been done. Further, these doped regions 110, 115a, and 115b can be doped with the same type of dopant, although the concentration of impurities is changed. Also, although not shown, all of the dope regions 110, 115a, 115b may be surrounded by one deep n or p well.

In one embodiment, boron is used as the p-type dopant and a deuterium-boron complex is used as the n-type dopant in the doped regions 110, 115a and 115b. The deuterium-boron complex can be formed by plasma treating the boron-doped diamond layer with deuterium plasma. In addition, deuterium can be replaced with tritium, hydrogen, and / or other hydrogen-containing gas. The impurity concentration in the dope region can be controlled by a direct current power supply or an RF (radio frequency) bias of the substrate 105. The process described above may be utilized to form a low concentration doped source / drain region and / or at least one active region 130a-e on the substrate 105.

The active regions 130a to e are portions of the dope regions 110, 115a, and 115b that are further divided, or predetermined portions thereof, or regions having an impurity concentration different from that of the dope regions in which the dope regions are present. However, in one embodiment, the active regions 130a to e can also be formed by first defining an oxide region on the substrate 105. This oxide region can be defined by and / or during the same steps performed to define the gate oxide layer corresponding to the gate electrodes 140a-e. Subsequently, the polysilicon layer may be formed by performing selective deposition or blanket deposition on the oxide region and then patterning. In such an embodiment, the polysilicon layer becomes part of the gate electrodes 140a-e. However, depending on the embodiment, it is not necessary to form the polysilicon layer. Further, the polysilicon layer can be subjected to a silicide process to form a silicide layer on the polysilicon layer. An example of silicide is TiSi₂, CoSi₂, NiSi₂, WSi₂And / or other materials suitable for silicidized gate wiring are included. Not all embodiments include a silicide layer, but when the silicide layer is used, the VDD layer forms part of the gate electrodes 140a to e.

In the active region 130a to e, for example, the energy is about 30 keV to 400 keV, and the impurity concentration is about 1 × 10.¹⁵atoms / cm²From 1x10¹⁷atoms / cm²The ion implantation process can also be performed. This ion implantation process may involve implanting ions so that the active regions 130a-e have a higher concentration than adjacent components, structures, or regions. Further, in the case of using the above-mentioned oxide region, polysilicon layer and / or VDD layer, the ion implantation process may be to implant ions into the region of the substrate 105 below them. By doing so, at least a part of the active regions 130a to 130e is formed on the substrate 105. On the other hand, in one embodiment, the entire active region 130a-e can be formed on or above the substrate 105. When the polysilicon layer and / or silicide layer described above is used, the ion implantation process for forming the active region 130a to e is performed either before or after the formation of the polysilicon layer and / or the silicide layer described above. You may. Additional and / or alternative processes can also be used to form active regions 130a-e. Further, in one embodiment, the resistance of the active regions 130a to e is about 1 kΩ to 100 kΩ. For example, the resistance of the active region 130a to e, or the resistance of the junction between the active region 130a to e and the adjacent component, structure or region can be about 3 kΩ.

The dopants used to form the active regions 130a-e are specified by the particular layout of the devices they form. As an example, if the active regions 130a-e form part of an NMOS transistor, the dopant is an n-type dopant, such as arsenic, P32, antimony and / or other n-type dopant. On the other hand, when the active regions 130a to 130 form a part of the MOSFET transistor, the dopant is a p-type dopant such as boron or BF.₂, Indium and / or other p-type dopants. In addition, in a single embodiment, different types of dopants can be injected into the active regions 130a-e. As shown in FIG. 1, the active regions 130a are formed in the p-doped region 115a, the active regions 130b and 130c are formed in the n-doped region 110, and the active regions 130d and 130e are formed in the p-doped region 115b. There is. In one embodiment, the active regions 130a and 130d are separated by an n-doped region at intervals of less than about 70 nm. The active regions 130a-130e are arranged so as to be substantially parallel to the longitudinal axes of the dope regions 110, 115a, 115b and extend beyond the boundary 125 of the particular SRAM unit cells 120a-i. ing. The width of one or more active regions 130a to e may be different from the width of the other active regions 130a to e. For example, the width of the active region 130e can be substantially wider than the other one or more active regions 130a-d. Further, in one embodiment, the active region 130e has a width sufficient to be shared by a plurality of transistor elements.

The gate electrodes 140a to 140e are patterned and / or selectively deposited, polysilicon, W, Ti, Ta, TiN, TaN, Hf, Mo, metal silicide, SiO.₂, Nitriding SiO₂, SiO_xN_y, WSi_x, V, Nb, MoSi_x, Cu, Al, carbon nanotubes, high-k dielectrics, alloys thereof, and / or other materials may be composed of one or more layers. Of these, Ta is a typical high-dielectric material.₂O₅, HfO₂, ZrO₂, HfSiON, HfSi_x, HfSi_xN_y, HfAlO₂, NiSi_xThere is. Such a layer may be configured to include a portion of the polysilicon and / or silicide layer described above. The manufacturing processes used to form the gate electrodes 140a-e include imprint lithography, immersion photolithography, maskless photography, chemical vapor deposition (CVD), plasma CVD (PECVD), atmospheric CVD ( APCVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and / or other processes are included. The process environment at the time of execution of these processes includes hydrogen (H) excited by plasma.₂) And carbon can be used. In addition, CH is used for such process gas.₄, C₂H₆, C₃H₈And / or other carbon-containing gases are included.

The gate electrodes 140a-e include a seed layer made of Ni, Cr, Nb, V, W and / or other materials formed by PVD, ALD, PECVD, APCVD and / or other process techniques and the like. May be good. Further, the gate electrodes 140a to 140a may include one or more gate dielectric layers, or may be formed on or above the upper surface of the gate dielectric film. Such a gate dielectric film is SiO₂, SiON, HfO, Ta₂O₅, Al₂O₃, Nitride oxides, CVD oxides, thermal oxides, nitrogen-containing derivative materials, high dielectric materials, and / or other materials, and formed by CVD, PECVD, PVD, ALD and / or other processes. be able to.

As shown in FIG. 1, the gate electrode 140a extends above the active region 130a and the gate electrode 140d extends above the active region 130d. Further, the one or more gate electrodes 140a to e may be shared gate electrodes extending over the plurality of active regions 130a to e so that they can be shared by a plurality of transistor elements. For example, the gate electrode 140b extends above the active regions 130a and 130b, and the gate electrode 140c extends above the active regions 130c and 130e. Further, since the active region 130e is configured to be shared by a plurality of transistor elements, the gate electrode 140e extends only above a single active region, that is, the active region 130e, but is plural. It is stretched in a form that can be shared by the transistor elements of. The gate electrodes 140a-e may extend beyond the boundary 125 of the particular SRAM unit cells 120a-i, whether or not they are configured as shared gate electrodes. Further, as shown in the illustrated form, the gate electrodes 140a to 140e may have a wide portion that is a position where a contact or via to be formed later can be formed, for example.

The cell boundaries 125 of each SRAM unit cell 120a to i can each have an aspect ratio greater than 3.2. This aspect ratio refers to the larger basic dimension (L in the illustrated embodiment) and the smaller basic dimension (W in the illustrated embodiment) of each cell 120a to i. It is a ratio. As an example, the SRAM unit cell 120e has a length L of about 0.32 μm to 8 μm, a width W of about 0.08 μm to 2 μm, and an aspect ratio of about 3 to 6. In another embodiment, the SRAM unit cell 120e may have a length L of about 12 nm to 80 nm and a width W of about 3 nm to 20 nm. Further, the aspect ratios of cells 120a to i can be set to about 3 to 6, and can be made different for each cell. In yet another embodiment, one, some or all of the cells 120a-i have an aspect ratio greater than 3.5.

FIG. 2 is a layout diagram of the SRAM device 100 in the next stage of FIG. 1, in which a first wiring metal layer is formed above each already formed structure. The metal layer may consist of one or more layers of aluminum, gold, copper, silver, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof and / or other materials. .. The metal layer can be formed by imprint lithography, immersion photolithography, maskless photography, CVD, PECVD, PVD, ALD and / or other processes, but is not limited to these. The metal layer can also be formed by performing a patterning process after performing selective deposition or blanket deposition. In one embodiment, the metal layer is formed by one or more processes described above with respect to the formation of the gate electrodes 140a-e and one described above with respect to the composition that can be taken for the gate electrodes 140a-e. Or it is made up of multiple materials.

The first wiring metal layer is a write port word line contact 210, a write port bit line contact 215, a first L-shaped wire 220, and a ground (Vss) contact 225. , Voltage source (Vcc) contacts 230 and 235, second L-shaped wiring 240, ground wire 245, write port word line contact 250, write port inverted bit line contact (write port bit-bar line contact) 255, read port bit It may consist of a read port bit line contact 260, as well as a read port word line contact 265. Of these, one or more wires (eg, wires 220, 240) can be formed in a substantially L-shape to connect wiring structures that are not aligned and arranged.

The SRAM device may also include contacts or vias (hereinafter collectively referred to as contacts) that extend between each component of the metal layer and the underlying structure. The contacts 270 can be formed by a process similar to that used to form the metal layer and may be formed prior to the formation of the metal layer. However, in one embodiment, the contacts 270 can also be formed by a damascene or dual damascene process as part of the process of forming the metal layer. When a large number of contacts 270 are pierced to the lower structure, the arrangement of a plurality of transistors included in the SRAM device 100 appears depending on the arrangement state of these contacts. The SRAM device in the illustrated embodiment has two passgate transistors (first passgate transistor PG-1 and second passgate transistor PG-2) and two pull-up transistors (first pull-up transistor). PU-1 and 2nd pull-up transistor PU-2), 2 pull-down transistors (1st pull-down transistor PD-1 and 2nd pull-down transistor PD-2), and 2 read port transistors (1st) It has a read port transistor RP-1 and a second read port transistor RP-2). Table 1 below lists examples of wiring connections of the corresponding transistor to the node, realized by the contact 270, based on the embodiment of FIG. Each column in Table 1 represents the presence of a contact 270 or other wiring structure.

<tables num="1"><img file="JP2005294849A_D0001.tif" /></tables>

It should be noted that the connection may be made between the wiring metal layer and the lower structure by inserting one or more contacts 270, or instead, another structure or component. Needless to say. Wiring configurations other than those shown in Table 1 are also included in the scope of the present invention. In addition, SRAM devices may have more or fewer transistors and / or contacts 270 than the illustrated embodiments.

FIG. 3 is a layout diagram of the SRAM device 100 in the next stage of FIG. 2 based on the aspect of the present invention, in which the second wiring metal layer is formed above the first wiring metal layer. In one embodiment, the second metal layer has substantially the same composition and manufacturing process as the first wiring metal layer described above.

The second wiring metal layer is a write port word line contact 310, Vss contact 315, write port bit line 320, voltage source line 325, write port inverting bit line 330, (second) ground line 335, read port bit line. It has a 340, a write port word line contact 345, and a read port word line contact 350. The SRAM device also has contacts 360 extending between each component of the first and second wiring metal layers. Thus, one or more contacts 360 (and many other contacts described herein) can, or include, a landing pad for receiving later formed contacts or vias. It consists of. In one embodiment, the contact 360 has substantially the same composition and manufacturing process as the contact 270 shown in FIG. Table 2 below lists examples of wiring connections between the first and second wiring metal layers realized by the contact 360. Each column in Table 2 represents the presence of a contact 360 or other wiring structure.

<tables num="2"><img file="JP2005294849A_D0002.tif" /></tables>

It should be noted that, in addition to or in place of one or more contacts 360, these connections are made between the first wiring metal layer and the second wiring metal layer via other structures or components. Needless to say, you can do so. Wiring configurations other than those shown in Table 2 are also included in the scope of the present invention.

FIG. 4 is a layout diagram showing the SRAM device 100 in the next stage of FIG. 3 based on the aspect of the present invention, in which the third wiring metal layer is formed above the second wiring metal layer. In one embodiment, the third wiring metal layer has substantially the same composition and manufacturing process as the first wiring metal layer described above.

The third wiring metal layer has a write port word line 410, a read port word line contact 450, and a (first) ground line 420. The SRAM device also includes a contact 430 that extends between each component of the second and third wiring metal layers. In one embodiment, the contact 430 has substantially the same composition and manufacturing process as the contact 270 shown in FIG. Table 3 below lists examples of wiring connections between the second and third wiring metal layers realized by the contact 430. Each column in Table 3 represents the presence of a contact 430 or other wiring structure.

<tables num="3"><img file="JP2005294849A_D0003.tif" /></tables>

It should be noted that, between the second wiring metal layer and the third wiring metal layer, in addition to one or more contacts 430, or in place of the contact 430, other structures or components are inserted to make these connections. Needless to say, you can do so. Wiring configurations other than those shown in Table 3 are also included in the scope of the present invention.

FIG. 5 is a layout diagram showing the SRAM device 100 in the next stage of FIG. 4 based on the aspect of the present invention, in which the fourth wiring metal layer is formed above the third wiring metal layer. In one embodiment, the fourth wiring metal layer has substantially the same composition and manufacturing process as the first metal layer described above.

The fourth wiring metal layer has a read port word wire 510 and a ground wire 520. The SRAM device also includes a contact 530 that extends between each component of the third and fourth wiring metal layers. In one embodiment, the contact 530 has substantially the same composition and manufacturing process as the contact 270 shown in FIG. Table 4 below lists examples of wiring connections between the third and fourth wiring metal layers realized by the contact 530. Each column in Table 4 represents the presence of a contact 530 or other wiring structure.

<tables num="4"><img file="JP2005294849A_D0004.tif" /></tables>

It should be noted that, between the third wiring metal layer and the fourth wiring metal layer, these wiring connections are made by inserting one or more contacts 530, or instead, other structures or components. It goes without saying that you may do it. Wiring configurations other than those shown in Table 4 are also included in the scope of the present invention.

After forming the structure shown in FIG. 5, the SRAM device 100 can be completed by a process that can be developed conventionally and / or in the future. For example, additional metal above the fourth wire metal layer shown in FIG. 5 to further connect the SRAM device 100 to other elements or components, including another SRAM device, on the same chip and / or wafer. Layers can also be formed. Further, in one embodiment, the SRAM memory array may be formed by repeatedly using the example in which the SRAM device 100 is formed.

The SRAM device 100 described above may include one or more interlayer dielectrics or other insulating layers interspersed with various conductor components. Such an insulating layer may itself be composed of a plurality of insulating layers and may be flattened to give a substantially flat surface for convenience in subsequent processes. This insulating layer is SiO₂, Fluoride glass (FSG), SiLK (registered trademark, manufactured by Dow Chemical Co., Ltd.), Black Diamond (registered trademark, manufactured by Applied Materials), and / or other insulating materials, and CVD, ALD, PVD, It can be formed by spin-on coating and / or other processes.

FIG. 6 is a circuit diagram illustrating one embodiment of the SRAM device 600 based on the aspect of the present invention. The SRAM device 600 is substantially the same as the SRAM device 100 shown in FIG. The SRAM device 600 includes pull-up transistors 610 and 615, pull-down transistors 620 and 625, passgate transistors 630 and 635, and read port transistors 640 and 645. In one embodiment, the pull-up transistors 610 and 615 are MOSFET transistors, while the pull-down transistors 620 and 625, passgate transistors 630 and 635 and read port transistors 640 and 645 are NMOS transistors. However, the configurations of other MIMO and MOSFETs also fall within the scope of the present invention.

The sources of the pull-up transistors 610 and 615 are electrically connected to the voltage source (hereinafter referred to as Vcc) 650. The drain of the pull-up transistor 610 is electrically connected to the source of the pass-gate transistor 630, the source of the pull-down transistor 620, and the gate of the pull-up transistor 615. Similarly, the drain of the pull-up transistor 615 is electrically connected to the source of the pass-gate transistor 635, the source of the pull-down transistor 625, and the gate of the pull-up transistor 610. The gate of the pull-up transistor 610 is electrically connected to the gate of the pull-down transistor 620. Similarly, the gate of the pull-up transistor 615 is electrically connected to the gate of the pull-down transistor 625 and is also electrically connected to the gate of the read port transistor 640.

The drains of the pull-down transistors 620, 625 are grounded or electrically connected to the Vss contact 655. The drain of the read port transistor 640 is electrically connected to the Vss contact 657.

The drains of the passgate transistors 630 and 635 are electrically connected to the write port bit line 660 and the write port inverting bit line 665, respectively. The gates of the passgate transistors 630 and 635 are electrically connected to the write port word line 670. The read port transistors 640 and 645 are connected between the Vss contact 657 and the read port bit line 675, and the gate of the read port transistor 645 is electrically connected to the read port word line 680. Write port bit lines 660, write port inverting bit lines 665, write port word lines 670, read port bit lines 675 and read port word lines 680 are row and column latches, decoders, select drivers, It may extend to other SRAM cells and / or components including control and logic circuits, sense amplifiers, multiplexers (muxers), buffers, and the like. In one embodiment, the maximum capacity of the write port storage node of the SRAM device 600 is less than about 0.6 farads.

FIG. 7 is a circuit diagram of the SRAM device 700 according to another embodiment of the present invention. This SRAM device 700 is substantially the same as the SRAM device 100 shown in FIG. The SRAM device 700 is also the SRAM device shown in FIG. 6, except that the transistor wiring for the input / output circuits has been changed and the passgate transistors 710 and 715 have been added in place of the read port transistors 640 and 645. Is substantially the same as.

In the embodiment of FIG. 7, the drain of the passgate transistor 630 is electrically connected to the first port bit line 720 and the drain of the passgate transistor 635 is electrically connected to the first port inverting bit line 725. There is. The passgate transistor 710 is electrically connected in series between the source of the pull-down transistor 620 and the second port bit line 730, and the gate of the passgate transistor 710 is electrically connected to the second portward line 740. ing. In the same way, the passgate transistor 715 is electrically connected in series between the source of the pull-down transistor 625 and the second port inverted bit line 735, and the gate of the passgate transistor 715 is the second port word line 740. Is electrically connected to.

FIG. 8 is a partial plan view of a wafer for manufacturing an SRAM device according to the aspect of the present invention. This wafer 800 can be used to manufacture the SRAM devices 100, 600 and / or 700 described above. The portion of the wafer 800 shown is composed of a dope region 810 having a first-type dopant and dope regions 820 and 830 having a second-type dopant. As an example, the doped region 810 is an n-doped region, and the doped regions 820 and 830 are p-doped regions. Each dope region 810 is interposed between the dope region 820 and the dope region 830. Two or more of these dope regions 810, 820 and 830 can be substantially parallel. In one embodiment, as shown in FIG. 8, all the dope regions 810, 820 and 830 are substantially parallel. The spacing between adjacent dope regions 830 can be from about 3 μm to 5 μm, and the spacing between adjacent dope regions 830 in one embodiment can be about 3.6 μm.

FIG. 8 also shows the configurations of SRAM unit cells 840 and 845 with increased recording densities. The longitudinal axes of these cells 840, 845 are substantially perpendicular to the longitudinal axes of the dope regions 810, 820 and 830. Also, cells 840, 845 have a common or substantially aligned longitudinal axis. In addition, each cell 840, 845 has a substantially equal length (L) or first primary dimension, a substantially equal width (W) or second primary dimension, And / or have substantially equal aspect ratios (L / W). In one embodiment, the aspect ratio of one or more cells 840, 845 is at least 3.2.

The SRAM unit cells 840, 845 are substantially similar to those shown in the SRAM devices 100, 600 and / or 700 described above. Cell 845 can be a cell in the form of mirror image or a rotation thereof with respect to cell 840. Since each of the cells 840 and 845 extends from a substantially intermediate position of the dope region 820 to a substantially intermediate position of the dope region 830, the cells 840 and 845 extend past the dope region 810. That is, each cell 840, 845 corresponds to the segment of the dope region 810 corresponding to the full width of the dope region 810, the segment of the dope region 820 corresponding to the partial width of the dope region 820, and the partial width of the dope region 830. It is composed of segments of the dope region 830. In one embodiment, the area of cells 840, 850 covering the dope region 830 is larger than the area covering the dope region 820, the former being about 1 to 5 times the latter.

As described above, the present invention discloses an SRAM device including a substrate and an SRAM unit cell. This substrate is formed by interposing an n-doping region between the first and second p-doping regions. The SRAM unit cell is then composed of (1) a first passgate transistor and a first pull-down transistor located at least partially on the first p-doped region, and (2) at least partially on the n-doped region. The first and second pull-up transistors located in, and (3) the second passgate transistor, the second pull-down transistor, the first and second, located at least partially on the second p-doped region. It includes a read port transistor. The boundaries of the SRAM unit cells are the first and second primary dimensions such that the aspect ratio is at least 3.2. dimension) has. In another SRAM device embodiment configured based on aspects of the invention, the SRAM unit cell further comprises third and fourth passgate transistors located at least partially above the second p-doped region. .. In one embodiment, the SRAM device of the present invention has a cell boundary having an aspect ratio of at least 3.5.

The present invention also includes (1) a first passgate transistor and a first pull-down transistor in which the SRAM unit cell is at least partially located on the first p-doped region, and (2) at least partially n-doped region. The first and second pull-up transistors located above and (3) the second passgate transistor located at least partially above the second p-doped region, the second pull-down transistor, the first and second It also provides a SRAM device with a read port transistor. Such an embodiment includes a first transistor active region that is injected into the first p-doped region and extends between the source / drain contacts of the first passgate transistor and the first pull-down transistor. Is done. In addition, it may include a second transistor active region that is injected into the second p-doped region and extends between the source / drain contacts of the second passgate transistor and the second pull-down transistor. Furthermore, it may include a third transistor active region that is injected into the second p-doped region and extends between the source / drain contacts of the first and second read port transistors. The first transistor active region, the second transistor active region, and the third transistor active region extend substantially in parallel in the same direction.

The features and technical advantages of the present invention have been described in detail above. The disclosure of the present invention can be readily utilized as the basis for changes or designs to other processes or structures made to achieve the same objectives and / or the same and advantages as those of the embodiments presented herein. , Should be understood by those skilled in the art. Those skilled in the art should be able to understand that such an equal configuration does not deviate from the spirit and scope of the present invention, and various types as long as they do not deviate from the spirit and scope of the present invention. Can be changed, replaced and changed.

<figref num="1">It is a layout drawing which shows one Embodiment of the SRAM device in the manufacturing intermediate stage by the aspect of this invention.</figref><figref num="2">It is a layout drawing which shows the embodiment in the next stage of the SRAM device in FIG.</figref><figref num="3">It is a layout drawing which shows the embodiment in the next stage of the SRAM device in FIG.</figref><figref num="4">FIG. 3 is a layout diagram showing an embodiment of the SRAM device in the next stage in FIG.</figref><figref num="5">FIG. 5 is a layout diagram showing an embodiment of the SRAM device in the next stage in FIG.</figref><figref num="6">It is a circuit diagram which shows another Embodiment of the SRAM device by the aspect of this invention.</figref><figref num="7">It is a circuit diagram which shows another embodiment of the SRAM device in FIG.</figref><figref num="8">It is a top view which shows a part of the wafer for manufacturing the SRAM device by the aspect of this invention.</figref>

Code description

100, 600, 700 SRAM device 105 Substrate 110 n Dope region 115a, 115b p Dope region 120a ~ i SRAM unit cell 125 Cell boundary 130a ~ e Transistor active region 140a ~ e Transistor gate electrode 210, 250, 310, 345 Write Port Ward Wire Contact 215 Write Port Bit Wire Contact 220, 240 L-Shaped Wiring 225, 315 Ground (Vss) Contact 230, 235 Voltage Source (Vcc) Contact 245, 335, 420, 520 Ground Wire 255 Write Port Inverted Bit Wire Contact 260 Read Port Bit Wire Contact 265, 350, 450 Read Port Word Wire Contact 270, 360, 430, 530 Via or Contact 320 Write Port Bit Wire 325 Voltage Source Line 330 Write Port Inverted Bit Wire 340 Read Port Bit Wire 410 Write Port Word Wire 510 read port word line 610, 615 Pull-up transistor 620, 625 Pull-down transistor 630, 635 Passgate transistor 640, 645 Read port transistor 650 Voltage source (Vcc) 655, 657 Ground (Vss) 660 Write port Bit line 665 Write port Invert bit line 670 Write port Word wire 675 Read port bit wire 680 Read port Word wire 710, 715 Passgate transistor 720 First port bit wire 725 First port inverted bit wire 730 Second port bit wire 735 Second port inverted bit wire 740 Second 2 Portward line 800 Doping area with type 1 dopant 810 Doping area with type 1 dopant 840, 850 Doping area with type 2 dopant 840, 850 SRAM unit cell L Length or first basic dimension (first) primary dimension W width or second primary dimension)