Non-volatile memory and method with bit line to bit line coupled compensation

Non-volatile memory with bit line to bit line coupling compensation and method

The present invention generally relates to non-volatile semiconductor memory, such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically relates to a page with adjacent rows for charge storage units Improve the memory of programming and sensing circuits.

Non-volatile storage of charge, especially solid-state memory in the form of EEPROM and flash EEPROM packaged as smaller form factor cards, has recently become a variety of mobile and handheld devices, especially information applications and consumer electronics products The preferred storage. Unlike RAM (random access memory), which is also a solid-state memory, the flash memory system is non-volatile, so it retains its stored data even after the power is turned off. Despite the high cost, flash memory is still increasingly used for mass storage applications. Traditional mass storage based on rotating magnetic media (such as hard disk drives and floppy disks) are not suitable for mobile and handheld environments. This is because disk drives tend to be bulky, tend to have mechanical failures, and have high latency and high power requirements. These undesirable features make disk-based storage impractical in most mobile and portable applications. On the other hand, embedded flash memory and flash memory in the form of a removable card are ideally suited for mobile and handheld environments due to their small size, low power consumption, high speed, and high reliability.

EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory, which can be erased and new data written or "programmed" into its memory unit. Both use floating (unconnected) conductive gates between the source region and the drain region, fixed in the channel region of the semiconductor substrate, and in the field-effect transistor structure. Then the control gate is provided on the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge held on the floating gate. In other words, for a given level of charge on the floating gate, there is a corresponding voltage (threshold voltage), which must be applied to the control gate before "turning on" the transistor to allow its source and drain regions Conduction between.

The floating gate can maintain the range of charge, and therefore can be programmed to any threshold voltage level in the threshold voltage window. The size of the threshold voltage window is defined by the minimum threshold level and the largest threshold level of the device corresponding to the range of charge programmable to the floating gate. The critical window generally depends on the characteristics, operating conditions, and history of the memory device. In principle, the different and distinguishable threshold voltage levels in the window can be used to specify the specific memory state of the cell.

The transistor used as a memory cell is usually programmed into a "programmed" state by one of two mechanisms. In "hot electron injection", a high voltage applied to the drain will accelerate the electrons across the substrate channel area. At the same time, the high voltage applied to the control gate drags the hot electrons to the floating gate through the thin gate dielectric. In "tunnel injection", a high voltage is applied to the control gate relative to the substrate. Using this method, electrons can be dragged from the substrate to the floating gate in the middle.

There are many mechanisms to erase the memory device. For EPROM, by using ultraviolet radiation to remove charge from the floating gate, a large amount of memory can be erased. For EEPROM, by applying a high voltage to the substrate with respect to the control gate, in order to induce the electrons in the floating gate to tunnel through the thin oxide and into the substrate channel area (ie Fowler-Nordheim tunneling), the electrical Sexually erase the memory unit. Generally speaking, EEPROM can be erased byte by byte. For a flash EEPROM, all the memory or one or more blocks can be erased electrically at one time, and one block can be composed of 512 bytes or more of the memory.

Memory devices usually include one or more memory chips that can be installed on a card. Each memory chip includes an array of memory cells supported by peripheral circuits such as decoders and erase, write, and read circuits. More complex memory devices also include a controller that performs smart and higher-level memory operations and connections. Many commercially successful non-volatile solid-state memory devices are in use today. The memory devices can use different types of memory cells, and each type has one or more charge storage units.

Figure 1 schematically illustrates a non-volatile memory cell in the form of an EEPROM cell. It has a charge storage unit in the form of a floating gate. Electrically erasable and programmable read-only memory (EEPROM) has a structure similar to EPROM, but it also provides a mechanism to electrically load and remove charges from its floating gate after applying an appropriate voltage without requiring Exposure to UV radiation. Examples of such units and methods of manufacturing such units are provided in U.S. Patent No. 5,595,924.

Figure 2 schematically illustrates a string of charge storage cells organized into a NAND cell or string. The NAND cell 50 is composed of a series of memory transistors M1, M2, ... Mn (n=4, 8, 16 or higher), and these transistor systems form a daisy chain with their source and drain. A pair of selection transistors S1 and S2 control the connection of the memory transistor chain to the outside via the source terminal 54 and the drain terminal 56 of the NAND cell. In the memory array, when the source selection transistor S1 is turned on by the signal SGS, the source terminal is coupled to the source line. Similarly, when the drain selection transistor S2 is turned on by the signal SGD, the drain terminal of the NAND cell is coupled with the bit line of the memory array. Each memory transistor in the chain has a charge storage unit to store a given amount of charge to represent the expected memory state. The channel region is between each source and drain of each memory transistor. The voltage on the control gate of each memory transistor (for example, 60, 62, 64) respectively controls the current conduction in the channels of the memory transistors M1, M2, ..., Mn. The selection transistors S1 and S2 provide control access to the NAND cell through its source terminal 54 and drain terminal 56 respectively, and each transistor is turned on by the appropriate voltage of its control gate.

When reading or confirming the address memory transistor in the NAND cell during programming, supply an appropriate reference voltage for its control gate. At the same time, by applying sufficient voltage V_PASSOn its control gate, the remaining non-addressed memory transistors in the NAND cell 50 can be fully turned on. Using this method, the conduction path from the source of the individual memory transistor to the source terminal 54 of the NAND cell is effectively established, and the conduction from the drain of the individual memory transistor to the drain terminal 56 of the cell is also established. path. Similarly, during the programming period, the memory transistor to be programmed makes its control gate supply to a programming voltage V_PGM, And other memory transistors in the string make it control the gate supply to pass the voltage V_PASS. Memory devices with such a NAND cell structure are described in US Patent Nos. 5,570,315, 5,903,495, and 6,046,935.

Another similar non-volatile memory has charge storage units in the form of dielectric layers. Instead of using the conductive floating gate element described above, a dielectric layer is used. This type of memory device using dielectric storage elements has been described by Eitan et al. in November 2000 in "NROM: Novel Partial Capture 2-bit Nonvolatile Memory Unit", IEEE Electronic Device Communications Vol. 21, No. 11 In pages 543 to 545. The ONO dielectric layer extends across the channel between the source diffusion and the drain diffusion. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for another data bit is localized in the dielectric layer adjacent to the source. For example, US Patent Nos. 5,768,192 and 6,011,725 disclose non-volatile memory cells with a capture dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by independently reading the binary state of the space-separated charge storage area in the dielectric.

<b>Memory array</b>

Memory devices generally include a two-dimensional array of memory cells arranged in columns and rows and addressable by word lines and bit lines.

FIG. 3 illustrates an example of a NAND cell array, such as the example shown in FIG. 2. Along each row of NAND cells, the bit line 36 is coupled to the drain terminal 56 of each NAND cell. Along each column of the NAND cell, the source line 34 can be connected to all its source terminals 54. In addition, the control gates 60,..., 64 of the NAND cells along a column are connected to a series of corresponding word lines. The connected word line uses a pair of select transistors (see FIG. 2) with appropriate voltages on the control gates SGD and SGS to turn on the pair of transistors, which can address the entire column of NAND cells. When the memory transistors in the chain of NAND cells are being read, the remaining memory transistors in the chain are hard-turned on through their associated word lines, so that the current flowing through the chain is essentially dependent on the memory transistors being stored in the chain. The level of charge in the read cell. Examples of the NAND architecture array and its operation as part of the memory system are found in US Patent Nos. 5,570,315, 5,774,397, and 6,046,935.

<b>Block erasure</b>

The programming of the charge storage memory device can only result in adding more charge to its charge storage element. Therefore, before the programming operation, the existing charge in the charge storage element must be removed (or erased). An erase circuit (not shown in the figure) is provided to erase one or more blocks of the memory cell. When the entire array of cells or a significant group of cells of the array (ie, in flash memory) is electrically erased together, the non-volatile memory (such as EEPROM) is called "flash" EEPROM. Once erased, the group of cells can be programmed again. The group of units that can be erased together can consist of one or more addressable erase units. Although more than one page can be programmed or read in a single operation, the erasure unit or block usually stores one or more pages of data, and the page is the unit of programming and reading. Each page usually stores one or more blocks of data, and the size of the erase block is defined by the host system. An example is an erase block of one of 512 bytes of user data, following the standard established by the drive, plus a certain number of bits of information about the burden of the user data and/or the block used to store the data Group. In other systems, the erase block size can be much larger than 512 bytes.

<b>Read/write circuit</b>

In a common two-state EEPROM cell, at least one current breakpoint level is established to divide the conduction window into two regions. When reading a cell by applying a predetermined, fixed voltage, the breakpoint level (or reference current I_REF) Compare and decompose its source/drain current into memory state. If the read current is higher than the breakpoint level or I_REFThe current determines that the cell is in a logic state (for example, "zero" state). On the other hand, if the current is less than the current at the breakpoint level, it is determined that the cell is in another logic state (for example, "1" state). Therefore, this binary unit stores one bit of digital information. Usually, an externally programmable reference current source is provided as a part of the memory system to generate the breakpoint level current.

As the state of semiconductor technology advances, in order to increase the memory capacity, higher and higher densities are being used to manufacture flash EEPROM devices. Another method for increasing the storage capacity is to make each memory cell store more than two states.

For multi-state or multi-bit quasi-EEPROM memory cells, the conductive window is divided into two or more regions by more than one break point, so that each cell can store more than one bit of data. The information that a given EEPROM array can store therefore increases with the number of states that each unit can store. US Patent No. 5,172,338 has described EEPROM or flash EEPROM with multi-state or multi-bit quasi memory cells.

In practice, when a reference voltage is applied to the control gate, the memory state of the cell is usually read by sensing the conduction current across the source electrode and the drain electrode of the cell. Therefore, for each given charge on the floating gate of the cell, the corresponding conduction current with respect to the fixed reference control gate voltage can be detected. Similarly, the range of charge programmable to the floating gate defines the corresponding threshold voltage window or the corresponding conduction current window.

Or, instead of detecting the conduction current in the divided current window, you can set the threshold voltage for a given memory state under test conditions in the control gate, and detect whether the conduction current is lower or higher than the threshold Current. In one embodiment, the detection of the conduction current relative to the critical current is accomplished by checking the rate at which the conduction current is discharging through the capacitance of the bit line.

<b>Factors affecting read/write performance and accuracy</b>

In order to improve reading and programming performance, multiple charge storage elements or memory transistors in an array are read or programmed side by side. So read or program the logical "pages" of the memory components together. In the existing memory architecture, a row usually contains several interleaved pages. All memory elements of a page will be read or programmed together. The row decoder will selectively connect each page of the interleaved page with a corresponding number of read/write modules. For example, in one embodiment, the memory array is designed to have a page size of 532 bytes (512 bytes plus 20 burden bytes). If each row contains one drain bit line and each column has two interleaved pages, then there are a total of 8512 rows, and each page is associated with 4256 rows. There will be 4256 connectable sensing modules to read or write all even bit lines or odd bit lines in parallel. Using this method, a page of 4256 bits (ie, 532 bytes) of side-by-side data is read from or programmed into the page of the memory device. The read/write module forming the read/write circuit 170 can be configured into various structures.

As described above, conventional memory devices improve read/write operations by operating in a large number of parallel manners. This method can improve performance, but has an impact on the accuracy of read and write operations.

Another issue that must be dealt with is bit line-to-bit line coupling or crosstalk. In the case of parallel sensing of closely spaced bit lines, this problem becomes more acute. The traditional method to avoid bit line-to-bit crosstalk is to sense all even bit lines or all odd bit lines while grounding other bit lines. This structure of one column consisting of two interleaved pages will help avoid bit line crosstalk and alleviate the problem of densely matching read/write circuits for this page. The page decoder is used to multiplex the set of read/write modules into even or odd pages. With this method, whenever a group of bit lines is read or programmed, the interleaved group can be grounded to eliminate the crosstalk between the odd-numbered bit lines and the even-numbered bit lines, but the odd-numbered or even-numbered lines cannot be eliminated. Crosstalk between.

However, the interleaved page architecture is disadvantageous in at least three aspects. First, it requires additional multiplexing circuits. Secondly, its performance is low. In order to complete the reading or programming of memory cells connected by word lines or in a row, a second reading operation or a second programming operation is required. Third, it is not optimal in handling other interference effects. For example, when two adjacent charge storage elements are programmed at different times (for example, independently in odd and even pages), the one at the floating gate level Wait for the field coupling between adjacent charge storage elements.

When the spacing between memory transistors is closer, the problem of adjacent field coupling becomes more obvious. In the memory transistor, the charge storage unit is clamped between the channel area and the control gate. The current flowing through the channel area is a function of the resultant electric field contributed by the control gate and the electric field in the charge storage unit. With increasing density, memory transistors are formed closer and closer together. Then the electric field from the adjacent charge element becomes an important contributor to the combined electric field of the affected cell. The adjacent electric field depends on the charge programmed into the adjacent charge storage unit. The perturbing electric field is dynamic because it changes with the programmed state of the adjacent charge storage cells. Therefore, the reading of the affected cell at different times may be different, depending on the change state of the adjacent charge storage cells.

The traditional structure of interleaved pages exacerbates errors caused by the coupling of adjacent charge storage cells. Because even and odd pages are programmed and read independently of each other, a page can be programmed under a set of conditions and read back under a set of completely different conditions, depending on what happens to the interleaved pages at the same time. Reading errors will become more serious as the density increases, requiring more precise read operations and wider division of the critical window for polymorphic implementations. Performance will be affected, and the potential capacity in polymorphic implementations will be limited.

US Patent Application Nos. 10/254483 and 10/254290 filed on September 24, 2002 disclose a memory architecture in which a page of adjacent memory storage cells is programmed or read in parallel. Because the programming is performed on a page of the adjacent memory storage unit, the memory storage unit that has been programmed to its target state will be programmatically prohibited or blocked from further programming during processing. In a preferred solution, the memory storage unit is blocked by floating its channel and increasing the voltage therein to prohibit programming. This increased voltage creates significant disturbances on adjacent storage cells that are still under programmed conditions.

Therefore, high-performance and high-capacity non-volatile memory is generally required. In particular, there is a need for a high-capacity non-volatile memory with improved reading and programming performance that can effectively deal with the above-mentioned problems.

By having a larger page of the read/write circuit to read and write the corresponding page of the memory cell in parallel, the requirements for high-capacity and high-performance non-volatile memory devices can be met. In particular, the interference effects inherent in high-density chip integration that may introduce errors into reading and programming can be eliminated or minimized.

When programming the adjacent pages of a storage unit, every time the storage unit has reached its target state and gets program prohibition or blockade from further programming, it will create a disturbance on the adjacent storage unit that is still under programming conditions. The present invention provides a part of a programming circuit and method in which a disturbance offset is added to adjacent storage units still under programming conditions. The offset is added by the program prohibiting the controlled coupling between the neighboring bit lines of the storage cell and the neighboring bit lines of the storage cell still under programming conditions. Using this method, the inherent errors in parallel programmed high-density memory storage units can be eliminated or minimized.

According to a preferred embodiment, the storage unit enters the program prohibition mode by floating the channel of the storage unit and increasing its voltage to the program prohibition voltage. This must increase its bit line voltage to enable floating. For a certain part of this voltage rise, the adjacent bit line of the storage cell that is still under the programmed condition is floated, so as to couple the predetermined offset with its own bit line. With this method, under the condition of controlled bit line-to-bit line coupling, the offset can automatically track and compensate for the disturbance caused by the program-forbidden storage unit to the storage unit still under the programmed condition.

According to another specific embodiment, the channel increase for program prohibition is performed before the coupling offset.

According to another aspect of the present invention, the bit line of the storage unit still under the programming condition is set to: whenever two of its adjacent storage units are still under the programming condition, the programming efficiency can be maximized The potential. In a preferred embodiment, the bit line is set to ground potential. This avoids any coupling from adjacent storage cells, which may have their voltage increased by adjacent storage cells under program prohibition conditions.

Additional features and advantages of the present invention will be understood from the following description of the preferred embodiments of the present invention, which description should be combined with the accompanying drawings.

<b>All bit threaded</b>

Preferably, a memory architecture configured to perform all bit line sensing is used to implement the sensing module 380 shown in FIGS. 4A, 4B, and 12. In other words, adjacent memory cells in a row can be connected to a sensing module to perform sensing in parallel. This type of memory architecture is also disclosed in the co-pending and co-assigned U.S. Patent Application No. 10/254,483 filed by Cernea et al. on September 24, 2002, and its name is "Very small non-volatile Sexual memory and its methods". The entire disclosure of the patent application is incorporated herein by reference.

As explained above, the number of memory cells in a "page" that can be programmed or read at the same time may vary depending on the size of the data sent or requested by the host system. Therefore, there are several methods to program memory cells coupled with a single word line, such as (1) independently program even-numbered bit lines and odd-numbered bit lines, the programming can include page up programming and down page programming , (2) Programming all bit lines ("All bit threading"), or (3) independently programming all bit lines in the left or right page, the programming can include the right page programming And the left page is stylized.

4A schematically illustrates a memory device according to an embodiment of the present invention, which has a read/write circuit for reading and programming a page of memory cells in parallel. The memory device includes a two-dimensional array of memory cells 300, a control circuit 310, and a read/write circuit 370. The memory array 300 can be addressed through the word lines through the column decoder 330 and through the bit lines through the row decoder 360. The read/write circuit 370 includes a plurality of sensing modules 380, and allows a page of memory cells to be read and programmed in parallel.

In the present invention, the page of memory cells to be read or programmed in parallel is preferably adjacent to the memory storage cell or a row of storage cells. In other embodiments, the page is a section adjacent to a memory storage unit or a row of storage units.

The control circuit 310 cooperates with the read/write circuit 370 to perform memory operations on the memory array 300. The control circuit 310 includes a state machine 312, an on-chip address decoder 314, and a power control module 316. The state machine 312 provides chip level control for memory operations. The on-chip address decoder 314 provides an address interface between the hardware address used by the host or the memory controller to the hardware address used by the decoder 330 and the circuit 370. The power control module 316 controls the power and voltage supplied to the word lines and bit lines during memory operation.

FIG. 4B illustrates a preferred configuration of the memory device shown in FIG. 4A. The access by each peripheral circuit of the array is implemented in a symmetrical manner on opposite sides of the memory array 300, so that the density of access lines and circuits on each side can be halved. Therefore, the column decoder is divided into column decoders 330A and 330B, and the row decoder is divided into row decoders 360A and 360B. Similarly, the read/write circuit is divided into a read/write circuit 370A connected to the bit line from the bottom of the array 300, and a read/write circuit 370B connected to the bit line from the top of the array 300 . With this method, the density of the read/write module is substantially halved, and therefore the density of the sensing module 380 is halved.

<b>Boost voltage on channel and charge storage unit</b>

The inherent errors in high-density integrated circuits and non-volatile memory devices are caused by the coupling between adjacent charge storage units and the channel area. If the channel area and charge storage unit of a memory storage unit are added to a neighboring memory storage unit, this will cause disturbances on the charge storage unit of the neighboring unit. This effect is more obvious when the memory storage cells that are being programmed in parallel are densely packaged or insufficiently shielded.

5A illustrates a cross-sectional perspective view of the memory transistors along the direction 5A-5A shown in FIG. 2 and the equivalent capacitances between the charge storage unit and the word line, and between the charge unit and the channel. The memory transistor M1 has a control gate 60 formed as a part of a word line extending along a column of the NAND array 100 (see FIG. 3). In this figure, the drain electrode protrudes from the page of FIG. 5A and the source electrode is behind, thereby defining the channel area 80 between the two. The charge storage unit 70 is inserted between the control gate 60 and the channel 80, and the unit is insulated from the two by a layer of dielectric material. With equivalent capacitor C_WF, The electrical coupling between the charge storage unit 70 and the control gate 60 can be simulated. Similarly, with the equivalent capacitor C_FC, The coupling between the charge storage unit 70 and the control gate 80 can be simulated.

FIG. 5B schematically illustrates the capacitive coupling of the memory transistor shown in FIG. 5A, thereby specifically displaying the voltage in the charge storage unit due to the voltage in the channel and the voltage in the word line. If the charge storage unit 70 is storing Q amount of charge, then C_WFAnd C_FCBoth maintain the same charge. Voltage V in charge storage unit 70_CS=(C_WF V_W+C_WF V_C)/(C_WF+C_FC). It can be easily seen that the voltage of the charge storage unit generally increases with increasing voltage in the channel and/or word line. In the next section, it will be explained that when the memory transistor such as M1 is placed in the program inhibit mode, the channel voltage can be increased to a high voltage. Therefore, this will also lead to an increased voltage in the charge storage unit. The combination of the increased voltage in the channel 80 and the charge storage unit 70 will have a disturbing effect on the adjacent memory transistors connected in a programmed mode.

<b>Programmatic overshoot due to the increase of neighboring units in the (program prohibited) state</b>

FIG. 6A illustrates a cross-sectional perspective view of the NAND cell array shown in FIG. 3 when the two adjacent memory transistor systems are in the programming mode. For example, FIG. 6A may show three adjacent memory transistors, such as M1-1, M1-2, and M1-3, which belong to NAND strings 50-1, 50-2, and 50 along a column that share the same word line 60, respectively. -3. The NAND strings 50-1, 50-2, and 50-3 have bit lines 36-1, 36-2, and 36-3 connectable to them, respectively. The memory transistors M1-1, M1-2, and M1-3 have corresponding charge storage units 70-1, 70-2, and 70-3, and channels 80-1, 80-2, and 80-3.

As the density of the memory array increases, the memory transistors are formed closer together, and their effects on each other will become more significant. For example, the threshold voltage of the memory transistor M1-2 depends on the voltage on the charge storage unit 70-2. Because its neighbors M1-1 and M1-3 are in close proximity, the voltage in the channels and charge storage cells of M1-1 and M1-3 can affect the voltage on the charge storage cells of M1-2. For example, the charge storage unit 70-2 can be regarded as having an equivalent capacitor C₁₂And C₂₃They are respectively coupled to its neighboring charge storage units 70-1 and 70-3. Similarly, the charge storage unit 70-2 can be regarded as having an equivalent capacitor C'₁₂And C'₂₃Coupled to its adjacent channels 80-1 and 80-3, respectively. The closer the spacing between memory transistors, the more coupling between them.

FIG. 6A illustrates the situation when the two adjacent memory transistors M1-2 and M1-1 are both in the programming mode. Focusing on the effect on M1-2 due to M1-1, there is a small change due to the word line and bit line voltages, because these voltages are the same for M1-2 and M1-1. The channel voltage is similar. The only change seen by the charge storage unit 70-2 is due to the change of the charge storage unit 70-1, and the only change is mainly a function of the charge held by the charge storage unit 70-2 or its data representation. For example, the voltage on the charge storage units of M1-1 and M1-2 may be about 1 to 2 V. The disturbance caused by this type of disturbance is usually solved by allowing a sufficient margin between two different memory states.

6B illustrates a cross-sectional perspective view of the NAND array similar to that of FIG. 6A, except that one of the adjacent memory transistors is in the program inhibit mode. In this case, program M1-2 and prohibit M1-1 from further programming. The word line voltage remains the same for both, and the voltage on the bit line 36-1 of M1-1 has now become V_DD, Which is the predetermined system voltage, for example ~2.5 V. This can effectively turn off the select transistor S2 (see Figure 2), disconnect the NAND chain 50-1 from its bit line 36-1, and float the channel 80-1 of M1-1, so that when a high voltage appears on the word line The channel can be capacitively increased to a high voltage when it is above 60. For example, this method can increase channel 80-1 of M1-1 to 10 V. Increasing the channel voltage will effectively reduce the potential difference between the channel and the charge storage unit, thereby preventing the drag of electrons from the channel to the charge storage unit to affect programming.

According to the discussion above in connection with FIG. 5B, adding channels will result in increasing charge storage units. For example, when the memory transistor M1-1 is in the program inhibit mode, it can cause a voltage increase of approximately 10 V in the channel 80-1 and an increase in the voltage from 2 V to 8 V in the charge storage unit 70-1. This can greatly disturb the adjacent memory transistors (such as M1-2) to be programmed. For example, the charge storage unit 70-2 of M1-2 can increase its voltage by V₂~0.2 V. This is because of its charge storage unit 70-2, which will (for example) capacitor C₁₂And C'₁₂It is capacitively coupled with the charge storage unit 70-1 and the channel 80-1 of the memory transistor M1-1 (program prohibition). Generally speaking, programming the threshold voltage of the memory transistor with a step difference between 0.8 V and about 0.1 V or less will cause M1-2 to be incorrectly programmed to be higher than the desired threshold.

So far, the discussion has focused on the effect of M1-1 on the memory transistor M1-2. If M1-3 is also in the program inhibit mode, its increased voltage will be coupled in a similar manner to contribute to the increase of the voltage on the charge storage unit 70-2 of M1-2. In the worst case where the memory transistor M1-2 is in the programming mode, and its neighbors M1-1 and M1-3 on either side are blocked from further programming (program prohibition), M1-2 The perturbation on the charge storage unit 70-2 can be as high as 0.2 V. For M1-2 under programmed conditions, this effect is equivalent to increasing the programmed voltage of up to 0.4 V on its control gate. In some cases this can cause over-programming of the error state. For example, a memory cell can divide its critical window with a separation of approximately 0.3 V, and increase the programmed pulse segment difference by approximately 0.1 V each time, so that it usually takes more than one pulse to traverse each segment. The current programming pulse segment difference can make M1-2 just below the critical area indicating the required programming state. At the same time, the current pulse step difference can program the transistors M1-1 and M1-3 to their final state, so that the transistors can be blocked from further programming by entering the program inhibit mode. Therefore, in the next programmed pulse step difference, M1-2 suddenly suffers a larger programmed step difference of up to 0.5 V. This will likely cause M1-2 to overshoot the required critical area and be incorrectly programmed into the next memory state.

<b>Automatic compensation for interference caused by the increase of the neighbor's voltage</b>

FIG. 7 illustrates a bit line-to-bit line coupling mechanism according to a preferred embodiment of the present invention, which is used to compensate for the disturbance of adjacent memory transistors in the self-program inhibit mode.

Using the same example as in FIG. 6B, the memory transistor M1-2 is programmed, and the adjacent transistor M1-1 is prohibited from further programming. As indicated in the above description, increasing the channel 80-1 and charge storage unit 70-1 of M1-1 will cause the voltage in the charge storage unit 70-2 of M1-2 to increase by ΔV₂, Which leads to stylized errors.

According to a preferred embodiment, the disturbance ΔV in the charge storage unit 70-2 is compensated by introducing a similar amount of charge on the bit line 36-2₂. This bit line compensation voltage will be transferred to the channel so that the net change in the potential difference between the charge storage unit 70-2 and the channel 80-2 will effectively be zero. Using this method will eliminate any errors in the critical voltage. Use automatic compensation schemes. Whenever a memory transistor (such as M1-1) enters the program inhibit mode, its bit line 36-1 changes from 0 V to V_DD, So that the channel can be activated to float to reach the program prohibition increase. This increase in bit line voltage can be used to increase the voltage of an adjacent bit line (such as bit line 36-2) through capacitive coupling between two bit lines.

Fig. 7 schematically shows the capacitor C between the two bit lines 36-1 and 36-2_BL12Capacitive coupling. Similar capacitor C_BL23It exists between bit lines 36-2 and 36-3. When floating the bit line 36-2 used for the memory transistor M1-2, and increase the voltage on the adjacent bit line 36-1 by V₁Whenvia capacitor C_BL12Will increase the voltage αV₁(in<i>α</i>Is a coupling constant and has been estimated to be ~40% in a certain example) part of it is coupled to the bit line 36-2. This coupling voltage will be used as the error V in its charge storage unit 70-2₂OfOffset. Generally speaking, V₁Is the predetermined voltage so that the coupling part αV₁~V₂. As the bit line 36-1 (used for program blocking or forbidden memory transistor M1-1) changes from 0 V to V_DD, Floating bit line 36-2 (for the memory transistor M1-2 to be programmed) to use a predetermined αV₁coupling. Preferably, the voltage on the bit line 36-1 rises from 0 V to V_DD-V₁During the first period of, the bit line 36-2 is set to 0 V (non-floating). Then rise the final V on bit line 36-1₁In the second cycle, the floating bit line 36-2 adopts αV₁-V₂coupling. Using this method, for the memory transistor M1-2 (in the NAND chain 50-2) under the programmed conditions, whenever one of the adjacent transistors of the bit line 36-2 (for example, the NAND chain M1-1 in 50-1) enters the program prohibition mode, all compensate the bit line voltage to be equal to V₂OfOffset.

8(A) to 8(G) are timing diagrams according to the first embodiment of the present invention, which illustrate the voltage compensation scheme by capacitive bit line-to-bit line coupling during the programming operation. For the NAND chain under programming and programming prohibition conditions (see also FIG. 2 and FIG. 3), the voltage shown is applied to each word line and bit line of the memory array. The programming operation can be aggregated into the bit line precharge phase, programming phase and discharge phase.

In the bit line precharge phase:

(1) Turn off the source selection transistor from SGS in the case of 0 V (Figure 8(A)), and increase it from V to V_SGThe SGD turns on the drain select transistor (Figure 8(B)), so that the bit line can access the NAND chain.

(2) Make the program prohibit the bit line voltage of the NAND chain to increase (in the first step of the two-step rise) to V_DD-V₁Given a predetermined voltage (Figure 8(F)). At the same time, actively pull down the bit line voltage of the program NAND chain to 0 V (Figure 8(G)).

(3) In this cycle, the bit line voltage of the NAND chain continues to rise to V as the program prohibits_DD, The voltage change (in the second stage of the rise of the second stage difference) reaches V₁(Figure 8(F)). This will drop the gate voltage SGD on the drain selection transistor to V_DDWhen the program prohibits the NAND chain from floating. In the same cycle, if one of the neighbors of the programmed NAND chain is in the program inhibit mode, the bit line voltage of the programmed NAND chain can now be floated, and V can be used₂=αV₁Coupling (Figure 8(G)).

(4) The drain word line connected to the drain selection transistor in a column of the NAND chain causes its voltage to drop to V_DD. This will only the floating program prohibit the NAND chain, where its bit line voltage can be compared with V_DDIn comparison, the drain selection transistor has been turned off (Figure 8(B) and 8(F)). As for the NAND chain containing the memory transistor to be programmed, the drain selection transistor will not be turned off relative to the bit line voltage close to 0 V in the drain. In addition, as mentioned above, when the memory transistor system to be programmed is close to a transistor under the condition of program prohibition, its charge storage unit will adopt V due to the increase of channels and charge storage units of neighbors.₂coupling.

(5) The memory transistor in the unaddressed NAND chain makes its control gate voltage set to V_PASS, To close it completely (Figure 8(C)). Because the NAND chain is prohibited in the floating program, the high V applied to the unaddressed memory transistor_PASSAnd V_PGMIncrease the voltage in its channels and charge storage components, thereby prohibiting programming. Usually relative to V_PGM(E.g. ~15 to 24 V) and V_PASSSet to some intermediate voltage (for example ~10 V). For the chain being banned by the program, V_PASSHelps reduce the use of higher voltage V_PGMEffective V_DS, Thereby helping to reduce leakage. For the chain being programmed, V_PASSIt should ideally be ground potential, so the middle V_PASSThe voltage will be a reasonable compromise.

In the stylized phase:

(6) Apply a programming voltage to the control gate of the memory transistor selected for programming (Figure 8(D)). Will not program the chain under program prohibition conditions (that is, add channels and charge storage units).

In the discharge phase:

(7) Make each control line and bit line dischargeable.

Basically, two types of increases will occur on the memory transistors to be programmed. The first type arises from adjacent memory transistors, which have floating channels and charge storage cells that are capacitively increased by the high control gate voltage from the word line. This occurs when the NAND chain enters the program inhibit mode. The first type of increase caused by the prohibition of the memory transistor from being programmed by the neighboring program will increase the voltage on the charge storage unit of the memory transistor to be programmed. This is an undesirable side effect that the program prohibits. The second type of increase is a compensatory adjustment to the bit line of the memory transistor to be programmed so as to offset the first type of increase. By floating the bit line during a certain period of increasing the voltage of the adjacent bit line, the bit line obtains an increase in voltage through capacitive coupling to offset the effect of the first boost.

In the first specific embodiment just described, the increase of the second compensation bit line occurs before the first boost. This provides possible V₁The maximum range. On the other hand, it also means that the bit line of the memory transistor to be programmed will be floated, and its voltage will easily be moved by the subsequent high programmed voltage. However, it has been estimated that the bit line capacitance is considerably larger than the channel capacitance. Therefore, when a high programming voltage appears on the control gate, even if the bit line is floated, the bit line and channel voltages will not change significantly.

Or according to the second specific embodiment, the first boost is started first, and then the second boost is started. With this method, any coupling with the floating bit line due to the high programming voltage can be minimized.

9(A) to 9(G) are timing diagrams according to the second embodiment of the present invention, which illustrate the voltage compensation scheme by capacitive bit line-to-bit line coupling during the programming operation.

Bit line precharge and phase increase:

(1) Turn off the source selection transistor by SGS at 0 V (Figure 9(A)), and increase from V to V_SGThe SGD turns on the drain select transistor (Figure 9(B)), so that the bit line can access the NAND chain.

(2) Increase the bit line voltage of the program forbidden NAND chain (in the first step of the rise of the two steps) to V_DD-V₁Given a predetermined voltage (Figure 9(F)). This predetermined voltage drops to V in SGD in (3)_DDIt is enough to cut off the drain of the NAND chain from its bit line, thereby floating the channel in it. At the same time, the bit line voltage of the program NAND chain is fixed at 0 V (Figure 9(G)).

(3) The drain word line connected to the SGD of the control gate of the drain selection transistor of the NAND chain makes its voltage drop to V_DD. This will only the floating program prohibit the NAND chain, where its drain selection transistor has been turned off, because its bit line voltage can be compared with V_DDCompare (Figure 9(B) and 9(F)). As for the NAND chain containing the memory transistor to be programmed, the drain selection transistor will not be turned off relative to the bit line voltage of 0 V in the drain.

(4) The memory transistor in the unaddressed NAND chain makes its control gate voltage set to V_PASS, To close it completely (Figure 9(C)). Because the NAND chain is prohibited in the floating program, the high V applied to the unaddressed memory transistor_PASSAnd V_PGMIncrease the voltage in its channels and charge storage components, thereby prohibiting programming.

In the stylized phase:

(5) In this cycle, the bit line voltage of the NAND chain continues to rise to V as the program prohibits_DD, The voltage change (in the second stage of the rise of the second stage difference) reaches V₁(Figure 9(F)). In the same cycle, if one of the neighbors of the programmed NAND chain is in the program inhibit mode, the bit line voltage of the programmed NAND chain can now be floated, and V can be used₂=αV₁Coupling (Figure 9(G)).

The programming voltage is applied to the control gate of the memory transistor selected for programming (Figure 9(D)). Will not program the chain under program prohibition conditions (that is, add channels and charge storage units).

In the discharge phase:

(6) Make each control line and bit line dischargeable.

FIG. 10 is a flowchart according to a preferred embodiment, which shows a page of programming adjacent memory storage units, while minimizing the occurrence of individual memory transistors that are program-banned or blocked among these units Coupling error method.

<b>All bit programming</b>

Step 400: For a page of adjacent memory storage cells, each cell has a charge storage unit between a control gate and a channel region defined by a source and a drain, providing a A bit line that is switchably coupled to the drain of each cell, and a word line that is coupled to all control gates of the page of the memory storage cell.

<b>Bit line precharge</b>

Step 410: Apply an initial, first predetermined voltage to the bit line of the specified memory cell of the page to be programmed.

Step 420: Apply an initial and second predetermined voltage to the bit line of the unspecified memory cell of the page to be program disabled.

Step 430: The floating program enables the bit line, and at the same time increases the program forbidden bit line from the second predetermined voltage to the third predetermined voltage by a predetermined voltage difference, wherein a predetermined part of the predetermined voltage difference is coupled to any adjacent, Floating, one of the program enable bit lines is shifted, and the third predetermined voltage enables each program to prohibit the floating of the channel of the memory storage unit.

<b>Programmable pulse, confirmation and prohibition</b>

Step 440: Apply a programmed voltage pulse to the word line to program the designated memory storage unit of the page, where the undesignated memory storage unit of the page is programmed by its floating channel added to the program prohibit voltage condition It is prohibited, and the disturbance caused by adding any adjacent program to activate the memory unit is compensated by the offset.

Step 450: Confirm the selected memory storage unit under the programmed condition.

Step 460: Re-designate any memory storage unit that has not been confirmed.

Step 470: Have all the memory storage units of the page been confirmed? If not confirmed, return to step 420. If it has been confirmed, proceed to step 480.

Step 480: End.

FIG. 11 is a flowchart according to another preferred embodiment, which shows a page of programming adjacent memory storage units, while minimizing the occurrence of individual memory transistors that are program-banned or blocked among these units The wrong way of coupling. This specific embodiment is similar to the specific embodiment shown in FIG. 10, but in the step for precharging using the disturbance offset, the step of adding channels is prior to the step of floating bit lines.

<b>Bit line precharge</b>

Step 410': Apply an initial, first predetermined voltage to the bit line of the designated memory cell of the page to be programmed.

Step 420': Apply an initial, second predetermined voltage to the bit line of the unspecified memory storage cell of the page to be disabled by the program, and the second predetermined voltage enables the bit line of each program to disable the memory storage cell and Floating of the channel.

Step 430': The floating program enables the bit line, and at the same time increases the program forbidden bit line from the second predetermined voltage to the third predetermined voltage by a predetermined voltage difference, wherein a predetermined part of the predetermined voltage difference is coupled to any adjacent One of the bit lines of, floating, and program activation is shifted, and the third predetermined voltage enables each program to prohibit the floating of the channel of the memory storage unit.

Figure 12 illustrates a preferred sensing module implementing various aspects of the present invention. The sensing module 380 includes a bit line isolation transistor 502, a bit line pull-down circuit 520, a bit line voltage clamp 610, a read bus transfer gate 530, and a sense amplifier 600.

A similar sensing module is disclosed in a jointly pending and jointly owned U.S. patent application under the name "Non-volatile memory and method with improved sensing", which is presented in this application by Adrian-Raul Cernea and Yan Li The application was filed on the same day as the case. The entire disclosure of the co-pending application is incorporated herein by reference.

Generally speaking, one page of memory cells is operated in parallel. Therefore, a corresponding number of sensing modules are operated in parallel. In a specific embodiment, the page controller 540 conveniently provides control and timing signals to the sensing modules operating in parallel.

When the bit line isolation transistor 520 is activated by the signal BLS, the sensing module 380 can be connected to the bit line 36 of the memory cell 10. The sensing module 380 senses the conduction current of the memory cell 10 through the sense amplifier 600, and uses the sensing node 501 to latch as the read result of the digital voltage level SEN2, and outputs the result to the read bus Row 532.

The sense amplifier 600 essentially includes a second voltage clamp 620, a precharge circuit 640, a discriminator or comparison circuit 650, and a latch 660. The discriminator circuit 650 includes a dedicated capacitor 652.

One feature of the sensing module 380 is to incorporate a constant voltage supply into the bit line during sensing. This is preferably implemented by the bit line voltage clamp 610. The bit line voltage clamp 610 operates like a diode clamp, and the transistor 612 is connected in series with the bit line 36. Bias its gate to a constant voltage BLC, which is equal to exceeding its critical voltage V_TThe required bit line voltage V_BL. Using this method, it isolates the bit line from the sensing node 501, and sets a constant voltage level for the bit line during programmed confirmation or reading, such as the required V_BL=0.5 to 0.7 volts. Generally, the bit line voltage level is set to one level so that it is low enough to avoid a long precharge time, and high enough to avoid ground noise and other factors.

The sense amplifier 600 senses the conduction current through the sensing node 501, and determines whether the conduction current is higher or lower than a predetermined value. The sensing amplifier uses the sensing node 501 to output the sensing result in digital form as the signal SEN2 to the reading bus 532.

The digital control signal INV, which is essentially the inverted state of the signal SEN2, is also output to control the pull-down circuit 520. When the sensed conduction current is higher than the predetermined value, INV will be high and SEN2 will be low. This result is enhanced by the pull-down circuit 520. The pull-down circuit 520 includes an n-transistor 522 controlled by a control signal INV, and another n-transistor 550 controlled by a control signal GRS. When the GRS signal goes low regardless of the state of the INV signal, the GRS signal basically allows the bit line 36 to float. During the programming period, the GRS signal goes high so that the bit line 36 can be pulled down to ground. When a floating bit line is needed, the GRS signal will go low.

8(H) to 8(O) illustrate the timing of the preferred sensing module shown in FIG. 12 related to the features of the present invention. The detailed description of the operation of the better sensing module with other invention features has been explained and patented in the jointly pending and jointly owned U.S. Patent Application No. 10/254830, which was awarded by Adrian-Raul Cernea And Yan Li filed an application on September 24, 2002. The entire disclosure of the reference application is incorporated herein by reference.

<b>Alternative embodiment with correction when blocking two neighbors</b>

As explained above, when the memory cells in the NAND chain are under programmed conditions, their bit lines and therefore their channels are kept at approximately ground potential. When a high programming voltage appears on the control gate of a memory cell, it induces a high voltage on its floating gate. A channel maintained at approximately ground potential helps to maximize the potential difference between the channel and the floating gate, thereby establishing favorable conditions for tunneling electrons transmitted therebetween to affect programming.

For NAND chains on the same set of word lines that no longer need to be programmed, they are programmed to be prohibited or blocked regardless of the programmed voltage on their control gate. This is done by reducing the tunneling potential. The NAND chain must be programmed to increase its bit line from ground to V_DD. This can effectively close the drain select transistor and float the channel of the NAND chain. As the channel floats, the channel will rise from ground to a higher voltage due to the high programming voltage appearing on the word line. This reduction is associated with the tunneling potential between the floating gate and the channel to prohibit programming.

Therefore, the general plan is to ground the channel of the NAND chain to establish favorable conditions for programming and to float the channel to prohibit programming. However, as pointed out above, if the neighbors of the NAND chain are in the program prohibition mode, the NAND chain under the programmed conditions will be disturbed by the high potential on the channels of one or both of these neighbors. The solution described above attempts to adjust the bit line voltage of the NAND chain under programmed conditions by trying to use the same amount in a "common mode" cancellation to compensate for this disturbance. Float the bit line by using grounding, and when the adjacent bit line voltage changes from zero to V_DDWhen a part of the voltage is capacitively coupled, the adjustment can be completed. When the NAND chain is programmed so that its neighbors are in the program prohibit mode, there will be a capacitive coupling contribution from the bit lines of the two neighbors.

Figure 13 illustrates the stylized configuration along a row of the NAND chain where second-level errors may still occur. This occurs in the following situations: the NAND chain 50 under the stylized condition is flanked by the two adjacent chains 51, 51' also under the stylized condition, and the NAND chain 50 under the stylized condition is flanked by the two closely adjacent chains 52, 52' in the program prohibit mode Further flank the NAND chain. The solution described above requires the chains 50, 51 and 51' under stylized conditions to make the bit lines 36-0, 36-1, 36-1' float using the ground voltage from their adjacent bit lines And capacitive coupling. This is better for adjacent chains 51, 51', because the additional coupling voltage V₁It is used to compensate for the disturbance caused by the increased passage of the closely adjacent chains 52, 52'. However, for the NAND chain 50 flanked by adjacent chains 51, 51', the channel voltage should ideally be grounded to provide maximum programming efficiency. If it also floats its bit line 36-0 by grounding, it will get an extra, non-zero voltage V₀, Which uses extra voltage V from the bit lines 36-1 and 36-1' of the adjacent chain₁One part is coupled.

According to another aspect of the present invention, when one unit of the NAND chain is under the programmed condition and the NAND chain is surrounded by two adjacent neighbors flanking also under the programmed condition, the bit line coupled with the NAND chain is forced to be one Voltage in order to maximize the potential difference between the floating gate of the cell and the channel. In a preferred embodiment, this would require setting the bit line to ground potential. This will require the NAND chain to recognize the status of its neighbors, that is, whether it is in the program mode or program prohibit mode.

In a preferred embodiment, a sensing module (such as the sensing module 380 shown in FIG. 12) controls the voltage on the bit line. As explained above, the sensing module 380 and especially the sensing amplifier 600 coupled with the bit line 36 will generate the control signal INV, which is high in the programming mode and low in the programming mode. Therefore, the signal INV can be used to indicate to the neighbor that the NAND chain coupled with the bit line 36 is in the program mode or the program inhibit mode.

FIG. 14 illustrates the configuration of the sensing module in which each sensing module also senses the INV signal of its neighbor. The bit line 36-0 is surrounded by the flanks of the bit lines 36-1 and 36-1', respectively. The sensing module 380-0 is coupled to the bit line 36-0, and the sensing modules 380-1 and 380-1' are coupled to the bit lines 36-1 and 36-1', respectively. Because each sensing module receives the INV signal from its neighbors, the sensing module 380-0 receives the INV signal from the sensing module 380-1 and 380-1' respectively as the input signal INV_LAnd INV_R. Similarly, the INV signal of the sensing module 380-0 is input to the sensing modules 380-1 and 380-1'.

FIG. 12 illustrates the sensing module according to the preferred embodiment, which responds to pull the bit line to the adjacent state of grounding. This is implemented by an optional bit line pull-down circuit 560 used to pull node 523 to ground, depending on the neighboring state. When the NAND chain coupled to the bit line 36 is in the programming mode, INV is high and the transistor 522 is conducting to couple the bit line to the node 523. The bit line pull-down circuit includes two n-transistors connected in series with the ground. The INV signal INV from adjacent sensing modules 380' and 380" respectively_LAnd INV_RInput and control the conduction of two n-transistors. When two neighbors are in stylized mode, INV_LAnd INV_RWill also be high, thereby pulling down node 523, and therefore pulling bit line 36 down to ground. Conversely, if one or more of the neighbors are in the program inhibit mode, the circuit 560 will not pull the node 523 to ground.

FIG. 15 illustrates an alternative embodiment in which a signal indicating that the neighbor is in the programmed mode or the program disabled mode is directly obtained from the state of the neighbor's bit line. This solution can be used when it is difficult to obtain signals from adjacent sensing modules. As explained above, when the NAND chain is in the programming mode, the bit line voltage is maintained at approximately ground potential, and when the NAND chain is in the program inhibit mode, the bit line voltage is maintained at V_DD。

The virtual INV signal generator 570 senses the bit line voltage and outputs a virtual INV signal VINV, which is logically equivalent to the INV signal generated by the sensing module. The virtual INV signal generator 570 includes a p-transistor 572, which is connected in series with the n-transistor 574 in the pull-up/pull-down configuration of the node for outputting the signal VINV. The p-transistor 572 is determined by the voltage V in its gate_WKPPull up weakly. The voltage of the bit line 36' is input to the gate of the n-transistor 574. The virtual INV signal generator 570 is essentially a three-state inverter, which outputs a high VINV signal when the bit line 36-1 has a voltage close to the ground (programmed mode), and when the voltage is V_DD(Program prohibit mode) output low VINV signal.

In the example shown in Figure 15, the VINV signal is used as the signal VINV_LInput to adjacent sensing module 380-0. Therefore, the signal INV or VINV can be used to communicate the information about the programming or programming prohibition state with the sensing module 380-0 coupled to the NAND chain. In the case where both of its adjacent NAND chains are in the programming mode, the sensing module 380-0 pulls the bit line to the ground through the bit line pull-down circuit 560.

Although various aspects of the present invention have been described in terms of certain specific embodiments, it should be understood that the present invention is granted rights protected by the full scope of the appended patent application.

<p>10Memory Unit</p><p>36Bit Line</p><p>36'Bit line</p><p>36-0Bit Line</p><p>36-1Bit Line</p><p>36-1'Bit Line</p><p>36-2Bit Line</p><p>36-3Bit Line</p><p>50NAND string/chain</p><p>50-1NAND string</p><p>50-2NAND string</p><p>50-3NAND string</p><p>51Chain</p><p>51'Chain</p><p>52Chain</p><p>52'Chain</p><p>54Source terminal</p><p>56Kip terminal</p><p>60,...,64Control gate/word line</p><p>70Charge Storage Unit</p><p>70-1Charge Storage Unit</p><p>70-2Charge Storage Unit</p><p>70-3Charge Storage Unit</p><p>80Channel</p><p>80-1channel</p><p>80-2channel</p><p>80-3Channel</p><p>170Circuit</p><p>300Memory Unit</p><p>310Control circuit</p><p>312State Machine</p><p>314On-chip address decoder</p><p>316Power Control Module</p><p>330Column Decoder</p><p>330AColumn Decoder</p><p>330BColumn Decoder</p><p>360line decoder</p><p>360Aline decoder</p><p>360Bline decoder</p><p>370Read/Write Circuit</p><p>370ARead/Write Circuit</p><p>370BRead/Write Circuit</p><p>380Sensing Module</p><p>380'sensing module</p><p>380"Sensing Module</p><p>380-0sensing module</p><p>380-1Sensing Module</p><p>380-1'sensing module</p><p>501sensing node</p><p>502Isolation Transistor</p><p>520Pull-down circuit</p><p>522n Transistor</p><p>523node</p><p>530Read bus transmission gate</p><p>532Read bus</p><p>540Page Controller</p><p>550n Transistor</p><p>560Pull-down circuit</p><p>570Signal Generator</p><p>572p Transistor</p><p>574n Transistor</p><p>600Sensing amplifier</p><p>610Bit Line Voltage Clamp</p><p>612Transistor</p><p>620Second voltage clamp</p><p>640Pre-charge circuit</p><p>650Discriminator circuit</p><p>652Special capacitor</p><p>660Latch</p>

Figure 1 schematically illustrates a non-volatile memory cell in the form of an EEPROM cell.

Figure 2 schematically illustrates a string of charge storage cells organized into a NAND cell or string.

FIG. 3 illustrates an example of a NAND cell array such as the array shown in FIG. 2.

FIG. 4 schematically illustrates a memory device according to an embodiment of the present invention, which has a read/write circuit for reading and programming a page of memory cells in parallel.

FIG. 4B illustrates a preferred configuration of the memory device shown in FIG. 4A.

5A illustrates a cross-sectional perspective view of the memory transistors along the direction 5A-5A shown in FIG. 2 and the equivalent capacitance between the charge storage unit and the word line, and between the charge unit and the channel.

FIG. 5B schematically illustrates the capacitive coupling of the memory transistor shown in FIG. 5A, thereby specifically showing the voltage in the charge storage unit due to the voltage in the channel and the voltage in the word line.

FIG. 6A illustrates a cross-sectional perspective view of the NAND cell array shown in FIG. 3 when the two adjacent memory transistor systems are in the programming mode.

6B illustrates a cross-sectional perspective view of the NAND array similar to that of FIG. 6A, except that one of the adjacent memory transistors is in the program inhibit mode.

FIG. 7 schematically shows the capacitive coupling between the two bit lines through a capacitor.

8(A) to 8(G) are timing diagrams according to the first embodiment of the present invention, which illustrate the voltage compensation scheme by capacitive bit line-to-bit line coupling during the programming operation.

8(H) to 8(O) illustrate the timing of the preferred sensing module shown in FIG. 12 related to the features of the present invention.

9(A) to 9(G) are timing diagrams according to the second embodiment of the present invention, which illustrate the voltage compensation scheme by capacitive bit line-to-bit line coupling during the programming operation.

FIG. 10 is a flowchart according to a preferred embodiment, which shows a page of programming adjacent memory storage units, while minimizing the occurrence of individual memory transistors that are program-banned or blocked among these units Coupling error method.

FIG. 11 is a flowchart according to another preferred embodiment, which shows a page of programming adjacent memory storage units, while minimizing the occurrence of individual memory transistors that are program-banned or blocked among these units The wrong way of coupling.

Figure 12 illustrates a preferred sensing module implementing various aspects of the present invention.

Figure 13 illustrates the stylized configuration along a row of the NAND chain where second-level errors may still occur.

FIG. 14 illustrates the configuration of the sensing module in which each sensing module also senses the INV signal of its neighbor.

FIG. 15 illustrates an alternative embodiment in which a signal indicating that the neighbor is in the programmed mode or the program disabled mode is directly obtained from the state of the bit line of the neighboring memory transistor.