Non-volatile memory and method with bit line compensation dependent on neighboring operating modes

Non-volatile memory and method with adjacent operation mode and bit line compensation

The present invention relates generally to non-volatile semiconductor memory, such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM, and more specifically to having a row of charge storage cells for one page. A non-volatile semiconductor memory with improved stylized and sensed circuitry.

Solid-state memories capable of non-volatile storage of charge (especially EEPROM and flash EEPROM packaged in small form factor) have become the choice of various mobile and handheld devices (especially information appliances and consumer electronics) in recent years. Storage body. Unlike the RAM (random access memory) which is also a solid-state memory, the flash memory system is non-volatile, so it can retain its stored data even after the power is turned off. Although the cost is higher, the use of flash memory as a mass storage application is becoming more common. The cumbersome mass storage (which is dominated by rotating magnetic media, such as hard drives and floppy disks) is not suitable for use in mobile and handheld environments. This is because the size of the disc drive tends to be bulky, it is prone to mechanical failure, and the waiting time is cumbersome and the power supply demand is extremely high. These annoying factors make disc-type storage objects unusable for most mobile and portable applications. Conversely, flash memory (regardless of the type of built-in or removable cards) is ideal for both mobile and handheld environments because of its small size, low power consumption, fast speed, and high reliability.

Both EEPROM and Programmable Read Only Memory (EPROM) are non-volatile memory that can be erased and can be written or "programmed" into their memory cells. Both are tied to a floating (unconnected) conductor gate in a channel region of a semiconductor substrate located in the source region and the drain region in a potential transistor structure. A control gate is then placed on the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge remaining on the floating gate. That is, for a given charge level on the floating gate, a corresponding (critical) voltage must be applied to the control gate before the transistor is "on" to allow its source region and drain The interval produces conduction.

The floating gate is capable of retaining a certain range of charges and, therefore, can be programmed into any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is defined by the minimum critical level and the maximum critical level of the device, and the levels correspond to the range of charges that can be programmed on the floating gate. The critical window is typically dependent on the characteristics of the memory device, operating conditions, and historical data. In theory, each different, resolvable threshold voltage level range within the window can be used to represent a well-defined memory state of the memory cell.

One of the following two mechanisms is usually used to program the transistor as a memory cell into a "programmed" state. In "hot electron emission", the high voltage applied to the drain accelerates the electrons across the substrate channel region. At the same time, the high voltage applied to the control gate pulls the hot electrons up to the floating gate via a thin gate dielectric. In "tunneling", a high voltage is applied to the substrate to the control gate. In this way, electrons can be pulled from the substrate to the intermediate floating gate.

The following devices can be used to erase the memory device. For EPROM, ultraviolet radiation can be used to remove charge from the floating gate for bulk erasing of the memory. For the EEPROM, a high voltage is applied to the substrate relative to the control gate such that electrons can be induced in the floating gate to tunnel a thin oxide into the substrate channel region (ie, Fowler- The Nordheim tunneling effect can erase a memory cell. In general, EEPROM can be erased on a byte by byte basis. For flash EEPROM, the memory can be erased all at once or more than one block can be erased each time. One of the blocks is composed of more than 512 memory bytes.

The memory devices typically include more than one memory chip that can be mounted on a card. Each memory chip includes a memory cell array supported by peripheral circuits such as decoders, erase circuits, write circuits, and read circuits. The finer memory device is also equipped with a controller that implements the operation and interface of smart and high-order memory. There are many commercially available non-volatile solid state memory devices available today. These memory devices may use different types of memory cells, each having more than one charge storage unit.

Figure 1 is a schematic diagram of a non-volatile memory cell of an EEPROM memory cell. Its charge storage unit is a floating gate. An electrically erasable and stylized read-only memory (EEPROM) structure is identical to EPROM, however, a mechanism is additionally provided to electrically charge charge to its floating gate when a suitable voltage is applied and The charge is electrically removed from its floating gate without exposure to UV radiation. Examples of such memory cells and methods of making the same are disclosed in U.S. Patent No. 5,595,924.

2 is a schematic diagram of a series of charge storage units that have been assembled into a NAND cell or string. A NAND cell 50 is composed of a series of memory transistors M1, M2, ... Mn (n = 4, 8, 16 or higher), the source and the drain of which are daisy-chained. together. A pair of select transistors S1, S2 controls the connection of the memory transistor chains to the outside via the source terminal 54 and the drain terminal 56 of the NAND cell. In a memory array, when the signal SGS turns on the source select transistor S1, the source terminal is coupled to a source line. Similarly, when the signal SGD turns on the drain select transistor S2, the drain terminal of the NAND cell is coupled to a bit line of the memory array. Each memory transistor in the chain has a charge storage unit to store a specific amount of charge to represent a desired memory state. A channel-to-channel region between the source and the drain of each memory transistor. The voltage across the control gates (e.g., 60, 62, ..., 64) of each memory transistor controls the conduction of current in the channel regions of the memory transistors M1, M2, ..., Mn, respectively. situation. Selecting transistors S1, S2 will control the access condition of the NAND cells through their source terminals 54 and drain terminals 56, respectively, and will be turned on by the appropriate voltages on their control gates, respectively.

When a NAND cell-addressed memory transistor is read or verified during programming, its control gate is supplied with an appropriate reference voltage. At the same time, a sufficient voltage V is applied_PASSThe control gate of the remaining unaddressed memory transistors in the NAND cell 50 is fully turned on. In this manner, a conduction path can be effectively generated from the source of the individual memory transistor to the source terminal 54 of the NAND cell, as well as from the drain of the individual memory transistor to the NAND of the NAND cell. The pole terminal 56 effectively produces a conduction path. Similarly, during programming, the memory transistor to be programmed will supply a stylized voltage V._PGMThe gate is controlled, and the control gate of the other memory transistors in the string is supplied with the turn-on voltage V_PASS. A memory device having such a NADN cell structure is described in U.S. Patent Nos. 5,570,315, 5,903,495, and 6,046,935.

Another similar non-volatile memory utilizes a dielectric layer as its charge storage unit. It uses a dielectric layer in place of the previously described conductive floating gate elements. Such memory devices utilizing dielectric storage elements have been described in "NROM: A Novel" by Eitan et al., November 2000, IEEE Electron Device Letters, Vol. 21, No. 11, pp. 543-545. Localized Trapping, 2-Bit Non-volatile Memory Cell. An ONO dielectric layer extends across the channel between the source and drain diffusion regions. The charge of one of the data bits is localized in the dielectric layer near the drain, and the charge of the other data bit is localized in the dielectric layer near the source. For example, U.S. Patent Nos. 5,768,192 and 6,011,725 disclose the implantation of a trapped dielectric non-volatile memory cell between two layers of ceria. Multiple state data storage can be achieved by separately reading the binary state of the charge storage region separated by the space within the dielectric.

Memory array

A memory device typically includes a two-dimensional array of memory cells that are arranged in a plurality of columns and a plurality of rows and that can be addressed using a plurality of word lines and a plurality of bit lines.

3 is a schematic diagram of an example of an array of a plurality of NAND cells (such as those shown in FIG. 2). A bit line 36 is coupled to the drain terminal 56 of each NAND cell along each row of NAND cells. In the figure, a source line 34 connects all of its source terminals 54 along each column of NAND cells. In addition, the control gates 60, ..., 64 of the NAND cells are also connected to a series of corresponding word lines along a column. The entire column of NAND cells can be addressed by the associated word line, using the appropriate voltage on the gates SGD and SGS to turn on the pair of select transistors (see Figure 2). When a memory transistor in a NAND cell chain is being read, it is difficult to turn on the remaining memory transistors in the chain through the associated word line, so the current flowing through the chain is basically It depends on the level of charge stored in the memory cell being read. An example of a NAND architecture array and its operation as part of a memory system has been found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,046,93.

Block erase

Stylization of the charge storage memory device may only result in the addition of more charge to its charge storage element. Therefore, it is necessary to remove (or erase) the existing charge in a charge storage element before performing the stylization operation. An erase circuit (not shown) can be provided to erase more than one memory cell block. A non-volatile memory (such as EEPROM) can be called "flash" when the entire memory cell array is erased at the same time (that is, instantaneously) or the bulk of the memory cells in the array is erased. EEPROM. Once erased, the group of memory cells can be reprogrammed. The memory cells that can be erased at the same time may be composed of more than one addressable erase unit. The erase unit or block usually stores more than one page of data, which is a unit of stylization and reading, but can also be programmed or read more than one page in a single operation. Each page usually stores more than one erase block, the size of which is defined by the main system. An example is an erase block consisting of 512 user data bytes and a number of additional information bytes (which are related to the user data and/or its stored blocks), which will comply with The standard established for the disk drive. In other systems, the size of the erase block may be much larger than 512 bytes.

Read/take circuit

In a conventional two-state EEPROM cell, at least one current interrupt point level is established to divide the conduction window into two regions. When a certain memory cell is read by applying a predetermined fixed voltage, it can be leveled with the interrupt point (or reference current I)_REFFor comparison, the source/drain current is resolved into a memory state. If the current being read is higher than the current at the break point level or I_REFThe memory cell is then determined to be one of the logical states (eg, the "zero" state). Conversely, if the current is lower than the current at the breakpoint level, the memory cell is determined to be another logic state (eg, a "one" state). Therefore, such a two-state memory cell can store one-digit digital information. A reference current source (which is typically externally programmable) is typically supplied as part of a memory system to generate the interrupt point level current.

As semiconductor technology advances, higher density flash EEPROM devices can be fabricated to increase memory capacity. Another way to increase storage capacity is to store more than two states per memory cell.

For a multi-state or multi-level EEPROM memory cell, more than one interrupt point can be used to divide the conduction window into more than two regions, so that each memory cell can store more than one bit of data. . Therefore, the information that a particular EEPROM array can store increases with the number of states each memory cell can store. An EEPROM or flash EEPROM having a plurality of multi-state or multi-level memory cells is described in U.S. Patent No. 5,172,338.

In fact, when a reference voltage is applied to the control gate, the memory state of a memory cell is read by sensing the conduction current across the source electrode and the drain electrode of the memory cell. Thus, for each particular charge on the floating gate of a memory cell, a corresponding on current associated with a fixed reference control gate voltage can be detected. Similarly, the range of charges that can be programmed onto the floating gate defines a corresponding threshold voltage window or a corresponding on current window.

Alternatively, may not detect the on-state current a partitioned current window, whichever Instead of the system, setting the threshold voltage of a particular memory state of an inspection of to the control gate at, and detecting the conduction current is actually based Low At or above a critical current. In one of the designs, by detecting the rate of the on-current discharged through the capacitance of the bit line, the purpose of detecting the on-current associated with a critical current can be achieved.

Factors affecting read/write performance and accuracy

To improve read and program performance, multiple charge storage elements or memory transistors in an array can be read or programmed in parallel. Therefore, a logical "page" composed of a plurality of memory elements can be simultaneously read or programmed. In an existing memory architecture, a column typically contains several interlaced pages. All memory components on a page will be read or programmed simultaneously. The row decoder will selectively connect each of the interlaced pages to a corresponding number of read/write modules. For example, in one design, the memory array would be designed to have a page size of 532 bytes (512 bytes plus 20 additional data bytes). If each row contains one bungee bit line and each column has two interlaced pages, then there will be a total of 8512 lines, and each page will be associated with 4256 lines. Thus, there will be 4256 sensing modules connectable for reading or writing all even or odd bit lines in parallel. In this way, a data page composed of 4256 bits (ie, 532 bytes) of data can be read in parallel from the memory component page, or a data page composed of 4256 bit data can be paralleled. Stylized into the memory component page. The read/write modules that make up the read/write circuits 170 can be configured in a variety of architectures.

As described above, conventional memory devices improve read/write operations by parallel operation. This approach improves performance but compromises the accuracy of read and write operations.

Another problem that must be solved is the coupling or crosstalk of the bit line and the bit line. This problem becomes more severe as parallel sensing of closely adjacent bit lines. A conventional solution to avoid bit-line and bit-line crosstalk is to simultaneously sense all even bit lines or all odd bit lines while grounding the other bit lines. This architecture, which uses two interleaved pages to form a column, helps to avoid bit line crosstalk and mitigates the problem of densely configuring read/write circuit pages. The set of read/write modules can be multiplexed into even or odd pages using a page decoder. In this way, when one of the bit lines is being read or programmed, the interlace group can be grounded to eliminate the crosstalk problem between the odd bit line and the even bit line, but the odd line cannot be solved. Crosstalk between inter- or even-line lines.

However, there are at least three disadvantages to this interlaced page architecture. First, additional multiplexed circuits are required. Second, the performance is very slow. To read or program a plurality of memory cells connected by a word line or in a column, two read operations or two program operations are required. Third, the way to solve other interference effects is also not ideal. For example, when two adjacent charge storage elements are programmed in different time (for example, in odd and even pages respectively), the floating gate position occurs. The electric field coupling phenomenon between adjacent charge storage elements.

As the spacing between memory cells gets closer, the problem of adjacent electric field coupling becomes more severe. In a memory transistor, a charge storage unit is sandwiched between a channel region and a control gate. The current flowing in the channel region is a function of the electric field synthesized by the control gate and the electrical field at the charge storage unit. As the density increases, the memory transistors get closer and closer. Then, the electric field originating from adjacent charge elements can have a significant effect on the resultant electric field of an affected memory cell. The adjacent electric field will depend on the charge that is programmed into the charge storage unit of the neighbors. The nature of this disturbing electric field is dynamic because it changes with the stylized state of the neighbors. Therefore, depending on the changing state of the neighbors, the reading results of an affected memory cell at different times may be different.

Conventional interleaved page architectures can exacerbate errors caused by coupling phenomena in adjacent charge storage cells. Because even pages and odd pages are stylized and read independently of each other, depending on what happens to the interlaced page at the time, a page can be programmed under one set of conditions and is completely different in one set. Read back under the conditions. Read errors become more severe as density increases, which requires more accurate read operations and a broader separation of critical windows for multiple state designs. Its performance will be affected and the potential capacity in multiple state designs will be limited.

U.S. Patent Application Serial No. 10/254483 and No. 10/254,290, filed on Sep. 24, 2002, the disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire disclosure The constructed memory page. When a memory page composed of a plurality of contiguous memory storage units is programmed, in the process, the memory storage unit that has been programmed to its target state will be prohibited from being programmed or locked. No further stylization is possible. In a preferred technique, the memory storage unit is locked by floating the channels of the memory storage units and boosting the voltage at the place to prohibit stylization; however, the boosted voltage may seriously interfere To the adjacent storage unit that is still being programmed.

Therefore, we usually need a high-performance and high-capacity non-volatile memory. In particular, we need a non-volatile memory with high capacity and improved read and program performance that effectively solves the aforementioned problems.

Parallel reading and writing of a corresponding memory cell page by a large read/write circuit page can meet the needs of high-capacity and high-performance non-volatile memory devices. In particular, the inherent interference effects of high-density wafer integration that can cause read and stylized errors can be eliminated or minimized.

The present invention provides apparatus and methods for performing memory operations on a population of memory cells in parallel. Each memory cell in the group may exist in one of several modes of operation. For example, when the group is programmed, some of the memory cells may be in stylized disable mode. A certain memory cell in the memory group that is undergoing a particular memory operation may be disturbed by its neighbors. The extension of the interference will depend on the mode of operation in which the neighbors are located. The interference can be compensated by the offset voltage applied to the bit line of the memory cell, which may be a function of the mode of operation of its neighbors.

The present invention provides a partial stylized circuit and method in which interference from adjacent memory cells can be offset by adding a cancellation voltage to the bit line voltage of the stylized candidate memory storage unit. The offset will have a functional relationship with the mode of operation of the two neighbors. If the mode of operation of one or more of the neighbors causes interference, the offset can be adjusted accordingly to minimize the interference.

Specifically, when staging a contiguous page of multiple storage units, each time a storage unit reaches its target state and is prohibited from being stylized or locked for further stylization, it will still interfere with Stylized adjacent storage units. The present invention provides a portion of a stylized circuit and method in which offset sales can be added to adjacent memory cells that are still being programmed to offset interference. The offset is added by applying a predetermined bias voltage to the bit line of the memory cell that is still being programmed. Specifically, if the storage unit abuts two neighbors left and right in the stylization prohibition mode, the preset offset sales will compensate for interference originating from two neighbors. If the storage unit has only one of the neighbors in the stylized inhibition mode, then the bit line offset sales will be relatively low, only enough to compensate for interference from one of the neighbors. If the storage unit is not adjacent to any neighbors in the stylized prohibition mode, then the offset sales will actually be zero. In this way, errors inherent in the stylization of parallel high-density memory cells can be eliminated or minimized.

According to a preferred embodiment, the bit line voltage of each memory cell is set to function in relation to the mode of operation of its neighbors, whether in a stylized inhibit mode or a stylized mode. The mode of operation can be determined using signals from the sensing modules of each of its neighbors. Alternatively, the voltage conditions on the bit line of each of its neighbors can be utilized to determine the mode of operation of each of its neighbors. A one-line voltage selector supplies a suitable bit line voltage with an appropriate offset to the bit line as a function of the operating mode of the neighbors. In this way, the staggered storage unit can be sensed to interfere with the still-storing storage unit, and compensated by appropriately applying the bit line voltage to the sales volume.

Additional features and advantages of the invention will be apparent from the description of the preferred embodiments of the invention.

All bits threaded

The sensing module 380 shown in Figures 4A and 8 is preferably designed as a memory architecture configured to implement full bit line sensing. In other words, the contiguous memory cells in a column can be individually connected to a sensing module for performing sensing in parallel. Such a memory architecture is also disclosed in copending and co-pending U.S. Patent Application Serial No. 10/254,48, the entire disclosure of which is incorporated herein by reference. And Method Thereof". The entire disclosure of this patent application is incorporated herein by reference.

As mentioned earlier, the number of memory cells that are simultaneously programmed or read in a "page" may change with the size of the data sent or requested by a host system. Therefore, there are several ways to program the memory cells that are coupled to a single word line: (1) separate stylized even bit lines and odd bit lines, which may include the upper page stylized and Page stylization; (2) stylizing all of the bit lines ("full bit threading"); or (3) separately stylizing all bit lines in the left and right pages, which may include the right page stylized and The left page is stylized.

4A is a schematic diagram of a memory device having a plurality of read/write circuits for reading and staging a memory cell page in parallel, in accordance with an embodiment of the present invention. The memory device includes a two-dimensional memory cell array 300, a control circuit 310, and a read/write circuit 370. The memory array 300 can be addressed by the column decoder 330 by a plurality of word lines and by the row decoder 360 by a plurality of bit lines. The read/write circuit 370 includes a plurality of sensing modules 380 and allows parallel reading or programming of a memory cell page.

In the present invention, the memory cell pages to be read or programmed in parallel are preferably a series of consecutive memory cells or memory cells. In other embodiments, the page may be a segment of a contiguous memory storage cell or storage unit.

The control circuit 310 cooperates with the read/write circuits 370 to perform a memory operation on the memory array 300. The control circuit 310 includes a state machine 312, an on-chip address decoder 314, and a power control module 316. State machine 312 provides wafer level memory operation control. The on-chip address decoder 314 provides an address interface between the address used by the host system or memory controller to the hardware address used by the decoders 330 and 370. The power control module 316 controls the power and voltage supplied to the word lines and bit lines during memory operation.

FIG. 4B is a schematic diagram of a preferred configuration of the memory device shown in FIG. 4A. The memory array 300 can be accessed in a symmetrical manner on both sides of the array using various peripheral circuits such that the density of access lines and circuitry on each side can be halved. Thus, the column decoder can be partitioned into column decoders 330A and 330B and the row decoders can be partitioned into row decoders 360A and 360B. Similarly, the read/write circuits can be divided into read/write circuits 370A connected from the bottom of the array 300 to a plurality of bit lines and read/write circuits 370B connected from the top of the array 300 to a plurality of bit lines. . In this manner, the density of the read/write modules can be substantially halved, so that the density of the sense modules 380 can be halved.

High voltage on the channel and charge storage unit

The errors inherent in high-density integrated circuits and non-volatile memory devices are caused by the coupling of adjacent charge storage cells to the channel regions. If the voltage of the channel region and the charge storage unit of a memory storage unit is raised relative to an adjacent unit, the charge storage unit of the adjacent unit will be disturbed. This effect is more pronounced when the memory storage units are stylized in parallel and the memory storage units are densely packaged or the memory storage units are not properly shielded.

5A is a cross-sectional perspective view of a memory transistor taken along direction 5A-5A shown in FIG. 2, and between and between the charge storage unit and the word line. The equivalent capacitance between the channels. The control gate 60 of the memory transistor M1 is part of a word line that is routed along a column in the NAND array 100 (see Figure 3). In this figure, the drain is located on the front side of the page of Figure 5A, and the source is located on the back of the page, which defines a channel region 80 in the middle. A charge storage unit 70 is placed between the control gate 60 and the channel region 80 and is insulated by a plurality of layers of dielectric material. The electrical coupling between the charge storage unit 70 and the control gate 60 can utilize an equivalent capacitor C._WFTo model. Similarly, the electrical coupling between the charge storage unit 70 and the channel region 80 can utilize an equivalent capacitor C._FCTo model.

5B is a schematic diagram showing the capacitive coupling of the memory transistor shown in FIG. 5A, which clearly shows the voltage at the channel and the voltage at the word line at the charge storage unit. Voltage. If the amount of charge stored in the charge storage unit 70 is Q, then C_WFWith C_FCBoth will retain the same charge. The voltage at the charge storage unit 70 is V_CS=(C_WFV_W+C_WFV_C) / (C_WF+C_FC). It can be readily seen that the voltage of the charge storage unit generally increases as the voltage at the channel and/or the word line increases. The next paragraph will show that when a memory transistor (such as M1) is placed in the stylized disable mode, the channel voltage is raised to a high voltage. Therefore, a high voltage is also generated at the charge storage unit. Combining the high voltage at channel 80 and charge storage unit 70 will have an interfering effect on adjacent memory transistors in the stylized mode.

Stylized overshoot caused by neighboring cells in a high voltage (stylized inhibited state) state

6A is a cross-sectional perspective view of the NAND array shown in FIG. 3 in the case where both adjacent memory transistors are in a stylized mode. For example, FIG. 6A may represent three adjacent memory transistors in a column that share the same word line 60, such as M1-1, M1-2, and M1-3, belonging to NAND string 50, respectively. -1, 50-2 and 50-3. The NAND strings 50-1, 50-2, and 50-3 respectively have bit lines 36-1, 36-2, and 36-3 connectable thereto. The memory transistors M1-1, M1-2 and M1-3 have corresponding charge storage units 70-1, 70-2 and 70-3 and channels 80-1, 80-2 and 80-3.

As the density of memory arrays increases, the memory transistors become more and more compact, and the effects of each other become more and more serious. For example, the threshold voltage of the memory transistor M1-2 will depend on the voltage of its charge storage unit 70-2. Because of their close relationship with the neighbors M1-1 and M1-3, the voltages on the M1-1 and M1-3 channels and the charge storage unit may affect the voltage on the M1-2 charge storage unit. For example, the charge storage unit 70-2 can be considered to utilize an equivalent capacitor C, respectively.₁₂With C₂₃It is coupled to its adjacent charge storage units 70-1 and 70-3. Similarly, the charge storage unit 70-2 can be regarded as utilizing the equivalent capacitor C', respectively.₁₂With C'₂₃It is coupled to its adjacent channels 80-1 and 80-3. The closer the spacing between the memory transistors, the higher the degree of coupling between them.

Figure 6A illustrates the situation where both adjacent memory transistors M1-2 and M1-1 are in a stylized mode. Focusing on the effect of M1-1 on M1-2, there is a slight variation in the relationship between the word line voltage and the bit line voltage, because these voltages are the same for M1-2 and M1-1. . The channel voltages are also the same. The only difference seen by charge storage unit 70-2 is due to charge storage unit 70-1, which is primarily a function of its retained charge or its data. For example, the voltage on the charge storage cells of M1-1 and M1-2 may be approximately 1 to 2 V. Interference caused by such interference is usually resolved by allowing sufficient thresholds between two different memory states.

6B is a cross-sectional perspective view of the same NAND array as FIG. 6A, but one of the adjacent memory transistors is in a stylized inhibit mode. In this case, M1-2 is being programmed, and M1-1 is forbidden for further stylization. The word line voltages of the two will remain equal, but the voltage on the bit line 36-1 of M1-1 will change to V._DDIt is a preset system voltage, for example about 2.5 V. Thus, the selective transistor S2 (see FIG. 2) can be effectively turned off, the NAND chain 50-1 and its bit line 36-1 are disconnected, and the channel 80-1 of the floating M1-1 is caused to cause the word line 60. When a high voltage is present, it can be raised to a high voltage in a capacitive manner. For example, channel 80-1 of M1-1 can be raised to 10 V in this manner. Raising the voltage of the channel will effectively reduce the potential difference between the channel and the charge storage unit, thereby avoiding the studming of electrons from the channel to the charge storage unit.

Looking at the previous discussion with Figure 5B, a high voltage channel will result in a high voltage charge storage unit. For example, when the memory transistor M1-1 is in the stylized mode, it may increase the voltage of the channel 80-1 by about 10 V and increase the voltage of the charge storage unit 70-1 by about 2 V to 8 V. This will significantly interfere with the adjacent memory transistors (eg, M1-2) that are to be programmed. For example, the charge storage unit 70-2 of M1-2 will increase its voltage by ΔV.₂~0.2 V. This is because its charge storage unit 70-2 is capacitive (for example, C respectively)₁₂With C'₁₂The relationship of the charge storage unit 70-1 coupled to the high voltage (stylized inhibit) memory transistor M1-1 to the channel 80-1. In general, the threshold voltage of the memory transistor is programmed in steps from 0.8 V to about 0.1 V, which will cause the current to cause M1-2 to be incorrectly programmed to a higher than expected threshold.

All of the current discussions focus on the interference effects caused by M1-1 on memory transistor M1-2. If M1-3 is also in the stylized disable mode, its high voltage will be coupled in the same way, thereby increasing the voltage on the charge storage unit 70-2 of M1-2. In the worst case, when the memory transistor M1-2 is in the stylized mode and the neighbors M1-1 and M1-3 on both sides are locked (stylized prohibited) and cannot be further programmed, The interference caused to the charge storage unit 70-2 of M1-2 may be as high as 0.2 V. For the M1-2 being programmed, this effect is equivalent to increasing the stylized voltage on its control gate by 0.4 V. As a result, under certain circumstances, it may lead to excessive stylization, which in turn leads to a wrong state. For example, the critical window of the memory cell may be divided into intervals of about 0.3 V, while the stylized pulse step is increased by about 0.1 V each time, so more than one is usually required for each segment. Pulse. The current stylized pulse step may only push M1-2 to a critical area just below the expected stylized state. At the same time, the current pulse step may program M1-1 and M1-3 to their final state, causing them to be locked by entering the stylized disable mode, making it impossible to further program. Therefore, in the next stylized pulse step, the M1-2 will suddenly suffer up to 0.5. The role of V's large stylized steps. This will likely cause M1-2 to overshoot beyond the expected critical section and be incorrectly programmed to the next memory state.

A technique for correcting interference using bit line-to-bit line coupling is disclosed in the copending and co-owned U.S. patent application "Non-volatile memory and method with bit line to bit line coupled compensation". The application date and the applicant are the same as the case. The entire disclosure of this reference application is incorporated herein by reference.

Bit line compensation for interference caused by voltage boost of neighbors

7A-7D are various interference diagrams of a memory mode of operation for a neighbor of a stylized memory cell. The staging memory cell is coupled to a portion of NAND cell 50 of bit line 36-0. The adjacent NAND cells are respectively 51 on the left and 51' on the right, which are coupled to bit lines 36-1 and 36-1', respectively.

The configuration of Figure 7A is such that both neighbors 51 and 51' adjacent to NAND cell 50 are in a staging inhibit mode. This means that the NAND cells that are being programmed will be disturbed by the high voltage channels of the adjacent NAND cells on both sides. Referring again to Figure 6B, the memory cell or storage unit being programmed is M1-2 and its left neighbor M1-1. The interference caused by the high voltage channel of M1-1 will actually increase the potential of the floating gate 70-2 of M1-2 by ΔV.₂Voltage (for example 0.2 V). Similarly, if another neighbor M1-3 is also programmed to be disabled, its high voltage channel will also increase the voltage at the floating gate 70-2, resulting in a total ΔV.₂(eg 0.4 V).

The memory transistor M1-2 is being programmed, so if the voltage at the charge storage unit 70-2 of M1-2 is increased by ΔV₂This will lead to stylized errors.

According to a preferred embodiment, the same amount is introduced on the bit line 36-2 to compensate for the interference voltage ΔV at the charge storage unit 70-2.₂. This bit line compensation voltage will be transferred to the channel such that the potential difference between the charge storage unit 70-2 and the channel 80-2 is substantially zero. This eliminates any errors in the threshold voltage.

Therefore, according to the technique of the present invention shown in FIG. 7A, this high voltage will substantially be applied to the equal predetermined voltage bias ΔV of the bit line of M1-2.₁₁offset.

7B and 7C are configured such that one of the two neighbors 50-1 and 50-1' adjacent to the NAND cell 50 is in the stylized inhibit mode and the other is in the stylized mode. This means that the NAND cell being programmed will only be disturbed by the high voltage channel of one of the adjacent NAND cells. Therefore, the high voltage channel of one of the neighbors will increase the voltage at the floating gate 70-2, resulting in a total amount of ΔV.₂(eg 0.2 V). According to the technique of the present invention, this high voltage will substantially be applied to the equal predetermined voltage bias ΔV of the bit line of M1-2.₁₀(or V₀₁)offset.

The configuration of Figure 7D is such that none of the neighbors 50-1 and 50-1' adjacent to the NAND cell 50 are in the stylized disable mode. This means that the NAND cells that are being programmed will not be disturbed by their neighboring NAND cells. Therefore, adjacent channels will not increase the voltage at floating gate 70-2. Therefore, since there is no relationship between high voltage channels, V₂Will be 0 V, and the corresponding offset preset voltage V₀₀Or the bit line bias voltage will also be 0 V.

Figure 8 is a preferred sensing module for designing various aspects of the present invention. The sensing module 380 includes a one-bit isolation transistor 502, a one-line pull-down circuit 520, a one-line voltage clamp 610, a read bus transmission gate 530, and a sense amplifier 600.

In general, the memory cells in a page are operated in parallel. Therefore, there will be a corresponding number of sensing modules operating in parallel. In one embodiment, the page controller 540 will expediently provide control and timing signals to the sensing modules in the parallel operation.

When the signal BLS activates the bit line isolation transistor 502, the sensing module 380 can be coupled to the bit line 36 of a memory cell 10. The sensing module 380 senses the on current of the memory cell 10 by using the sense amplifier 600, and latches the read result at the sensing node 501 in the form of the digital voltage level SEN2, and outputs it to a read. The bus bar 532.

The sense amplifier 600 basically includes a second voltage clamp 620, a precharge circuit 640, a discriminator or comparison circuit 650, and a latch 660. The discrimination circuit 650 includes a dedicated capacitor 652.

One of the characteristics of the sensing module 380 is to add a constant supply voltage to the bit line during sensing. This purpose is preferably designed with the bit line voltage clamp 610. The bit line voltage clamp 610 operates in the same manner as the same diode clamp, which uses a transistor 612 to connect the bit lines 36 in series. Its gate is biased to a constant voltage BLC equal to its threshold voltage V_TThe above expected bit line voltage V_BL. In this way, it can isolate the bit line from the sensing node 501 during stylization-verification or reading, and set a constant voltage level for the bit line, such as the expected V._BL= 0.5 to 0.7 volts. In general, the bit line voltage level is set to very low to prevent lengthy precharge times; however, the level must be high enough to prevent ground noise and other factors.

The sense amplifier 600 senses the on current via the sense node 501 and determines whether the on current is higher or lower than a preset value. The sense amplifier outputs the resulting signal SEN2 sensed at the sense node 501 to the read bus 532 in a digital format.

The digital control signal INV (which is basically the reverse state of the signal SEN2) is also output to control the pull-down circuit 520. When the sensed on current is higher than the preset value, INV will be HIGH and SEN2 will be LOW. Pull down circuit 520 can enhance this result. The pull-down circuit 520 includes an n-electrode 522 controlled by a control signal INV and another n-electrode 550 controlled by a control signal GRS. After it enters LOW, the GRS signal substantially causes the bit line 36 to become floating regardless of the state of the INV signal. During the stylization, the GRS signal will enter HIGH, causing bit line 36 to be pulled to ground. When the bit line must float, the GRS signal will go to LOW.

14(H)-14(O) are timing diagrams of the preferred sensing module shown in FIG. 8 in accordance with features of the present invention. Adrian-Raul Cernea and Yan Li, in co-pending and co-owned U.S. Patent Application Serial No. 10/254, 830, filed on Sep. A detailed description of the operation of the group. The entire disclosure of this reference application is incorporated herein by reference.

FIG. 9 is a schematic diagram of the configuration of a sensing module, wherein each sensing module also senses the INV signal of its neighbors. Bit line 36-0 will adjoin bit lines 36-1 and 36-1', respectively. Sensing module 380-0 will be coupled to bit line 36-0, while sensing modules 380-1 and 380-1' will be coupled to bit lines 36-1 and 36-1', respectively. Because each sensing module receives the INV signal from its neighbors, the sensing module 380-0 receives the INV signal from its sensing modules 380-1 and 380-1', respectively, as input. Signal INV_LWith INV_R. Similarly, the INV signal of the sensing module 380-0 is input to the sensing modules 380-1 and 380-1'.

Referring again to FIG. 8, in accordance with a preferred embodiment, the bit line bias is supplied by a one-bit line voltage compensator 560. It will signal INV_LWith INV_RForms the mode from its left and right neighbors, and responds according to the bias voltage meter of FIG. 11 to supply a bias voltage ΔV_BL. The bias voltage is supplied to node 523, which is coupled to bit line 36 in a switchable manner. During the stylization, both signals BLS and INV are HIGH, while the signal GRS is LOW. These signals allow bit line 36 to access bit line voltage compensator 560.

Figure 10 is a schematic diagram of an alternative design in which a signal indicating whether the neighbor is in a stylized mode or a stylized inhibit mode is derived directly from the state of a neighboring bit line. This technique is very useful when it is not easy to get a signal from a proximity sensing module. As mentioned earlier, when the NAND chain is in the stylized mode, its bit line voltage will remain near ground potential, and its bit line voltage will remain at V when it is in the stylized disable mode._DDAt the office.

The virtual INV signal generator 570 senses the bit line voltage and outputs a virtual INV signal (VINV) that is logically equivalent to the INV signal generated by a sensing module. The virtual INV signal generator 570 includes a p-transistor 572 and an n-transistor 574, both in series in the form of a pull-up/pull-down configuration of a node of the output signal VIVIN. p transistor 572 will be voltage V at its gate_WKPSlightly pulled up. The voltage of the bit line 36' is input to the gate of the n transistor 574. The virtual INV signal generator 570 behaves substantially like the same tristate inverter. When the voltage of the bit line 36-1 is close to ground (stylized mode), it outputs a HIGH VINV signal; when the voltage is at V_DDAt this time, it outputs a LOW VINV signal (stylized inhibit mode).

In the example shown in Figure 10, the VIVIN signal will signal VIVIN._LThe form is input to the adjacent sensing module 380-0. Thus, with the signal INV or VINV, information related to the stylized or stylized inhibit state can be sent to the sensing module 380-0 coupled to a NAND chain. In the case where both of the adjacent NAND chains are in the stylized mode, the sensing module 380-0 pulls the bit line to ground through the bit line pull-down circuit 520.

Figure 11 is a bias voltage table listing the offset voltages applied to the bit lines of a stylized storage unit as a function of the stylized inhibit mode of its left and right neighbors. The intermediate rows are applied to the offset voltage or bias voltage in the bit line of the staging storage unit in a functional relationship to the mode of its left and right neighbors. In general, the more neighbors are in the stylized disable mode, the more bit line bias is needed to offset the interference effect.

Figure 12 is a schematic diagram of a more detailed portion of the bit line voltage compensator shown in Figure 8 in accordance with a preferred embodiment of the present invention. Basically, the bit line voltage compensator 560 will respond to the signals INV at inputs 561 and 563, respectively._LWith INV_RAnd will output the bias voltage ΔV at 565_BLOutput to node 523 of sensing module 380 (see Figure 8). To supply the bias voltages listed in the table of Figure 11, the three voltage sources 562, 564, 566 will supply ΔV, respectively.₀₀(eg 0 V), V₁₀(eg 0.15 V) and ΔV₁₁(eg 0.3 V). Output 523 is permeable to the input signal INV_LWith INV_RA pair of logic switches in the state select each of these voltage sources.

FIG. 13 is a flow chart of a method for staging a memory page composed of a plurality of consecutive charge storage units according to a preferred embodiment of the present invention. The state in which the crystal is programmed to be disabled or locked minimizes the coupling error caused by the individual memory transistors.

All bit stylized

Step 400: For a page of consecutive memory storage units, each unit has a charge storage unit between a control gate and a channel region defined by a source and a drain, which will be the page Each memory storage unit provides a bit line that is switchably coupled to its drain and a block of all control gates coupled to the memory storage unit page line.

Sensing the mode of operation of its neighbors

Step 410: Determine, for each of the memory storage units of the page to be programmed, whether the adjacent memory storage unit is in the stylized prohibition mode.

Bit line precharge with offset sales

Step 420: Apply a first preset voltage to each of the memory storage units of the stylized forbidden page to disable stylization.

Step 422: Apply a second preset voltage to each bit line of the memory storage units of the page to be programmed to facilitate programming, the second preset voltage of each bit line It is a function of its operating mode adjacent to the memory storage unit to offset any interference here.

Stylized pulse supply, verification & prohibition

Step 430: Apply a stylized voltage pulse to the word line to program the memory cells of the page in parallel, wherein the floating memory channel can be boosted to a stabilizing voltage condition. Stabilizing a memory storage unit having a certain predetermined voltage from a bit line, and compensating for the high voltage of any adjacent stylized memory storage unit by the offset from the second predetermined voltage The interference caused.

Step 440: Verify that any of the memory storage units that are being programmed are already programmed to their target state.

Step 450: Mark any memory storage unit that has been verified to be stabilizing and any memory storage unit that has not been verified for stylization.

Step 460: Have all the memory storage units in the page been verified? If not, return to step 420. If yes, proceed to step 480.

Step 470: End.

14(A)-14(G) are timing diagrams of the voltage compensation technique during a stylization operation in accordance with a first embodiment of the present invention.

The voltages in the figure are supplied to the word lines and bit lines of the memory array for NAND chains that are programmed and stabilized (see also Figures 2 and 3). Stylized operations can be classified into bit line precharge phase, stylized phase, and discharge phase.

In the bit line precharge phase:

(1) SGS at 0 V turns off the source selection transistor (Fig. 14(A)) and enters the high level V_SGThe SGD will turn on the drain select transistor (Figure 14(B)), allowing one bit line to access a NAND chain.

(2) The bit line voltage of a stylized NAND chain is allowed to rise to a preset voltage V_DD(Fig. 14(F)). When the bit line voltage of the stunted NAND chain rises to V_DDWhen the stunted NAND chain is turned off, the gate voltage SGD on the drain select transistor is reduced to V._DDTime becomes floating. At the same time, the bit line voltage of a programmed NAND chain is actively pulled down to 0 V (Figure 14(G)).

(3) Using the ΔV supplied from the bit line voltage compensator 560_BLThe bit line voltage of the stylized NAND chain is biased (Fig. 14(G)). ΔV output by voltage compensator 560_BLThe value depends on whether one or both of its neighbors are in a stylized disable mode.

(4) The voltage of the drain word line connected to the drain select transistor of a column of NAND chain will drop to V._DD. This result will only float the bit line voltage approaching V_DDThe stylization prohibits the NAND chain because its bungee selection transistor will be turned off (Figures 14(B) and 14(F)). For a NAND chain containing a memory transistor to be programmed, its drain select transistor will not be turned off in accordance with the bit line voltage at its drain that is close to 0 V.

(5) The memory transistor in the unaddressed NAND chain will set its control gate voltage to V._PASSTo fully open it (Fig. 14(C)). Because the NAND chain that is stabilized is floating, it is applied to the high V of the unaddressed memory transistors._PASSWith V_PGMIt will increase the voltage at its channel and charge storage element, thus prohibiting stylization. V_PASSUsually in accordance with V_PGM(eg ~15-24 V) is set at the intermediate voltage (eg ~10 V). In the case of a chain that is stigmatized, V_PASSHelps reduce the exposure to higher voltages V_PGMEffective memory V_DS, which helps to reduce leakage. As far as a stylized chain is concerned, ideally, V_PASSShould be at ground potential, therefore, the middle V_PASSThe voltage is a reasonable compromise.

Stylized phase:

(6) Applying a stylized voltage to the control gate of the selected memory transistor (Fig. 14(D)). Storage units that are stabilized (that is, with high voltage channels and charge storage units) will not be programmed. The stylized memory location will be stylized by a bias bit line voltage (Figure 14(G)) to offset one or both of its neighbors in the stylized disable mode. Any interference caused.

In the discharge phase:

(7) Each control line and bit line are allowed to discharge.

Basically, the interference on a stylized storage unit is due to the adjacent storage unit having a relationship between a floating channel that is capacitively boosted by a high control gate voltage (which voltage is from a word line) and a charge storage unit. This happens when a NAND chain is placed in stylized disable mode. This result also has the adverse effect of disturbing (increasing) the voltage on the charge storage unit of the memory transistor to be programmed. By sensing the motion of its neighbors during the staging of a memory cell, an appropriate bit line voltage bias can be utilized to compensate for interference from its neighbors.

While the various aspects of the present invention have been described with respect to the specific embodiments thereof, it should be understood that the invention is to be protected by the full scope of the appended claims.

<p>10 memory cells</p><p>34 source line</p><p>36 bit line</p><p>36-0 bit line</p><p>36-1 bit line</p><p>36-1' bit line</p><p>36-2 bit line</p><p>36-3 bit line</p><p>50 NAND cell</p><p>50-1NAND string</p><p>50-2NAND string</p><p>50-3NAND string</p><p>51 NAND cells</p><p>51' NAND cell</p><p>54Source terminal</p><p>56Bungy terminal</p><p>60Control gate</p><p>62Control gate</p><p>64Control gate</p><p>70Charge storage unit</p><p>70-1Charge storage unit</p><p>70-2Charge storage unit</p><p>70-3Charge storage unit</p><p>80Channel area</p><p>80-1 channel</p><p>80-2 channel</p><p>80-3 channel</p><p>100NAND array</p><p>300 memory array</p><p>310Control circuit</p><p>312 State Machine</p><p>314 on-chip address decoder</p><p>316Power Control Module</p><p>330 column decoder</p><p>330A column decoder</p><p>330B column decoder</p><p>360 line decoder</p><p>360A line decoder</p><p>360B row decoder</p><p>370Read/Write Circuit</p><p>370ARead/Write Circuit</p><p>370BRead/Write Circuit</p><p>380Sensor module</p><p>380-0Sense Module</p><p>380-1Sense Module</p><p>380-1'Sense Module</p><p>501Sensor node</p><p>502 bit line isolation transistor</p><p>520 bit line pull-down circuit</p><p>522n transistor</p><p>523 nodes</p><p>530Read busbar transmission gate</p><p>532Read busbar</p><p>540 controller</p><p>550n transistor</p><p>560 bit line voltage compensator</p><p>561Enter</p><p>562voltage source</p><p>563Enter</p><p>564voltage source</p><p>565 Output</p><p>566voltage source</p><p>570Virtual INV signal generator</p><p>572p transistor</p><p>574n transistor</p><p>600Sense Amplifier</p><p>610 bit line voltage clamp</p><p>612Optoelectronics</p><p>620Second voltage clamp</p><p>640Precharge circuit</p><p>650Discrimination circuit</p><p>652 capacitor</p><p>660Latch</p>

Figure 1 is a schematic diagram of a non-volatile memory cell of an EEPROM memory cell.

2 is a schematic diagram of a series of charge storage units that have been assembled into a NAND cell or string.

3 is a schematic diagram of an example of an array of a plurality of NAND cells (such as those shown in FIG. 2).

4A is a schematic diagram of a memory device having a plurality of read/write circuits for reading and staging a memory cell page in parallel, in accordance with an embodiment of the present invention.

FIG. 4B is a schematic diagram of a preferred configuration of the memory device shown in FIG. 4A.

5A is a cross-sectional perspective view of a memory transistor taken along direction 5A-5A shown in FIG. 2, and between and between the charge storage unit and the word line. The equivalent capacitance between the channels.

5B is a schematic diagram showing the capacitive coupling of the memory transistor shown in FIG. 5A, which clearly shows the voltage at the channel and the voltage at the word line at the charge storage unit. Voltage.

6A is a cross-sectional perspective view of the NAND array shown in FIG. 3 in the case where both adjacent memory transistors are in a stylized mode.

6B is a cross-sectional perspective view of the same NAND array as FIG. 6A, but one of the adjacent memory transistors is in a stylized inhibit mode.

7(A)-7(D) schematically show the different bit line voltage offsets of a stylized storage unit as a function of the stylized inhibit state of the left and right neighbors.

Figure 8 is a preferred sensing module for designing various aspects of the present invention.

FIG. 9 is a schematic diagram of the configuration of a sensing module, wherein each sensing module also senses the INV signal of its neighbors.

Figure 10 is a schematic diagram of an alternative design in which a signal indicating whether the neighbor is in a stylized mode or a stylized inhibit mode is derived directly from the state of a neighboring bit line.

Figure 11 is a bias voltage meter listing the offset voltages applied to the bit lines of a stylized storage unit as a function of the stabilizing state of its left and right neighbors.

Figure 12 is a schematic diagram of a more detailed portion of the bit line voltage compensator shown in Figure 8 in accordance with a preferred embodiment of the present invention.

FIG. 13 is a flow chart of a method for staging a memory page composed of a plurality of consecutive charge storage units according to a preferred embodiment of the present invention. The state in which the crystal is programmed to be disabled or locked minimizes the coupling error caused by the individual memory transistors.

14(A)-14(G) are timing diagrams of the voltage compensation technique during a stylization operation in accordance with a first embodiment of the present invention.

14(H)-14(O) are timing diagrams of the preferred sensing module shown in FIG. 8 in accordance with features of the present invention.