Driver chip and display apparatus having the same

Driver chip and display device with the chip

1. Field of Invention

The present invention relates to a driver chip and a display device with the driver chip. More specifically, the present invention relates to a driver chip that can improve the reliability of the connection between the driver chip and the display panel, and a display device with the driver chip.

2. Description of related skills

Generally speaking, mobile telecommunication devices, digital cameras, notebook computers, monitors, etc. require a display device. Various types of display devices can be used. However, flat panel display devices, such as a liquid crystal display (LCD) device, are widely used due to their advantages.

Liquid crystal display devices display images by using liquid crystals. The liquid crystal display device is not only thin and light, but also has the characteristics of low power consumption and low driving voltage.

A conventional liquid crystal display device includes a liquid crystal display panel for displaying images and a driver chip for driving the liquid crystal display panel.

The driver chip converts the external image data into a driving signal to apply the driving signal to the liquid crystal display panel. The driver chip can be electrically connected to the liquid crystal display panel in various ways.

Recently, in order to reduce the size and manufacturing cost, the chip-on-glass (COG) method is widely used. According to the COG method, the driver chip is directly mounted on the liquid crystal display panel. In detail, an anisotropic conductive film (ACF) is inserted between the driver chip and the liquid crystal display panel, and the liquid crystal display panel is compressed under high temperature. Therefore, the driver chip and the liquid crystal display panel are electrically connected to each other.

Although the COG method is effective for connecting the terminals of the driver chip to the liquid crystal display panel, the driver chip may be deformed due to the difference in thermal expansion coefficient between the driver chip and the liquid crystal display panel. Furthermore, pressure may be produced on the driver chip. Therefore, defects in the electrical connection between the driver chip and the liquid crystal display panel may occur.

Summary of the invention

The present invention provides a driver chip that can improve the reliability of the connection between the driver chip and the liquid crystal display panel.

The present invention also provides a display device with the driver chip.

In the driver chip exemplified according to the present invention, the driver chip includes a substrate, an input terminal area, and a first output terminal area. The base system includes a surface with a long side and a short side. The input end point area is formed on the first edge of the surface along the long side. The first output terminal area is formed on the second edge portion opposite to the first edge portion along the short side. The first output terminal area is formed along the long side. The input end area and the first output end area are arranged within about 9d/10 from the center of the long side to the short side, wherein<i>'</i>d<i>'</i>Indicates the distance between the center of the long side and the short side.

In another exemplary driver chip according to the present invention, the driver chip includes a substrate, an input terminal area, a first output terminal area, and a dummy terminal area. The base system includes a long side and a short side substantially perpendicular to the long side. The input end area is formed on the first edge of the base along the long side. The first output terminal area is formed along the short side on a second edge opposite to the first edge. The first output terminal area is formed along the long side. The dummy end point area is formed on one side of the first output end point area along the long side.

In the exemplified display device according to the present invention, the display device includes a driver chip and a display panel. The driver chip includes a base, an input terminal area and a first output terminal area. The base system includes a surface with a long side and a short side. The input end point area is formed on the first edge of the surface along the long side. The first output terminal area is formed on the second edge portion opposite to the first edge portion along the short side. The first output terminal area is formed along the long side. The input end area and the first output end area are arranged within about 9d/10 from the center of the long side to the short side, wherein<i>'</i>d<i>'</i>Indicates the distance between the center of the long side and the short side. The display panel includes a wire for transmitting electrical signals and a pad area for electrically connecting the driver chip to the wire.

According to the present invention, the input end point and the output end point are formed on areas other than the edge of the base body where the pressure is concentrated. Therefore, the reliability of the electrical connection between the driver chip and the display panel can be improved.

Schematic description

The above and other features and advantages of the present invention will become clearer by describing the illustrated embodiments in detail with reference to the accompanying drawings, in which: Figure 1 illustrates the driver chip according to the first exemplary embodiment of the present invention Perspective view; Fig. 2 shows the shear stress diagram of the driver chip in Fig. 1; Fig. 3 shows the normal stress diagram of the driver chip in Fig. 1; Fig. 4 shows the driver in Fig. 1 Fig. 5 is a plan view illustrating the driver chip in Fig. 1; Fig. 6 is a plan view illustrating the driver chip according to the second exemplary embodiment of the present invention; Fig. 7 A plan view illustrating a driver chip according to the third exemplary embodiment of the present invention; Fig. 8 illustrates a plan view of a driver chip according to the fourth exemplary embodiment of the present invention; Fig. 9 illustrates a plan view of the driver chip according to the fifth exemplary embodiment of the present invention Example of a perspective view of the display device; Figure 10 is an enlarged view of the pad area of the first substrate in Figure 9; and Figure 11 is along the line II of Figure 9<i>'</i>The cross-sectional view taken.

Description of the embodiment

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<u style="single">Example of driver chip</u>

<u style="single">Example 1</u>

FIG. 1 is a perspective view illustrating the driver chip according to the first exemplary embodiment of the present invention.

1, a driver chip 100 according to the first exemplary embodiment of the present invention includes a substrate 110, an input terminal area 120 and a first output terminal area 130.

The base 110 includes an insulating material, and the base 110 has a parallelepiped shape with one face. The surface has first and second long sides 110a and 110b, and first and second short sides 110c and 110d substantially perpendicular to the first and second long sides 110a and 110b. A semiconductor device (not shown) for converting an external image signal into a driver signal is arranged inside the substrate 110.

The input end region 120 is formed on the first edge of the surface of the base 110 along the first long side 110a. The input terminal area 120 includes n input terminals IT₁-IT_n,in<i>'</i>n<i>'</i>It is a natural number not less than 2. The input endpoint IT₁-IT_nThey are arranged on a single line along the first long side 110a.

The first output terminal area 130 is formed on the second edge of the surface of the base 110 along the second long side 110b. The first and second edge portions are separated from each other. The first output endpoint area 130 includes m output endpoints OTA₁-OTA_m,in<i>'</i>m<i>'</i>It is a natural number not less than 2. The output endpoint OTA₁-OTA_mThey are arranged in two lines along the second long side 110b. The first output terminals arranged on the first line are separated from each other, and the first output terminals arranged on the second line substantially parallel to the first line are arranged on the first line arranged on the first line. Between one output terminal.

However, the first output endpoint OTA₁-OTA_mCan be arranged in a single line, or the first output terminal OTA₁-OTA_mCan be arranged into more than two lines.

The driver chip 100 is directly mounted on a display panel (not shown) through the COG method. In the COG method, the driver wafer 100 is heated. When the driver chip 100 is cooled, the driver chip 100 is deformed due to the difference in thermal expansion coefficient between the driver chip 100 and the display panel. The driver chip 100 is also under stress. The stress can be classified into a shear stress and a normal stress, and the shear stress and the normal stress can be Suhir<i>'</i>s module simulation.

Fig. 2 shows the shear stress diagram of the driver chip in Fig. 1, and Fig. 3 shows the normal stress diagram of the driver chip in Fig. 1. The first and second long sides 110a and 110b of the driver chip in Figures 2 and 3 have a length of about 20 mm.

Referring to FIGS. 2 and 3, the shear stress applied to the driver chip 100 forms a plateau between 0 to about 8 mm, and the shear stress drops rapidly after passing a distance of about 8 mm. That is, when the distance between the central area and the area separated from the central area is less than or equal to about 8 mm, no shear stress is applied. However, when the distance between the central area and the area separated from the central area is greater than about 8 mm, the shear stress increases rapidly. In particular, when the distance between the central area and the area separated from the central area falls within the range of about 9 mm to about 10 mm, the shear stress is concentrated on the area separated from the central area.

The normal stress applied to the driver chip 100 is similar to shear stress. The normal stress applied to the driver chip 100 forms a plateau between 0 and about 8 mm, and the normal stress increases rapidly after passing a distance of about 8 mm. That is, when the distance between the central area and the area separated from the central area is less than or equal to about 8 mm, no normal stress is applied. However, when the distance between the central area and the area separated from the central area is greater than about 8 mm, the normal stress system increases rapidly.

As shown in Figures 2 and 3, the stress applied to the driver chip 100 is concentrated on an area of the first and second short sides 110c and 110d to reduce the electrical connection between the driver chip 100 and the display panel The reliability.

Figure 4 is a diagram showing the contact impedance between the driver chip and the liquid crystal display panel in Figure 1. The contact impedance is measured when the driver chip 100 performs a reliability test at a temperature of about 85° C. for 500 hours.

Referring to Fig. 4, the contact impedance does not change from 0 to about 8 mm, but when the area is separated from the central area by a distance greater than or equal to about 8 mm, the contact impedance increases. In particular, when the area is separated from the central area by a distance greater than or equal to about 9 mm, the contact resistance increases rapidly.

That is, when<i>'</i>d<i>'</i>When representing the distance between the center of the driver chip 100 and the first short side 110c, the stress is concentrated on the area from about 9d/10 to about d.

Therefore, the input terminal area 120 and the first output terminal area 130 are formed on a relatively low stress area not more than about 9d/10 from the center of the driver chip 100. As a result, the reliability of the electrical connection between the driver chip 100 and the display panel is improved.

Fig. 5 is a plan view illustrating the driver chip in Fig. 1 by way of example.

Referring to FIG. 5, an input terminal area 120 and a first output terminal area 130 are formed on a surface of the substrate 110.

The input end region 120 is formed on the first edge portion along the first long side 110a. A part of the input end region 120 is formed along the first long side 110a in an area of about 9d/10 from a center to a first short side 110c, and the remainder of the input end region 120 The part is formed along the first long side 110a in an area of about 9d/10 from a center to a second short side 110d, wherein<i>'</i>d<i>'</i>It is the distance from the center of the first long side 110a or the second long side 110b to the first short side 110c or the second short side 110d.

The first output terminal area 130 is formed on a second edge part separated from the first edge part. A portion of the first output terminal area 130 is formed along the second long side 110b in an area of about 9d/10 from a center toward the first short side 110c, and the first output terminal The remaining part of the area 130 is formed along the second long side 110b in an area of about 9d/10 from a center toward the second short side 110d. That is, the first end OTA of the first output end area 130 adjacent to the first short side 110c₁It is separated from the first short side 110c by a distance greater than about d/10. The last terminal OTA adjacent to the second short side 110d_mIt is separated from the second short side 110d by a distance greater than or equal to about d/10.

<u style="single">Example 2</u>

FIG. 6 is a plan view illustrating the driver chip according to the second exemplary embodiment of the present invention.

Referring to FIG. 6, a driver chip 200 according to the second exemplary embodiment of the present invention includes a substrate 210, an input terminal area 220, a first output terminal area 230, a second output terminal area 240, and a The third output terminal area 250. The base 210, the input terminal area 220, and the first output terminal area 230 are substantially the same as those of the driver chip 100 in FIG. 5. Therefore, any further explanations related to these components will be omitted.

The second output terminal area 240 is formed on a third end that is substantially perpendicular to the first end. The second output terminal area 240 is formed along the first short side 210c. The second output terminal area 240 may have substantially the same height as the first output terminal area 230. The second output terminal area 240 includes a number of second output terminals OTB₁To OTB_a,in<i>'</i>a<i>'</i>It is a natural number not less than 2. The second output terminal OTB₁To OTB_aThey are arranged in two lines on the third end along the first short side 210c. The second output terminal area 240 is disposed at a position about 9d/10 from the center of the first and second long sides 210a and 210b toward the first short side 210c. That is, the second output end region 240 is separated from the first short side 210c by a distance of not less than about d/10.

The third output terminal area 250 is formed on a fourth end portion separated from the third end portion. The third output terminal area 250 is formed along the second short side 210d. The third output terminal area 250 may have substantially the same height as the second output terminal area 240. The third output terminal area 250 includes b number of third output terminals OTC₁To OTC_b,in<i>'</i>b<i>'</i>It is a natural number not less than 2. The third output terminal OTC₁To OTC_bThey are arranged in two lines on the fourth end along the second short side 210d. The third output terminal area 250 is disposed at a position about 9d/10 from the center of the first and second long sides 210a and 210b toward the second short side 210d. That is, the distance between the third output end region 250 and the second short side 210d is not less than about d/10.

For example, the second output terminal OTB of the second and third output terminal regions 240 and 250₁To OTB_aAnd the third output terminal OTC₁To OTC_bThe lines are arranged in two lines. However, the second output terminal OTB₁To OTB_aAnd the third output terminal OTC₁To OTC_bCan be arranged into a single line or more than two lines.

<u style="single">Example 3</u>

FIG. 7 is a plan view illustrating the driver chip according to the third exemplary embodiment of the present invention.

Referring to FIG. 7, a driver chip 300 according to the third exemplary embodiment of the present invention includes a base 310, an input terminal area 320, a first output terminal area 330, and first and second dummy terminal areas 340a With 340b. The base 310, the input terminal area 320, and the first output terminal area 330 are substantially the same as those of the driver chip 100 in FIG. 5. Therefore, any further explanations related to these components will be omitted.

The first dummy terminal area 340a has a height from the surface of the base 310 that is substantially the same as the first output terminal area 330. The first dummy end area 340a extends from the first end of the first output end area 330 along a second long side 310b to be disposed close to the first short side 310c. The first dummy terminal area 340a includes a plurality of first dummy terminals DT₁. The first dummy terminal DT₁Are arranged in two lines, similar to the first output terminal OTA₁To OTA_mThe arrangement. The first dummy end region 340a is formed in an area not greater than about d/10, separated from the first short side 310c and toward the center of the second long side 310b.

The second dummy terminal area 340b has a height from the surface of the base 310 that is substantially the same as the height of the first output terminal area 330. The second dummy end area 340b extends from the second end of the first output end area 330 along a second long side 310b to be disposed close to the second short side 310d. The second dummy terminal area 340b includes a plurality of second dummy terminals DT₂. The second dummy terminal DT₂Are arranged in two lines, similar to the first output terminal OTA₁To OTA_mThe arrangement. The second dummy end region 340b is formed in an area that is separated from the second short side 310d by no more than about d/10 and faces the center of the second long side 310b.

No electrical signal is applied to the first and second dummy terminal regions 340a and 340b. The first and second dummy terminals DT₁With DT₂Can have an OTA with the first output endpoint₁To OTA_mA generally consistent shape. However, the first and second dummy terminals DT₁With DT₂Can have an OTA with the first output endpoint₁To OTA_mDifferent shapes.

According to this embodiment, the driver chip 300 further includes first and second dummy end regions 340a and 340b formed in the stress-concentrated area. The first and second dummy terminal regions 340a and 340b further relax or absorb stress, so as to improve the reliability of the connection between the driver chip 300 and the display panel.

<u style="single">Example 4</u>

FIG. 8 is a plan view illustrating the driver chip according to the fourth exemplary embodiment of the present invention.

Referring to FIG. 8, a driver chip 400 according to the fourth exemplary embodiment of the present invention includes a base 410, an input terminal area 420, a first output terminal area 430, a second output terminal area 440, and a The third output terminal area 450 and the first and second dummy terminal areas 460a and 460b. The base 410, the input terminal area 420, and the first, second, and third output terminal areas 430, 440, and 450 are substantially the same as those of the driver chip 200 in FIG. 6. Therefore, any further explanation will be omitted.

The third dummy end area 460a has substantially the same height as the second output end area 440, and the third dummy end area 460a is inserted between a first short side 410c and the second output end area. Between the end areas 440. In detail, the third dummy end region 460a is formed in the area where the stress is concentrated. In particular, the third dummy end region 460a is formed in an area that is not greater than about d/10 and is separated from the first short side 410c and faces the center of the driver chip 400. The third dummy terminal area 460a includes a plurality of third dummy terminals DT₃. No electrical signal is applied to the third dummy terminal DT₃。

The fourth dummy end point area 460b has substantially the same height as the third output end point area 450, and the fourth dummy end point area 460b is inserted between a second short side 410d and the third output end area. Between the end areas 450. In detail, the fourth dummy end region 460b is formed in the area where the stress is concentrated. In particular, the fourth dummy end region 460b is formed in a region that is not more than about d/10 apart from the second short side 410d and faces the center of the driver chip 400. The fourth dummy terminal area 460b includes a plurality of fourth dummy terminals DT₄. No electrical signal is applied to the fourth dummy terminal DT₄。

The third and fourth dummy terminals DT₃With DT₄Can be arranged in two lines. However, the third and fourth dummy terminals DT₃With DT₄Can be arranged into a single line or more than two lines.

In the foregoing, the driver chip according to the exemplary embodiment of the present invention has been explained. In the following, the display device using the driver chip will be explained.

<u style="single">Embodiment of display device</u>

<u style="single">Example 5</u>

FIG. 9 is a perspective view illustrating a display device according to a fifth exemplary embodiment of the present invention, and FIG. 10 is an enlarged view of the pad area of the first substrate in FIG. 9.

Referring to FIGS. 9 and 10, a display device 500 according to the fifth exemplary embodiment of the present invention includes a driver chip 200 and a display panel 600. The driver chip 200 is the same as the driver chip 200 in FIG. 6. Therefore, any further explanation about the driver chip 200 will be omitted.

The display panel 600 includes a first substrate 610, a second substrate 620 facing the first substrate 610, and a liquid crystal (not shown) interposed between the first and second substrates 610 and 620 Shows).

The first substrate 610 includes a plurality of wires 612 for transmitting electrical signals, and a pad area 614 for air connection between the driver chip 200 and the wires 612.

The wire 612 includes an input line 612a and a first output line 612b. The input line 612a is electrically connected to a flexible printed circuit (FPC) to receive external input signals. The first output line 612b is electrically connected to a gate line (not shown) and a data line (not shown). The gate line and the data line are formed on the first substrate 610. The gate line is substantially perpendicular to the data line.

The wire 612 may further include a second output line 612c and a third output line 612d. The second and third output lines 612c and 612d are electrically connected to the gate line and the data line.

The pad area 614 includes a plurality of input pad IP₁To IP_nAnd the first output pad OPA₁To OPA_m。

The input pad IP₁To IP_nIt is electrically connected to the input line 612 a on the first substrate 610. The input pad IP₁To IP_nCorresponding to the input terminal IT of the driver chip 200 in a one-to-one manner₁To IT_n, So that the external signal applied to the input line 612a passes through the input pad IP₁To IP_nAnd transfer to the driver chip 200.

The first output pad OPA₁To OPA_mIt is electrically connected to the first output line 612b on the first substrate 610. The first output pad OPA₁To OPA_mCorrespond to the first output endpoint OTA in a one-to-one manner₁To OTA_m, So that the output signal output from the driver chip 200 is transmitted to the gate line and the data line through the first output line 612b.

The pad area 614 may further include a second output pad OPB₁To OPB_aAnd the third output pad OPC₁To OCP_b。

The second output pad OPB₁To OPB_aIs formed on the input pad IP₁To IP_nOPA with the first output pad₁To OPA_mBetween, so that the second output pad OPB₁To OPB_aDepartment set in the input pad IP₁To IP_nAnd the first output pad OPA₁To OPA_mOn the edge above. The first edge part. The second output pad OPB₁To OPB_aIt is electrically connected to the second output line 612c. The second output pad OPB₁To OPB_aIt corresponds to the second output terminal OTB in a one-to-one manner₁To OTB_a。

The third output pad OPC₁To OPC_bIs formed on the input pad IP₁To IP_nOPA with the first output pad₁To OPA_mBetween, so that the second output pad OPB₁To OPB_aAttached to the input pad IP₁To IP_nAnd the first output pad OPA₁To OPA_mOn the second edge. The third output pad OPC₁To OPC_bIt is electrically connected to the third output line 612d. The third output pad OPC₁To OPC_bIt corresponds to the third output terminal OTC in a one-to-one manner₁To OTC_b。

The driver chip 200 is electrically connected to the pad area 614 having the above-mentioned explanation structure.

Picture 11 is along the line II of Picture 9<i>'</i>The cross-sectional view taken.

Referring to FIG. 11, a driver chip 200 is mounted on the pad area 614 by the chip-on-glass (COG) method. That is, an anisotropic conductive film (ACF) 700 is inserted between the driver chip 200 and the first substrate 610, so that the driver chip 200 is compressed with the first substrate at high temperature. 610 combined.

The ACF 700 includes a resin 710 and a plurality of conductive particles 720 randomly distributed in the resin 710.

The guiding particles 720 have a spherical shape. The conductive particles 720 inserted between the input terminal IT and the input pad IP are connected to each other by compression, so that the input terminal IT and the input pad IP are electrically connected to each other. The conductive particles 720 inserted between the first output terminal OTA and the first output pad OPA are connected to each other by compression, so that the first output terminal OTA and the first output pad OPA are electrically connected to each other. connect.

The resin 710 corresponds to a thermosetting plastic. Therefore, when the electrical connection between the input terminal IT and the input pad IP, or between the first output terminal OTA and the first output pad OPA is completed, the resin 710 is hardened to fix The driver chip 200 and the first substrate 610.

Although as shown in FIG. 11, the second output terminal OTB and the second output pad OPB are electrically connected to each other by the conductive particles 720, the third output terminal OTC and the third output pad OPC The conductive particles 720 are also electrically connected to each other.

For example, the display panel 600 is a liquid crystal display panel. However, a plasma display panel (PDP), an electroluminescence (EL), etc. can be used as the display panel 600.

According to the present invention, the input end point and the output end point are formed on the other areas except the edge of the substrate where the stress is concentrated. Therefore, the reliability of the electrical connection between the driver chip and the display panel can be improved.

The exemplified embodiments of the present invention and their advantages have been described. It should be noted that various changes, substitutions and substitutions of the present invention can be made without departing from the spirit and scope of the present invention defined by the scope of the appended patent application.

<p>100Driver chip</p><p>110Matrix</p><p>110aFirst long side</p><p>110bSecond long side</p><p>110cFirst short side</p><p>110dsecond short side</p><p>120Input Endpoint Area</p><p>130The first output end point area</p><p>200Driver chip</p><p>210Matrix</p><p>210aFirst long side</p><p>210bSecond long side</p><p>210cFirst short side</p><p>210dsecond short side</p><p>220Input Endpoint Area</p><p>230First output endpoint area</p><p>240Second output terminal area</p><p>250Third output terminal area</p><p>300Driver chip</p><p>310Matrix</p><p>310aFirst long side</p><p>310bSecond long side</p><p>310cFirst short side</p><p>310dSecond short side</p><p>320Input Endpoint Area</p><p>330The first output end point area</p><p>340aThe first dummy endpoint area</p><p>340bSecond dummy endpoint area</p><p>400Driver chip</p><p>410Matrix</p><p>410afirst long side</p><p>410bSecond long side</p><p>410cFirst short side</p><p>410dsecond short side</p><p>420Input Endpoint Area</p><p>430The first output end point area</p><p>440Second output end point area</p><p>450Third output terminal area</p><p>460aThe first dummy endpoint area</p><p>460bSecond dummy endpoint area</p><p>500Display device</p><p>600Display Panel</p><p>610First substrate</p><p>612Wire</p><p>612ainput line</p><p>612bThe first output line</p><p>612cSecond output line</p><p>612dThird output line</p><p>614Padded area</p><p>700Anisotropic Conductive Film (ACF)</p><p>710Resin</p><p>720Conducting particles</p><p>DT₁The first dummy endpoint</p><p>DT₂Second Dummy Endpoint</p><p>DT₃The third dummy endpoint</p><p>DT₄Fourth Dummy Endpoint</p><p>IP₁-IP_nInput pad</p><p>IT₁-IT_nInput endpoint</p><p>OPA₁-OPA_mFirst output liner</p><p>OPB₁-OPB_aSecond output pad</p><p>OPC₁-OPC_bThird output pad</p><p>OTA₁-OTA_mThe first output endpoint</p><p>OTB₁-OTB_aSecond output terminal</p><p>OTC₁-OTB_bThird output terminal</p>

Fig. 1 is a perspective view illustrating the driver chip according to the first exemplary embodiment of the present invention; Fig. 2 is a shear stress diagram of the driver chip in Fig. 1; Fig. 3 is a diagram showing the driver in Fig. 1 The normal stress diagram of the chip; Fig. 4 is a diagram showing the contact impedance between the driver chip and the liquid crystal display panel in Fig. 1; Fig. 5 is a plan view illustrating the driver chip in Fig. 1; Fig. 6 is an example A plan view of the driver chip according to the second exemplary embodiment of the present invention; Fig. 7 illustrates a plan view of the driver chip according to the third exemplary embodiment of the present invention; Fig. 8 illustrates a plan view of the driver chip according to the fourth exemplary embodiment of the present invention A plan view of the driver chip; FIG. 9 is a perspective view illustrating a display device according to a fifth exemplary embodiment of the present invention; FIG. 10 is an enlarged view of the pad area of the first substrate in FIG. 9; and Picture 11 is along the line II of Picture 9<i>'</i>The cross-sectional view taken.