Synchronizing the transmission of data via a two-way link

(54) NAME Synchronization of data transmission via a bidirectional link (56) PUBLISHING QUOTES:

EP A2 607 672 (H04L 12/56) (57) SUMMARY:

In a cell-based selector, the transfer of user cells, which may contain different number of data bits, is synchronized between functional entities via a bidirectional link. Each functional entity includes a link control function which contains functions for aft initiating and controlling the transmission of data on the link by means of sync cells, which are exchanged between the link control functions controlled by a sync state machine, which has three states (404,408,412). In a SEARCH state (412), the loan control function is caused to examine a sync cell coming from the link to determine whether it corresponds to a predetermined pattern for sync cells. In a DELETE state (404), which is preceded by a sync cell having been found in accordance with the predetermined pattern in the SEARCH state, the link control function causes the predetermined number of subsequent incoming sync cells to determine whether they predetermine whether if this is not the case, return to the SEARCH condition occurs. In a SYNC condition (408), which is preceded by in the SUPPLY state the predetermined number of sync cells exhibiting the predetermined pattern, transmission of data on the link during monitoring of data with respect to errors is permitted, whereby failure to occur switches to SÖK occurs.

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Technical area.

According to a first aspect, the present invention relates to a method and a system for synchronizing in a cell-based selector, the transfer of user cells, which may contain different numbers of data bits, between selector ports and selector core via a bidirectional link.

In a second aspect, the invention relates to a system for synchronizing data transmission in the form of a bit stream between functional entities via a bidirectional link, each functional entity having means for affixing user incoming data to be transmitted on the link. in user cells, which may contain different number of data bits depending on the size of the respective user data.

In many data transmission systems, various functional functions are interconnected via a link. This is especially the case with telecommunications systems. The link cost in many cases depends on the number of physical connections. The more connections, the higher the cost. Therefore, it is a common practice to apply all the information required to a single physical connection, which carries a digital signal. This makes it necessary to reconstruct the logical structure at the receiving end of the link. To accomplish this, implicit information must be transmitted, which points to the structure at different levels.

Examples of implicit information encoded in the digital signal are the clock, which allows bit alignment to be performed, and a synchronization pattern that allows alignment to be performed on octets, words, ATM cells, or any other higher structure than bits. For the term alignment with its meaning in terms such as cell alignment, the term attitude will continue to be used.

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The prior art.

Synchronization when transferring ATM cells causes problems, especially if different cell sizes occur.

A link for transmitting ATM cells has a cell synchronization mechanism based on the so-called Header Error Correction field (HEC) in the ATM cell and the process flow. A calculation called HCS (Header Checksum) is based on the four continuous octets and the remainder, which are included in the HEC. The process flow is based on a state machine, which has state HUNT, PRESYNC and SYNC. A well-known state machine for this purpose is described in Bellcore Document FA-NWT-001109. This state machine is shown in Fig. 1.

Proper HCS calculation brings the state machine according to arrow 102 to state PRESYNC 104. Provided that six consecutive correct HCS calculations occur in this state, transition 106, state SYNC 108, or transition, arrow 110, state HUNT 112. After seven consecutive incorrect HCS calculations in the SYNC state, transition, arrow 114, also occurs in the HUNT state.

A major disadvantage of using such a closed state machine, which operates without support from the originating side, is the time required to reach synchronization state, and consequently the cell loss when synchronization is lost. More than 60 cells can be lost before the link is brought into operative state. Another disadvantage is that the method in question does not allow the transfer of cells of different sizes on the link.

U.S. Patent No. 5,123,013 describes cell synchronization in a packet-switched system for transmitting and receiving a cell train composed of fixed-length data cells, including data to be transmitted. At least one synchronization cell containing a synchronization pattern is inserted between the data cells.

The synchronization cell or cells are transmitted in certain situations, namely, for a period of time during which no data cell is transmitted, or after that data cells have been transmitted successively for a predetermined interval after transmission of the synchronization cell.

GB 1,550,121 describes a speed tolerant digital data decoding system. Digital words are stored in cells of about the same size

506 540 width, with the exception of the initial cell of each word, which is called sync cell and has double width.

DE 3,842,371 relates to a device for rate synchronization of a cell-structured digital signal.

Disclosure of the Invention.

It is an object of the invention to provide a method for cell alignment in a bit stream containing cells of various sizes. Generally, this is achieved by the invention using a fast synchronization algorithm based on small synchronization cells and the use of suitable devices on either side of a bidirectional link.

The above purpose is achieved by means and systems for synchronizing the kind defined in the appended claims.

Specifically, in the method of the first aspect, the transmission of data on the link is initiated and monitored by means of sync cells, which are exchanged between the functional entities, each containing a synchronization pattern, with which the sync cell can be identified, and partly control data. Control data can be transmitted by the functional entities to values ​​that allow mutual control of synchronism, or a value that, in a state of operation on the link, which is perceived as a loss of synchronism, causes the functional entities to take steps to restore synchrony, etc.

The system according to the first aspect includes in each functional entity a link control function containing functions for initiating and controlling the transmission of data on the link by means of sync cells, which are exchanged between the link control functions controlled by a sync state machine having three states. In a SEARCH state, the link control function is caused to examine a sync cell coming from the link to determine if it matches a predetermined sync cell pattern. In a DELETED state preceded by a sync cell having been found in accordance with the predetermined pattern, in the SEARCH state, the link control function is caused to examine a predetermined number of incoming consecutive sync cells to determine if they are mismatched, return to the SEARCH state.

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In a SYNK state, which is preceded by the PRESET state, the predetermined number of sync cells exhibited by the predetermined pattern, the transmission of data on the link during monitoring of data with respect to errors, permits the transition to the SÖK state. .

The system of the second aspect includes in each functional entity a link control function with functions for initiating and controlling the transmission of data on the link by means of sync cells, which are exchanged between the link control functions, each containing identification information, with which the sync cell can be identified, and partly control data. Control data can be transmitted from each link control function to values ​​that allow for mutual control of synchronism, or a value which, in a state of operation on the link, which is perceived to mean loss of synchronism, causes the two loan control functions to take synchronization restoration measures. An output function against the link has a sync cell insertion function which receives a stream of user cells and in it inserts sync cells, and a first conversion function which receives the resulting user cells and sync cells and converts it into a bit stream signal which is clocked with a bit stream signal. clock signal out on the link. An input function from the link includes a second conversion function which receives a bit stream signal coming from the link and converts it into an n-bit parallel format, which is normally clocked out for every nth bit with an n-bit clock signal from the input function. A comparison function is connected to search and identify in the n-bit parallel format the identification information of a sync cell, and when it is found to output a confirmation signal. A clock function exists to enable clocking for each bit with a 1-bit clock signal of the n-bit parallel format from the input function. A sync state machine receives the confirmation signal to control the transition from clocking the n-bit parallel format with the n-bit clock signal to clock with the 1-bit clock signal.

Important advantages of the invention are the rapid synchronization and the fact that it allows the occurrence of different cell sizes. Due to the fast synchronization, cell loss is reduced when errors occur.

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Ficrurbeskrivnincr.

The invention will now be described in more detail with reference to the accompanying drawings, in which Fig. 1 shows a sync state diagram of a known sync state machine used in connection with cell synchronization on a transmission link; Fig. 2 schematically shows a telecommunications switch intended for both ATM and STM line connections, in which the invention can be applied, Fig. 3 shows in greater detail and on a larger scale a part of the selector according to fig. 2, including a bidirectional transmission link between a selector port and the selector core, to illustrate some essential features of the principle of the invention; FIG. between a selector port and selector core using the sync state machine of FIG. 4 for a possible practical synchronization scenario, Figures 6 and 7 show examples of embodiment of a synchronization cell or user cell, Fig. 8 shows in some detail a functional diagram of an embodiment of a link control system according to the invention included in each selector port and selector core, according to Fig. 3. Fig. 9 shows a functional diagram of a part of the link control system according to Fig. 8 in more detail; 10 shows a simplified sync state diagram of a sync state machine used in conjunction with the invention cell synchronization; Fig. 11 shows a transaction state diagram between a selector gate and selector core using the sync state machine of Fig. 10 for a possible practical synchronization scenario; 12 shows a more detailed sync state diagram of a sync state machine used in an embodiment of a link control system according to the invention described with reference to the following figures; Fig. 13 shows a functional diagram of a link control function,

506 540 which includes the sync state machine of Fig. 12, Figs. 14 and 15 show timing diagrams of examples of link synchronization processes in the link control system of Fig. 13.

Preferred embodiments.

Figure 2 shows a cell-based telecommunications switch intended for both ATM (Asynchronous Transfer Mode) and STM (Synchronous Transfer Mode) line connections. The selector contains a plurality of selector ports 202-l - 202_n connected to a selector core 204 via two-way link 206_n. Select the ports 202 are connected to e.g. a communication network, which may contain e.g. incoming lines 207 and 208, processors, etc. Lines 207 and 208 can carry ATM cells or STM time slots. Selector ports 202-l^{and 202}2 ^vin^SAS schematically, for example, as located on a line interface board 210-1 for STM line connection and a line interface board 210, respectively₂ for ATM line connection.

Line Interface Cards 210-l ^oc^ ²¹θ2 ^vin^SAS also schematically, such as containing each line ether terminals ing 212-1 and respectively. 2122, which via a link 214-l respectively. 2142 for user data is connected to the corresponding selector port 202-l^resP · 2022. Selector gate 202_n is shown schematically as an example located on a server card 210_n, which contains a processor 216, which is connected to the selector port via a link 214_n for user data.

In Fig. 3, the bidirectional traffic between e.g. selector port 202_n and select arc 204 via link 206_n in greater detail. Selector gate 202_n places based on upcoming user data in user cells. The size of these user cells is selected to fit the user data. Thus, for an ATM cell of 53 octets, a user cell size of 56 octets can be used, i.e. 53 bytes plus cell size information plus checksums. The STM time slots are placed in smaller cells. The user cell is then passed from one selector port to another through the selector core. For a more detailed description of the technology for inserting user data into user cells, and different approaches and circumstances in this context, reference can be made to Swedish patent application 9402051-8.

Selector gate 202_n contains a link control function 302, which receives user cells based on forthcoming user data for forwarding on link 206_n, and emits from the link comma506 540 the user cells whose data is to be sent to e.g. the network, indicated by double arrow 304. Traffic between selector port 202_n and the selector core 204 extends between the link control function 302 and a link control function 306 in the selector core. Link control functions 302 and 306 handle cell synchronization, as will be described in more detail below.

Cells of different sizes are transmitted on the link as a bit stream in each direction, which bit streams are schematically indicated at 308 and 310. 314. No explicit information regarding the beginning of a cell is transmitted. Both sides must therefore perform cell alignment in order to synchronize the link. For this purpose, sync cells are used, which if necessary are plugged into the user cell flow. In the bit streams 308 and 310, for example, a sync cell is indicated at 316 and 316, respectively. 318. The sync cells are originated and terminated in the link control function 302, respectively. 306 on each side, i.e. they do not appear in the selector ports or selector core outside the link control functions. The user cells are led unaffected by the link control functions. The design and operation of the link control functions will be described in more detail in the following description of embodiments.

Fig. 4 shows a sync state diagram illustrating the operation of a state control machine for the loan control functions on either side of the link, which is used for synchronizing the link. Sync cells incoming from the link to a link control function are compared with a predetermined pattern for sync cells. A first found match between an incoming sync cell and the predetermined pattern causes the state machine of arrow 402 to state 404. Assuming that two consecutive sync cells in the SUPPLY condition are found, which show compliance with the predetermined pattern, transition occurs, arrow 406, to a state 408 SYNC, otherwise transition, arrow 410, to a state 412 SEARCH occurs. The method of the invention is based on the consecutive transfer of sync cells during the SUPPLY condition. In the SYNK state, user cells can be transferred. Each user cell must contain information about its size in order for cell synchronization to be maintained, and should furthermore have error codes that allow it to detect an error in the cell size. One detected

506 540 errors in SYNK state 408 likewise bring the state machine to state 412 according to arrow 414. To ensure a true SYNK state if the error codes in the user cells cannot be considered sufficient, a monitoring state machine can also be added to the SYNK state. This monitoring function brings the state machine to state 412 according to arrow 414 if a predetermined number of n of consecutive user cells occurs. For further clarification in connection with the above mentioned regarding the design and desirable properties of user cells, reference is made to the aforementioned Swedish patent application 9402051-8.

In order to achieve fast synchronization and to keep the link in operational condition, it is required that the link controller on the page that receives user cells can transmit control data in the sync cells on the link to the link control function on the originating page.

Examples of such control data (commands) and the resulting actions can thus appear in the link controller on the originating page:

1st Control data: abortion. Means instruction to the originating link controller to interrupt ongoing user cell transmission and send a sync cell instead. Ongoing transmission of sync cells must be completed and the new sync cell then inserted.

2nd Control data: prompt. Indicates that SYNK state exists and instructs the originating link controller to return a sync cell at the first appropriate time. Specifically, the retained sync cell should be inserted into the normal cell flow so that as little disruption as possible of normal operation occurs.

3rd Control data: sync. Indicates that no sync cell is required in return from the originating page.

The use of the above three control data or commands will become more apparent from the description in connection with Figures 5, 8 and 9.

The abortion command could be replaced by the prompt command as shown below, among other things. in connection with the description of Fig. 6. The result is a somewhat slower synchronization if a large user cell is transmitted at this time.

The following sync cell transition rules are applied for the state machine:

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1st SEARCH / PRESYNC state. Send sync cells to the originating page containing the abortion or prompt command. The sync cell should be sent at the first appropriate time without any ongoing cell transfer.

2nd SYNC state. Send user cells, or send sync cells if a sync cell with an abort or prompt command has been received. If sync cells are returned, they should normally contain control data sync.

Fig. 5 schematically shows a simple transaction state diagram between selector port 502 and selector core 504 for a possible synchronization scenario.

First, both sides are in either of the states SEARCH and SUPPLY. They consequently send sync cells with control data prompt / abortion, arrows 506 and respectively. 508. After a defined number of consecutive sync cells, both enter the SYNK state. In the illustrated example, selector core page 504 switches to the SYNK state, according to arrow 510, before the selector gate. Select the archive therefore responds to the sync cells with control data abort / prompt by sending a sync cell with control data sync, arrow 512. Select port 502 now passes to SYNK state, arrow 514. The selector gate knows that the selector core is already in the SYNK state and therefore permits transfer of user cells, arrow 516. The now user cells receiving selector core 504 may in turn allow transfer of user cells, arrow 518 . The link is now in operational condition on both sides and will remain so until either side enters the SEARCH state because errors are detected or the monitoring function becomes operational.

In this example, selector gate 502 is affected and switches to the SEARCH state according to arrow 520. The selector gate now sends out sync cells with control data abortion / prompt according to arrow 522. Selector core 504 must respond by sending sync cells containing control data SYNK instead of user cells according to arrow 524. required number of consecutive sync cells returns selector port SYNK state, arrow 526.

The two sides can control each other during normal operation for they are really in the SYNK state. This can be done by sending sync cells regularly with the control data prompt. The other side should respond within a predetermined time frame with a sync cell with controlled sync. If not

506 540 occurs, it can be assumed that it is in some sort of incorrect SYNK state. For example, synchronization can be be lost but this is not detected due to the presence of a correct pattern in the user cells at the sites where the cell size analysis occurs and this condition may exist for a longer period of time. The right action if no sync cell occurs in return is to end the transmission of user cells and bring the other side to sync. The described method can supplement or replace the previously described monitoring function.

A first embodiment of a link control system according to the invention will now be described in more detail with reference to Figures 6-9.

In order to achieve rapid synchronization, it is desirable that the sync cell be as small as possible and yet so large that it may contain a pattern which is unlikely to be found in the user cells for an uninterrupted period of time. Fig. 6 shows an example embodiment of the sync cell. The size of the sync cell is limited to two words 602 respectively. 604. All codes are given in hexadecimal format. The first word 602 contains a sync pattern hex C2F1. The second word 604 contains a control data field for control data SYNK and prompt, which later in this case is presumed to have replaced abortion, an option mentioned as an alternative above. Thus, according to the main alternative, the control data field 604 in Fig. 6, in addition to the two displayed sync and prompt control data, could also contain control data abortion. In Fig. 6, for example, the codes hex 0100 and hex 0200 for sync and prompt are indicated.

The transmission direction is bits 1 to 16 and words 1 to 2. The most significant bit in a field is transmitted first. The bit to the right is least significant. The specified synchronization pattern is just one example; other codes can also be used. The synchronization pattern together with the control codes is selected so that the start position of the sync cell can be unambiguously defined in a consecutive sequence of sync cells. The control codes are selected with a Hamming distance of two. Other codes are conceivable.

Fig. 7 shows the user cell as containing a number of words 702_ς - 702_n. The size field 704 contains codes for various fixed sizes with redundant coding allowing error detection. The method is well known and can be based on Hamming code or the like. The user cell also contains two parity bits 706

506 540 and 708. Further details can be obtained from the above mentioned Swedish patent application 9402051-8. A code similar to the sync cell is not allowed. If errors occur in the size field or parity bits, the state machine of Fig. 4 ends in the SEARCH state 412.

Fig. 8 shows a functional block diagram of a link control function of the type described previously with reference to Fig. 3 and which is included in each selector port and in the selector core. As in Figure 3, in Figure 8, the designation 206 is used for the link between the two loan control functions, and the designation 304 for the flow of user cells to and from the link control function. In Fig. 8, however, a division has been made so that the flow of user cells from the loan control function is denoted by 304_f and the flow of user cells to the link control function is denoted by 304_t. The link control function includes a serial / parallel converter and sync cell setting function 802, a cell analysis function 804, a sync state machine 806, a sync cell insertion function 808, a clock generator 810, and a parallel / serial converter 812.

On the link 206 between the selector port and the selector core, in each direction a bit stream signal and a bit clock signal are indicated, indicated by arrows 816 and 818 for the receiving direction and arrows 820 and 822 for the transmission direction, respectively. The S / P converter and sync cell setting function 802 receives the bit stream 816 and converts it into 16 bits of parallel data, which is output as a word stream 824 to the cell analysis function 804.

Whenever the SEARCH condition applies to the sync state machine 806, it outputs a search signal 826 to the S / P converter and sync cell setting function 802, which causes the latter to search for a sync cell pattern for each bit position, cf. Fig. 6. When this pattern is found, function 802 outputs a sync coincidence signal 828 to sync state machine 806 and sync start signal 830 to cell analysis function 804. The sync match signal 828 causes the sync state machine 806 to DELETE state and deactivates the search signal 826. The sync start signal 830, which is only active when the search signal 826 is active, indicates to the cell analysis function 804 that a sync cell has been found.

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The S / P converter and sync cell setting function 802 now switches to parallel mode and clocks off the incoming bit stream 816 word for word. Each word is indicated by a word clock signal 832 to the cell analysis function 804. The S / P converter and sync cell setting function 802 outputs the sync matching signal 828 to the sync state machine each time it identifies a sync pattern.

The cell analysis function 804 contains an internal cell size counter, not shown, which it starts when it receives the sync start signal 830. The counter is clocked by the word clock signal 832. When the cell size is counted down, the cell analysis function 804 gives a new signal 804 to the sync state machine. The cell analysis function 804 studies the new cell to see if it has an accepted format in the size field. An unacceptable code causes the transmission of an error signal 836 to the sync state machine 806. The error signal 836 brings the sync state machine 806 to the SEARCH state.

Cell analysis function 804 forwards, arrow 304_f, the encountered user cells for further processing in the select arport and select the archer. A sync cell is terminated in the cell analysis function 804. The control data in the sync cell is extracted and if promptly indicated, cf. 4 and 5, a prompt signal 840 is transmitted to sync cell insertion function 808. An unknown control code causes the transmission of error signal 836 to sync state machine 806.

The flow of function of the sync state machine 806 is shown in the state diagram of Fig. 4. The following rules apply: if the sync compliance signal 828 occurs in the state SEARCH, it is brought to the state SEARCH. The nickel signal 834 together with the sync match signal 828 drives it to the SYNK state after two consecutive sync cells. If a monitoring function is used, it is reset by each new cell signal 834 together with the sync matching signal 828. Triggering the monitoring function brings the sync state machine to the SEARCH state. The sync state machine 806 outputs the search signal 826 to the S / P conversion and sync cell setting function 802 always when it is in the SEARCH state, and a sync signal 842 to the sync cell insertion function 808 always when it is in the SYNK state.

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Sync cell insertion function 808 uses sync signal 842 to generate, in a control code generator 844, the control code in the outgoing sync cells and to output mandatory sync cells 846 to a sync cell / user cell selector function 848 when the sync signal is deactivated In the selector function 848, a sync cell 846 is inserted into a stream 850 of user cells when the prompt signal 840 occurs. The cell stream 850 originates from a fifo 852 in which user cells entering according to arrow 304_t to the sync cell insertion function 808, stops when a sync cell is inserted into the selector function 848. The sync cell insertion function 808 uses the clock from the clock generator 810 to drive its logic, arrow 856.

The P / S converter 812 receives data in word format, arrow 858, and provides a serial bit stream which forms the output bit stream 822, for transmission on the link 206 to select the port or select the arc at a rate determined, arrow 860, by clock generator 810.

The clock generator 810 sets the bit clock and clocks off the bit stream blocks 822 in the outgoing direction. The clock generator 810 could use the incoming bit clock signal 818 to obtain the same speed in both directions, as indicated by a dashed line 862. In this case, the other side must be clock master and generate the clock while the side using the incoming bit clock signal 818 of the output bit stream 822 is slave. In this case, the slave need not transmit with the clock signal 820 on the link 206.

Figure 9 shows the S / P conversion and sync cell setting function 802 in more detail. More specifically, it is shown as divided into a series / parallel converter 902 and a sync cell setting function 904, whereby internal logic is clarified.

The serial / parallel converter 902 contains a 16-bit shift register 906 and a 16-bit register 908. Controlled by the bit clock signal 818, the 16-bit shift register 906 converts the incoming bit stream into a 16-bit parallel format 910. As will be seen in more detail below, 16 the bit register normally of a setting clock signal 912 for every 16 bit clock pulses to complete the series / parallel conversion, and for each bit clock pulse while searching for the sync pattern.

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The sync cell setting function 904 contains a comparison function 913, a bit clock divider 914, in the form of a 4-bit counter, and a multiplexer 916 with some combinatorial logic. The comparison function 913 is connected to the output of the register 908 for sensing, arrow 918, of when the hexadecimal pattern C2F1 occurs in the word stream 824. In that case, the comparison function 913 outputs the sync matching signal 828, hereinafter also referred to as the equal signal, to the sync signal, 80. Fig. 8. The sync match signal 828 multiplied by the search signal 826 forms the sync start signal 830. This is symbolized by an AND function 920, both of which are connected to receive the sync match match signal 828 and the search signal 826, respectively, and at the output the sync start signal signal is output from the sync start signal 830.

The inverted sync matching signal 828 multiplied by the search signal 826 controls the multiplexer 916. This is symbolized by an AND function 922 with an input connected to receive the search signal 826 and an inverting input connected to receive the sync correspondence signal 828 and the output 922 of the output 922. of the multiplexer 916. The multiplexer 916 is connected for receiving the bit clock signal 818 and an output 928 at the output of an AND gate 929, whose inputs receive each of the four bits appearing on the counter 914 outputs. When the search signal 826 but not the sync match signal 828 occurs, i.e. AND output 924 of the AND function 924 goes high, the bit clock signal 818 is selected by the multiplexer 916 as the setting clock signal at the clock input 912 of the register 908. When both the search signal 826 and the sync match signal 828 occur, ie. AND the output of function 922 becomes low, the signal 928 derived from the bit clock divider 914 is selected as the setting clock signal. This derived clock signal is active every 16th part of the time.

The bit clock divider 914's 4-bit counter counts one step for each bit clock pulse. The bits appearing on the four outputs of the bit clock divider 914 are indicated by b0, b1, b2 and b3. The most significant bit b3 is used as the word clock signal 832. The bit clock divider 914 has a reset input 932 connected to AND function 922 output 924. The bit clock divider is reset when output 924 goes high due to the lack of signal sync over 506 540 unity 828 on the inverting input of AND function 922, ie. when the bit clock signal 818 is selected as the setting clock signal. When the sync pattern was found, ie. output 924 goes low because the sync matching signal 828 appears on the inverting input of AND function 922, the bit clock divider 932 begins to count, with a restart after 16 steps.

A further example of a state machine and a transaction transition diagram between selector port and selector core for a possible synchronization and re-synchronization scenario according to this state machine will now be described in more detail with reference to Figures 10 and 11.

In the present example, the following states and corresponding codes are to be transmitted and, on the receiving side, result in the simultaneously specified measures:

- SYNC. Indicates to the receiving page that the originating page is in SYNK state.

- SUPPLY. Informs the receiving page that the originating page is in DELETE state and wants a synchronization cell in return at the first appropriate time. The returned sync cell should be inserted into the normal cell stream so that it causes as little disruption to normal operation as possible.

Fig. 10 shows the sync state diagram of a page.

The incoming sync cells from the opposite side of the link are compared to the predetermined pattern of sync cells. In DELETE state 1002 and after three consecutive synchronization cells, arrow 1004 enters SYNK state 1006. In SYNK state 1006, user cells can start flowing. The user cell contains information about its size, which is used to maintain the cell synchronization in the SYNK state. A detected error in the user cells directly brings the sync state machine to SUPPLY state 1002 according to arrow 1008.

In order to achieve fast synchronization and keep the link in operational state, it is necessary that the opposite side state can be transmitted in the synchronization cells. The states are specified in the sync cell specification.

The following synchronization cell transition rules apply to the sync state machine:

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- In the DELAY state. Send sync cells to the opposite page with the DELAY state indication. The selector core should terminate an ongoing transfer of user cells to the selector port. Select the port allowed to cancel or terminate an ongoing transfer to the selector core.

2-1 SYNC condition. Allow transfer of user cells. Received synchronization cells, which indicate SUPPLY state, should result in a corresponding synchronization cell after the ongoing transfer of user cells is completed.

- Consecutive synchronization cells indicating SUPPLY state must be matched by a consecutive stream of synchronization cells following the permissible initial delay caused by an ongoing transfer of a user cell.

- Select the arport to send sync cells, which simulate the SUPPLY condition, on a regular basis, to verify in the SYNK state that the selected archer is in true sync state.

In Fig. 11, both sides are first in SUPPLY condition. Accordingly, they transmit synchronization cells, generally indicated by 1102, with the SUPPLY state. After the defined number of consecutive sync cells, both sides enter the SYNK state, which can occur at different times. In the example shown in the figure, the selector core 1104 first enters the SYNK state, arrow 1106, before the selector gate 1108. Therefore, the caster 1104 responds to its three received, state SUPPLY indicating synchronization cells by transmitting, arrow 1110, a synchronization cell indicating the SYNC state for each received synchronization cell indicating the DELAY state. After at least three consecutive synchronization cells 1102 emitted by the core core 1104, the selector port 1108 enters the SYNK state, arrow 1112. Selector port 1108 now begins to transmit user cells, arrow 1114, since no synchronization cells with the SUPPLY state come from the core core 1104. The now user cells receiving the core core 1104 may in turn allow the transmission of user cells, arrow 1116. The link is now operational on both sides and will so stay until either side enters the DELAY state due to some detected error.

In this example, selector port 1108 detects an error in a received user cell, arrow 1118, and passes, arrow 1120, to

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PRESYNC state. Selector port 1108 now outputs synchronization cells with the SUPPLY state, arrow 1122. Selector core 1104 must now respond, arrow 1124, by transmitting synchronization cells indicating the SYNK state, arrow 1126, instead of user cells. After the required number of synchronization cells resumes, arrow 1128, selector port 1108 SYNK state. The two sides then return to sending user cells to each other, double arrow 1130.

Corresponding process where selector core 1104 detects an error in a received user cell, arrow 1132, is also indicated. It passes, arrow 1134, to the SUPPLY state and outputs synchronization cells indicating the SUPPLY state, arrow 1136. Selector port 1108 must now respond, arrow 1138, by transmitting synchronization cells indicating the SYNK state, arrow 1140, instead of user cells. After the required number of synchronization cells, arrow 1142, selector core 1104 resumes the synchronization state. The two sides then return to sending user cells to each other according to double arrow 1144.

Theoretically, there is little likelihood of the voter core switching to a false SYNK state. This means that the synchronization is lost, but not detected. The cause may be a correct synchronization pattern in the user cells or an incorrect user cell head. This situation could theoretically extend over a long period of time. In order to deal with such a situation, during normal operation, the selector gate 1108 can check that the selector core 1104 is actually in the SYNC state by regularly sending sync cells, arrow 1146, the simulate state SUPPLY. Selector core 1104 must respond, within a given time period, after ongoing user cell transfer, arrow 1148, with a synchronization cell with the SYNK state, arrow 1150. If this does not happen, it can be assumed that the selector core is in some sort of false SYNK state.

If no synchronization cell is returned, the transmission of user cells is terminated and the selector port side is forced into synchronism.

During normal operation, the selector gate can also ensure that its own terminating side is in true SYNK state by simply holding the synchronization cells in the simulated state SUPPLY for a period of time corresponding to at least the longest user cell type.

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With reference to Figs. 12-15, a more detailed description of a modification of part of the link control function of Figs. 8 and 9 will now be given. common to this prior embodiment. An incoming serial bit stream must be synchronized, whereby the serial data is converted to 16-bit parallel data, and during the synchronization process the data is set to correct cell boundaries. The incoming clock speed is divided into the clock speed of the clock signal (s) used in the selector core. In the outgoing direction, towards the selector port, the outgoing 16-bit parallel data is converted into a serial bit stream.

In Fig. 13, the same or corresponding parts as in Figs. 8 and 9 have been given the same reference numerals.

As will be seen, the embodiment of Figs. 12-15 is based on the realization that the fastest possible cell synchronization using the least amount of chip area can be achieved by using only a 16-bit comparator 913 and making synchronization pattern comparisons every clock cycle. Comparator 913 compares 16-bit data from serial / parallel converter 908 to the pattern to be included in the first 16 bits of the synchronization cell. The synchronization state machine 806, with reference to Fig. 12, keeps track of the four synchronization states, namely SÖK 1202, first SUPPLY 1204, second SUPPLY 1206 and SYNK 1208.

In the SEARCH state 1202, the link synchronization process is active. When comparator 913 indicates a pattern similarity, the process switches to the first SUPPLY state 1204, arrow 1210. After three consecutive pattern similarities are reached, arrows 1212 and 1214, SYNC state 1208 and normal operation can begin.

In the SYNK 1208 and SUPPLY 1204/1206 states, the output register 908 is loaded into the serial / parallel converter 902 only every 16 data bit cycles, so that a completely new 16-bit word is given after every 16 data bits. During the synchronization process, on the other hand, register 908 should instead clock each clock cycle (by the data clock 818 from the selector port). As a result, the bits in the incoming serial data stream 816 shift two bit positions for each data clock cycle (two bits because the data from the selector port changes on both clock flanks), with a new bit in bit position 0 and bit position 1. During each clock cycle,

506 540 comparator 913 of the outgoing word stream following the synchronization pattern. At pattern similarity, signal 828 is output, which starts normal operation of the synchronization unit. This means that the register 908 is stopped from charging each clock cycle, a transition to the first SUPPLY state 1204 occurs according to arrow 1210, and the clock divider 914 reset during the link synchronization process starts counting from 0 up to 15. If the next cell is also a synchronization cell, the second SUPPLY state 1206 is achieved according to arrow 1212, otherwise return to the SEARCH state 1202 according to arrow 1216 occurs and the link synchronization process begins again. After three consecutive synchronization pattern similarities, the process switches to state SYNK 1208, arrow 1214, otherwise return to SEARCH state 1202 according to arrow 1218 and the link synchronization process begins. Return to SEARCH state 1202 from SYNK state 1208 occurs when the cell analyzer 804 indicates that a parity error or some other error has been detected in a cell.

With the described synchronization method, all 16 possible bit positions in a cell will have been tested as starting positions within a cell cycle. Only the 16 bits on the positive edge of the data clock are tested.

The cell synchronization unit of Fig. 13 utilizes both clock flanks of the data clock from the selector port. The first bit of each user cell received from the select port should appear on the positive clock flange.

The clock divider 914 is a 4-bit counter used to generate the various clock signals used in the selector core. Enumeration occurs on the conductive edge of the data clock signal 818, but only if the reset signal at reset input 932 is not active. In the SUPPLY and SYNK states 1204/1206 and 1, respectively. In 1208, the counter 914 counts from 0 up to 15 and then starts from 0 again. During the SEARCH state 1202, the reset input 932 is activated. Synchronous counting / resetting occurs on the leading edge of data clock 818.

The sink state machine 806 contains a two-bit counter 1302, which at its count input 1304 receives bit 2 from the clock divider 914 and keeps track of the current synchronization state. As also highlighted in Figure 12, 00 SEARCH states, 01 means first SUPPLY state, 10 second SUPPLY state, and 11

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SYNC state. The four states are indicated at the output of the counter 1302 in Fig. 12 with = 0, = 1, = 2 and 2, respectively. = 3rd Synchronous counting occurs on the rear edge of the clock signal when the count is activated by an activation input 1306 being high. Synchronous resetting occurs on the rear edge of the clock signal if a reset input 1308 is activated.

Enumeration is enabled when:

- SEARCH state 1202 is present and an equal signal 828 is present from comparator 913 on the activation input 1306,

- Delay state exists and equal signal 828 appears on the activation input 1306 during the first word of a new cell.

Reset is enabled when:

SYNK state 1208 exists and error indication 836 is obtained from cell analyzer 804,

- Delay state exists and equal signal 828 is not obtained from comparator 913 during the first word of a cell.

Details of how the above-described functions of the sync state machine are achieved will be appreciated by those skilled in the art by means of the logic blocks shown in Figs. 13 at 1310, 1312 and 1314 in more detail and their mutual and external connections, the latter with reference numerals introduced from Fig. 8. .

The serial / parallel converter 902 converts the serial bit stream into 16-bit parallel data. It consists of two 8-bit shift registers 906.1 and 906.2, and a 16-bit register 908. The shift register 906.1 is clocked on the leading edge of the bit clock 818, the shift register 906.2 clocked on the rear flank. The result is that each of the shift registers 906.1 and

906.2 is clocked every other bit cycle. This means that when sixteen bits are received, bits 1, 3 .... 15 are in register 906.1 and bits 2, 4 .... 16 in register 906.2 (bit 1 is received first, bit 16 last). The first bit, ie. bit 1, to be received on the positive edge by bit clock 818.

After sixteen bits are received, the 16-bit register 908 is charged. Synchronous charging occurs on the conductive edge of the bit clock signal 818 on a clock input 1316 if the charge input 912 is activated. The charge input 912 must be activated via the logic function 916 each time the clock divider 914 has the value 7, or if SÖK506 540 state exists according to the output of AND gate 922. 16-bit input data to register 908 is selected from the 2 x 8 bits of parallel output data from shift registers 906.1, 906.2 in such a way that bit positions 1, 3 ... 15 are selected from 906.1 and bit positions 2, 4 ... 16 from 906.2.

In addition to the inverting input of signal 828 from comparator 913 and input of signal 826, AND gate 922 also has an inverting input of a user cell signal 1318 from sync cell generator 844. This signal 1318 indicates that a user cell is being transferred to the selector port. When an error has occurred and a change to the SEARCH state has occurred, the re-synchronization process will not begin until the cell transfer to the selector port is complete.

The parallel / serial converter 812 converts 16-bit parallel output to the serial bit stream 822 toward the selector port. It consists of two 8-bit shift registers 812.1 and 812.2 and a multiplexer 1320. Both shift registers 812.1 and 812.2 are simultaneously loaded by the bit clock signal 818 on clock inputs 1322 and 812, respectively. 1324 on charge inputs 1326 and 1326 respectively. 1328 from the output 928 of the clock divider 914 is activated. The charge input must be activated each time the 4bit counter 914 has the value 7 or 15, at its output, which is also connected to the charge inputs 1326 and 1328 as above. Bits 1, 3 ... 15 of the 16 bit parallel output data are loaded into the 812.1 2, 4 ... 16 are loaded into 812.2. Both shift registers 812.1 and 812.2 are clocked (shifted) on the conductive edge of the bit clock 818, which means that they are only shifted every other bit cycle. No change is made about the charging input 1326 and 1326 respectively. 1328 years activated.

The multiplexer 1320 uses the bit clock at 1330 to select between the outputs of the two shift registers 812.1 and 812.2. If the bit clock = 1, 812.1 is selected, if the bit clock = 0, 812.2 is selected. The result is that after loading the 16 bits of output, the first bit 1 will be transmitted to the selector port, then bit 2, whereupon the shift register changes data, and bit 3 is transmitted, then bit 4, and so on.

Selector block 913 compares the parallel input data with the predetermined pattern of the first 16 bits of the synchronization cell (hex'C2F1 '). When the pattern fits, the equal signal 828 is transmitted.

The time diagrams in Figures 14 and 15 show the timing of the link synchronization process.

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In Figure 14, the row shows:

bit clock signal 818, data out of register 906.1, data out of register 906.2.

the activation signal into charge input 912 of 16-bit register 908, parallel data 824 out of register 908, equal signal 828, sync state signal 842 from sync state machine 806, counter signal 928 from 4-bit counter 914, bit-2 signal 1304 from 4-bit counter 914 counter input of counter 1302.

It is apparent from rows 1-3 in Fig. 14 how the shift registers 906.1 and 906.2 shift on each positive clock edge 1402 and negative clock edge 1404, respectively, of the signal 818. First, the synchronization unit is in the SEARCH state 1202 (Fig. 12), marked at 1406 on row seven in the chart, and therefore register 908 is loaded on each positive clock edge. Each clock cycle, comparison circuit 913 scans parallel data 824 to find the synchronization pattern hex'C2F1 '. After a few clock cycles, the pattern is found, at 1408 on line 5, which is indicated by the equal signal 828 appearing on row six in the diagram, at 1410. The beginning of the equal signal 828 is shaded, at 1412, to indicate that it takes some time to make the comparison and to prevent register 908 from being loaded during the next clock cycle again. The delay must be less than one data clock cycle. When equal signal 828 has occurred, counter 914 begins to count, at 1414 on line 8. The synchronization state DELAY occurs, marked at 1416 on line 7, when the 4-bit counter 914 has the value 7 on its output 928. After three consecutive sync cells, the transition to the synchronization state will occur, as described below with reference to Fig. 15.

Figure 15 shows what happens if a failure of a cell has been detected by the cell analysis function 804. In the figure, the row indicates:

the signal 912 into the register input 908 of the register 908, the word stream 824 out of the register 908, the word clock 832, ie. bit 3 out of clock divider 914, error signal 836 from cell analysis function 804 to

506 540 sync state machine 806, sync state signal 842 from sync state machine 806 to sync cell entry block 808, user cell signal 1318 from sync cell generator 844, equal signal 828 from comparison function 913.

When a failure of a cell has been detected by the cell analysis function 804, cf. row 4 at 1502, a transition to the SEARCH permit is made, cf. line 5 at 1504. Because the ongoing user cell signal 1318 from sync cell generator 844 indicates that a cell is currently being transmitted to the selector port, the synchronization process does not start immediately. Only when the ongoing user cell signal 1318 ceases, indicated at 1506 on line 6, and thus the shift register 908 receives the charge signal 912 at its charge input, marked at 1508, begins the search for synchronization. In line 2, this is evident from the rapidly changing course at 1510 of signal 824. In this case, it takes 16 bit clock cycles before equal signal 828 indicates, at 1512 on line 7, that the pattern at 1514 on line 2 fits. Transition to state SUPPLY occurs at 1516 on line 5. After the three consecutive equal signals 1512, 1518, 1520, the synchronization state SYNK occurs, at 1522, line 5.

The delays through gates included in Fig. 13 are very critical during the synchronization process. If a data rate of 200 Mbit / s is used, each clock period is only 10 ns long. The search for the synchronization pattern and the stopping of the charge activation signal 912 to the register 908 and the reset signal 932 to the clock divider 914 must occur in less than this time.

The delay for a gate is approximately 0.3 ns. The number of gate levels from the input of comparator 913 to register 908 charge input 912 and reset input 932 of clock divider 914 is about 5-6, which means less than 1.8 ns.

The above-described cell synchronization according to the invention is required because the cell clock is not transmitted. Link control could probably be largely avoided if a clock indicating start for each new cell was signaled over the link on both sides. However, in a cell-based selector, it is desirable to be able to produce the selector core in a

506 540 chip, where each pin, however, involves a cost. Using the above-described method of the invention, including selecting the arcs to be made into bells, only half of the pins are required for a link.

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