Synchronization apparatus in transmitting information on a simplex bus.

(54) Name: Device for synchronization when transmitting information on a one-way bus (56) Published publications: --- (57) Summary:

The invention relates to a device for synchronization in a time-multiplex type telecommunication system in which information is transmitted in allocated time slots, in unidirectional data transmission between a number of equal transmitter / receiver modules (AN) connected to a common bus. The bus is divided into three parts, all transmitters (S) being successively connected to the first part of the bus (B1) and all receivers (R) being connected to the end of the bus (B3) in the same order as the transmitters. The delay in time between the transmitters and the bus is the same for all the transmitters and constitutes a fixed value whereby the total delay on the first part of the bus is determined by the number of connected transmitters. The same applies to the recipients, so that the delay on the bus end portion (B3) is also a fixed value. The bus intermediate portion (B2) extends from the last connected transmitter to the first connected receiver and is variable in its length in such a way that the length is adapted to give a selectable predetermined total delay between transmitter and receiver. in the same module. Each of the modules (AN) contains a local kiosk oscillator (CL) common to the respective transmitters and receivers. In addition to internal clock signals, the oscillator outputs each time the module is designated master, frame synchronization pulses (FS) for synchronization of other modules (slave modules). The synchronization pulses are transmitted a thread / frame and parallel to the data information from respective transmitters (S). By means of the device according to the invention, a synchronization method is obtained which allows the transmission of a first information between an arbitrarily selected module pair and a second information between another arbitrarily chosen module pair using two adjacent time slots without time difference between the transmission processes in the respective time slot.

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TECHNICAL FIELD

The invention relates to a device for synchronization in a time-multiplex type telecommunication system in which information is transmitted in allocated time slots, in unidirectional data transmission between a number of equal transmitter / receiver modules connected to a common bus.

BACKGROUND OF THE INVENTION

In order to ensure that the data transmission takes place in a timely manner, signals for synchronization between transmitter and receiver must also be sent out on the bus.

In known devices, see for example LME description X / Yg 118909 Ue regarding the RP bus (Regional Processor) in the telephone station AXE 110, a separate clock equipment for the bus is used, which means that the information is deliberately delayed and clocked out on the bus by means of the separate clock signal unit .

DISCLOSURE OF THE INVENTION

In the known device, a combination of transmitters and receivers in the same module requires separate clock signals and possibly clock oscillators in both the transmitters and receivers for synchronization with the bus. This results in a delay in the transmission of information, poor capacity utilization on the bus and a complicated hardware structure. Furthermore, when centralizing the clock signals, it is difficult to achieve high reliability.

The device which solves said problems is characterized by the claims and consists of a bus intended for unidirectional information transmission, which is connected to a number of modules, each of which comprises a transmitter and a receiver. An arbitrarily selected module is a master module and in addition to data also sends synchronization pulses to the other modules (slave modules). The synchronization pulses are used to determine time slots in the time multiplex system.

Considering the direction of transmission, all transmitters are successively connected to the start of the bus, while all receivers are connected to the end of the bus in the same order as the transmitters. This allows the start of the bus and

8202577-6 end part can be placed in parallel conductors in the same cable. The bus intermediate part:

in which extends from the last connected transmitter to the first connected | the receiver, is so dimensioned that the delay through the bus during information transmission from the transmitter to the receiver in one and the same module, according to the example below, becomes at least one time slot or more. The delay can also, in some cases, be less than a time slot. Because the synchronization pulse and data information go the same way, each of the slave modules is synchronized to assume a relative phase position corresponding to its position on the bus. Thereby, data is clocked out in the same local clock phase regardless of the transmitter module, and clocked into the next local clock phase regardless of the receiver module. The delay through the bus with a time slot allows the same clock oscillator to be used for transmitters and receivers in a module. The bus arrangement and sizing make it possible to

In interference-free transmit an initial information between an arbitrarily selected module.

pairs and a second information between a second arbitrarily selected module pair using two adjacent time slots, and so on until all time slots are coated. '

The advantages of the device according to the invention over known devices are:

Better capacity utilization of the bus is achieved through the design of the bus and the synchronization procedure.

No reversing device on the bus intermediate part necessary. The transmitter and receiver clock are the same for each module, regardless of whether the module is master or slave, ie master and slave are equal, thereby achieving uniform hardware.

DESCRIPTION

The device according to the invention is described in more detail with the aid of an embodiment with reference to the accompanying drawing in which

Figure 1 is a simplified block diagram of the device according to the invention Figure 2 is a block diagram of the transmitter-receiver equipment included in each module and

Figure 3, which is a timing diagram showing how the data information and synchronization pulses behave temporarily during transmission between transmitter and receiver through the bus.

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PREFERRED EMBODIMENT

The bus is, as mentioned, divided into three parts, a first part B1 connected to the transmitter outputs of the modules, a second part consisting of a middle part B2 and a third part constituting the end part B3 of the bus and connected to the modules' input inputs.

The bus is suitable for high transmission speed, for example 8 MHz bus clock frequency. If the delay is selected to a time slot, it will be relatively short 125 nS, relative to an entire frame.

As mentioned earlier, a certain delay time is determined, for example, corresponding to a time slot between transmitter and receiver in the same module. The same 1q delay time applies to any transmission, that is, whatever module is transmitter and which module is receiver, by transmitting a synchronization pulse sent from the master module in parallel with the data signals from the respective transmitter module. Said delay time is determined by the different parts of the bus B1, B2, B3. The bus portions B1 and B3 consist of parallel wires in the same cable, and provide a fixed delay time depending on the number of cuts, ie how many modules comprising both bed transmitters and receivers connected to the bus. Since the number of cuts can vary and. hence the fixed part of the delay time, then the center portion B2 of the bus is variable and is adjusted to its length such that the desired total time delay of at least one time slot always 2q is achieved regardless of the fixed delay in the bus parts B1 and B3. The cable length from transmitter to bus and from bus to receiver is also predetermined. The bus may consist of a cable bus with cable connectors as connectors.

As shown in Figure 1, a number of modules AN, each containing a transmitter S and a receiver R, are connected to a common bus. The bus is divided into three parts, a first part B1, which constitutes the beginning of the bus, to which all transmitters S are connected, a second part B2 constituting the middle part of the bus and a third part B3, the end part of the bus, to which all receivers R are connected. The transmitters are connected to! the bus in a fixed order and the receivers are connected to the bus in the same order.

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Namely, to achieve the object of the invention, to provide a synchronization method which permits interchange of. information between arbitrary transmitters and receivers in adjacent time slots without time gap, the device according to the invention comprises, in addition to said bus arrangement, equipment in said modules AN.

As shown in Figure 2, each module AN contains a time slot memory TM of type INTEL 2148 in which data from, respectively, to the bus are read and read under the control of signals from a continuously increasing time slot counter TSC of type 74LS161 and a control memory CM of type INTEL 2148. The time slot10 counter is controlled by a local clock oscillator CL of the type MOTOROLA MC 4024, which belongs to the module and common to transmitters and receivers, which also generates synchronization pulses FS for the bus and also other internal control signals. The control memory CM is controlled in a known manner by a microprocessor CP of type MOTOROLA 6801 not shown in the figure.

When transmitted to the bus, the control memory CM, upon clocking from the time slot counter, issues addresses to the time slot memory TM so that data can switch time slot in the time multiplex system. The address points out the cell in memory TM from which data is to be read out during the current time slot. The data outputs of the memory TM are connected to the inputs of a holding circuit L1 in the form of a D flip-flop of type 74LS373, in which data is stored for output at the correct time to the inputs of a bus transmitter BS of type AMD 26LS31. Output of data from the holding circuit L1 is controlled by a continuously clocked internal clock signal CS continuously output via the time slot counter TSC. From the control memory CM, a signal TE (time slot enable) is output via the holding circuit to an input of the bus transmitter, thereby controlling the output of synchronization pulse and data from the bus transmitter BS to the bus. The oscillator CL delivers synchronization pulse to the bus via the time slot counter TSC once per frame to synchronize the time slots. The frame synchronization pulse FS is transmitted in time slot 0 (zero) to one input of an AND circuit 01, the other of which receives the continuously transmitted internal clock signal from an output of the time slot counter TSC, the same signal that controls the output of data from the holding circuit L1. The AND circuit is activated once each frame, thereby delivering the synchronization pulse to the bus transmitter. Only the module designated as the master delivers synchronization pulses to the bus. Receiving data and synchronization pulses from the bus to the module takes place continuously in a bus receiver BR

8202577-6 of type AMD 26LS32, · which at its outputs output data to the inputs of a further pouring circuit L2 a D flip-flop of type 74LS373. The information is clocked into the holding circuit under the control of the internal clock signal CS, which is the same signal that clocks data to the bus, but since the information is delayed by the bus with a time slot, the internal clock signal is in this case inverted by an inversion circuit I, the same basic clock signal. thus controls both disabling and clocking data to and from the bus respectively. The phase ratio of the clock signals depends on the size of the delay through the bus. The holding circuit L2 has outputs connected to inputs on the time slot memory TM. When the information in the holding circuit is to be entered into the time slot memory TM, this is controlled by a signal DS (Data Select) from the control memory CM to the holding circuit L2, whereby the clock signals from the time slot counter TSC serve as pointers for entering the correct address in the memory.

From the output of the bus receiver BR, the frame synchronization pulse transmitted by the bus is taken out and a first input is applied to a phase comparator PC of type MC4044. A second input to the phase comparator is supplied by the frame oscillator pulse FS generated by the local oscillator CL generated by the time slot counter. Thus, in the known phase comparator PC, a comparison is made between the phase position of the locally generated synchronization pulse and the synchronization pulse transmitted by the bus. The comparison result is a voltage U which is used to control the frequency 'of the clock oscillator CL so that it is always stable. The clock frequency increases and decreases, respectively, depending on how the mutual phase position of the two signals varies, and thus the resulting voltage U.

Figure 3 is a time diagram showing how a module A transmits in a time slot and receives its own information in the receiver a time slot later. As mentioned above, in order to be able to clock the received information in the middle of the data pulse, the inverted transmit clock signal should be used.

The figure also shows how the frame synchronization pulse FS moves temporally from the transmitter in a master module B, through the bus to the receivers A, B and C.

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As shown in Figure 2, slave receiver A receives this frame synchronization pulse and makes a phase comparison with its own local clock. If the phase mode is not correct, the phase is controlled so that the synchronization pulse comes in the middle of the own time slot 0 (zero).

As a further feature of Figure 3, the relative phase states are always the same.

The delay is apparently a time slot. The timing at which the information is to be transmitted and received in the various modules is dependent on the position of the transmitters and receivers on the bus. Therefore, since all the receivers are lagging behind the transmitters, it is possible to start transmitting in a time slot before transmitting information from the previous time slot. This is an advantage that, for example, is not possible to achieve in a ring bus.

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