Synchronization apparatus in transmitting information on a simplex bus

Technical field

0001The invention relates to a synchronization apparatus in a telecommunication system of the time division multiplex (TDM) type in which information is transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules connected to a common bus.

Background art

0002In order to achieve data transmission correctly in time, signals for synchronizing between transmitter and receiver must also be sent out on the bus.

0003In known apparatus, as for example in the LM Ericsson Company Description with the catalogue code X/Yg 118909 Ue relating to the regional processor bus in the AXE 110 telephone exchange, separate clock equipment is utilized for the bus, which means that the information is intentionally delayed and clocked out on the bus with the aid of the separate clock signal unit.

Disclosure of invention

0004For a combination of transmitter and receiver in the same module, in the known apparatus there are required separate clock signals and possibly clock oscillators in both transmitters and receivers for synchronizing towards the bus. This results in delay in the information transmission, poor capacity utilization on the bus and a complicated hardware structure. Furthermore, it is difficult to achieve great reliability with central feeding of clock signals.

0005The apparatus solving the mentioned problem is characterized by the claims, and consists of a bus intended for simplex information transmission connected to a plurality of modules, each of which includes a transmitter and a receiver. An arbitrarily selected module constitutes the master module, and sends synchronizing pulses as well as data to the other modules (slave modules). The synchronizing pulses are used to establish time slots in the TDM system.

0006With respect to the transmission direction, all the transmitters are successively connected to the starting section of the bus, while all receivers are connected to the final section thereof in the same order as the transmitters. This enables disposing the starting and final sections in parallel conductors in the same cable. The intermediate section of the bus, extending from the last connected transmitter to the first connected receiver is dimensioned such that the delay of information through the bus for transmission from transmitter to receiver in one and the same module, in accordance with the example below, will be at least one time slot or more. The time delay can also be less than one time slot in certain cases. Since the synchronizing pulse and the data information travel the same way, each of the slave modules is synchronized to assume a relative phase position corresponding to its position on the bus. Data is thus clocked-out in the same local clock phase irrespective of the transmitter module, and is clocked- in in the next local clock phase irrespective of receiver module. The one time slot delay through the bus allows the same clock oscillator to be utilized for both transmitter and receiver in a module. The arrangement and dimensioning of the bus enables interferencefree transmission of first information between an arbitrarily selected module pair, and second information between a second arbitrarily selected module pairwhile using two mutually adjacent time slots, and so on until all time slots are occupied.

0007The advantages of the apparatus in accordance with the invention over known apparatus are: Better bus capacity utilization is obtained by the implementation of the bus and the synchronizing method.

0008No re-clocking unit on the bus intermediate section is necessary. Transmitter and receiver clocks are the same for the respective module, irrespective of whether the module is a master or a slave, i.e. master and slave are alike, unified hardware thus being obtained.

Description of figures

0009The apparatus in accordance with the invention is described in detail below with the aid of an embodiment and with reference to the appended drawing, on which Fig. 1 is a simplified block diagram of the apparatus in accordance with the invention, <ul id="ul0001" list-style="none"><li>Fig. 2 is a block diagram of the transmitter/ receiver equipment included in the respective module and,</li><li>Fig. 3 is a timing chart illustrating how the data information and synchronizing pulses occur in time during transmission through the bus between transmitter and receiver.</li></ul>

Preferred embodiment

0010As mentioned, the bus is divided into three sections, a first section B1 connected to the transmitter outputs of the modules, a second intermediate section B2 and a third final section B3, which is connected to the receiver inputs of the modules.

0011The bus is adapted for a high transmission rate, e.g. 8 M Hz bus clocking frequency. If the time delay is selected as one time slot, it will be 125 ns, which is comparatively short in relation to a whole frame.

0012As mentioned previously, a given time delay is decided, e.g. corresponding to one time slot between the transmitter and receiver in the same module. The same time delay applies to arbitrary transmission, i.e. irrespective of what module is the transmitter and what module is the receiver, by a synchronizing pulse sent from the master module being transmitted parallel to the data signals from the respective transmitter module. Said time delay is determined by the different sections B1, B2, B3 of the bus. The sections B1 and B3 consist of parallel conductors in the same cable, and give a fixed time delay depending on the number of modules comprising both transmitter and receiver that are connected to the bus. Since the number of modules can vary, and thereby the fixed part of the time delay, the intermediate section B2 of the bus is variable and is adjustable in length so that the desired combined time delay of at least one time slot is always achieved independent of the fixed time delay in the bus sections B1 and B3.

0013The cable length from transmitter to bus and from bus to receiver is also predetermined. The bus may be a cable bus with cable contacts as connection means.

0014As will be seen from Fig. 1, a number of modules A-N are connected to a common bus, each module containing a transmitter S and a receiver R. The bus is divided into three sections, a first section B1 at the start of the bus to which all transmitters S are connected, a second section B2 consisting of the intermediate section of the bus, and a third section B2 which is the final section to which all receivers R are connected. The transmitters are connected to the bus in a definite order and the receivers are connected to the bus in this same order.

0015In order to achieve the object of the invention, namely the provision of a synchronization method allowing exchange of information between arbitrary transmitters and receivers in adjacent time slots without play in time, the apparatus in accordance with the invention also includes equipment in said modules A-N, apart from said bus arrangement.

0016As will be seen from Fig. 2, each module A-N includes a time slot memory TM of the INTEL 2148 type, in which data from and to the bus is respectively read in and read out under control by signals from a continuously stepping time slot counter TSC of the type 74LD161 and a control memory CM of the type INTEL 2148. The time slot counter is controlled by a clock signal unit in the form of a local clock oscillator CL of the type MOTOROLA MC 4024, associated with the module and common to transmitter and receiver, this oscillator also generating synchronization pulses FS to the bus, and also generating remaining internal control signals. The control memory CM is conventionally controlled by a signal CP from a microprocessor of the type MOTOROLA 6801, not shown in the Figure.

0017For transmission to the bus, the control memory CM sends addresses to the time slot memory TM on clocking from the time slot counter, so that data can change time slot in the TDM system. The address points out the cell in the memory TM from which data is to be read out during the appropriate time slot. The data outputs from the memory TM are connected to the inputs on a latch circuit L1 in the form of a D flipflop of the type 74LS373, in which data is stored for feeding out in the right moment to the inputs on a bus transmitter BS of the type AMD 26LS31. Feeding out data from the latch circuit L1 is done under the control of an internal clock signal CS continuously fed out via the time slot counter TSC. A signal TE (time slot enable) is fed from the control memory CM via the latch circuit to an input of the bus transmitter, thus controlling the feed-out of synchronization pulse and data from the bus transmitter BS to the bus. The oscillator CL delivers a synchronization pulse to the bus once per frame via the time slot counter TSC to synchronize the time slots. The frame synchronization pulse FS is transferred in time slot 0 (zero) to one input of an AND circuit 01, the other input of which obtains the continuously sent internal clock signal from an output of the time slot counter TSC, which is the same signal controlling the feed-out of data from the latch circuit L1.The AND circuit is activated once per frame for sending the synchronization pulse to the bus transmitter. It is only the module selected as master which delivers synchronization pulses to the bus. Reception of data and synchronization pulses from the bus to the module takes place continuously in a bus receiver B R of the type AMD 26LS32, which sends from its outputs data to the inputs of a further latch circuit L2, a D-flipflop of the type 74LS373. The information is clocked into the latch circuit under control of the internal clock signal CS, which is the same signal clocking out data to the bus, but since the information through the bus is delayed by one time slot the internal clock signal in this case is inverted by an inverting circuit I, the same basic clock signal thus controlling both clocking-out and clocking-in of data respectively to and from the bus. The phase relationship between the clock signals is dependent on the size of the delay through the bus. The latch circuit L2 has outputs connected to inputs of the time slot memory TM. When the information in the latch circuit is to be fed into the time slot memory TM, the latter is controlled by a signal DS (Data Select) from the control memory CM to the latch circuit L2, the clock signals from the time slot counter TSC then serving as pointer for writing in the correct address in the memory.

0018The frame synchronization pulse sent through the bus is taken from an output of the bus receiver BR and applied to a first input of a phase comparator PC of the type MC 4044. The frame synchronization pulse FS generated by the local oscillator CL and fed out via the time slot counter is applied to a second input of the phase comparator. The latterthus conventionally makes a comparison between the phase position of the locally generated synchronizing pulse and the synchronizing pulse transmitted through the bus. The comparison result is a voltage U, which is utilized to control the frequency of the clock oscillator CL so that it is always stable. The clock frequency increases and decreases in response to how the relative phase position between the both signals varies, and thereby the resulting voltage U.

0019Fig. 3 is a timing chart illustrating how a module A transmits in a time slot and receives its own information in the receiver one time slot later. As previously mentioned, the inverted transmitter clock signal should be used for enabling clocking the received information in the middle of the data pulse.

0020The chart also illustrates how the frame synchronization pulse FS is displaced in time from the transmitter in a master module B through the bus to the receivers A, B and C.

0021As will be seen in Fig. 2, the slave receiver A receives this frame synchronization pulse and makes a phase comparison with its own local clock. If the phase position is not correct, the phase is controlled so that the synchronization pulse will appear in the middle of its own time slot 0 (zero).

0022As will further be seen from Fig. 3, the relative phase positions are the same all the time. The delay is one time slot, as will be seen. The instant when the information will start to be transmitted and re-. ceived in the different modules is dependent on the positions of the transmitters and receivers on the bus. Since all the receivers come after the transmitters in respect of delay, it is thus possible to begin transmission in one time slot before transmitted information from the preceding time slot has been received. This is an advantage which is not possible to achieve in a ring bus, for example.