Method and device for determining transmission speed of data conveyed at variable speed in communication system receiver

This invention relates to digital communication systems, and more particularly to a system in which variable rate data is transmitted without indicating the data rate and received in a communication receiver, wherein the transmission rate of the transmitted data is determined for use in processing data.

In digital communications systems, particularly in systems which use spread spectrum modulation, a transmitter may utilize vokodiruyuschuyu system which encodes voice information at a variable rate to lower the data rate during pauses or other cases where no voice activity thereby reducing interference level generated by the transmitter to receivers other than the one for which the transfer is intended. The system is used for vocoding voice data recovery at the receiver or other means associated with receiver system is used vocoding. It should be borne in mind that, in addition to the voice information can be transmitted to the receiver and the non-voice information, or a combination of speech and non-speech information.

Vocoder corresponding application under these conditions, is described in U.S. Patent 5414796 to "VARIABLE RATE VOCODER", the assignee of this invention. This vocoder produces from digital samples of the voice information encoded data at four different rates, eg approximately 8,000 bits per second (b / s), 4000 b / s 2000 b / s 1000 b / s, based on voice activity during a cycle duration 20 ms. Each group of vocoder data is formatted as an official group of bits of data in 9600, 4800, 2400 and 1200 b / s. Data Group the highest data rate corresponding to the group at 9600 b / s, is called the group "full rate", the band data at 4800 b / s - group "half rate", the band data at 2400 b / s - group " quarter rate ", and the band data at 1200 b / s - group" eighth rate ". Neither the coding process or during formatting data group rate information is not included in the data.

Detailed information about formatting vocoder data into groups of data are contained in the co-pending US patent application Serial 08/171146 of 21 December 1993, which is filed with the continuation of US patent application Serial 07 / 822.164 entitled "Method and apparatus for formatting data for transmission" of 16 January 1992, currently rejected, assigned to the assignee of the present invention. Further groups of data can be processed, spread spectrum modulated and transmitted in accordance with U.S. Patent 5,103,459 for "SYSTEM AND METHOD FOR GENERATING SIGNAL In cellular telephone systems, multiple access CDMA", dated 07 April 1992 and assigned to the assignee of the present invention .

Since rate information for each group of data is not transmitted, the receiver must determine from the received group of data the rate at which they are encoded for the vocoder to properly recover the voice information. The transmitter could transmit information regarding the rate at which a group of coded data, but this would reduce system resources available for transmitting voice and non-voice data. Also, distortions in the transmitted rate information would adversely affected the entire data group. Thus, it is desirable that the receiving device determines the rate at which the coded data groups without receiving from the transmitting device information about the speed. The present invention seeks to overcome these problems and disadvantages existing in the prior art.

The invention relates to a system for determining at a receiver of a communication system with variable data transmission rate of speed at which data is encoded by a transmitter of the communication system. Although the present invention can be used in various communication systems, it is particularly useful in cellular communication systems that use a variable rate vocoder for encoding and decoding speech from a plurality of discrete rates or in accordance with the transmission protocol data at a variable rate. Such communication systems include mobile telephones, personal communication, local wireless link, private telephone stations, especially those communication systems that use spread spectrum modulation. The present invention can be used in the receivers of both the mobile station and the mobile station or base station, or in cases when the receiving vocoder is located in a system such as a cellular telephone system to provide for the vocoder receiver information about the data rate, thereby vocoder to decode the encoded speech.

The present invention includes receiving the data group consisting of a predetermined number of symbols that represent speech, digitized and encoded by the vocoder, the transmitter for a predetermined period of time. Taking a group of data may consist of multiple copies of each symbol if the transmitter vocoder encoded the speech unit at a rate which is less than a predetermined maximum speed.

Each group received symbols decoded with each possible rate. Transmitted to a processor error metric that characterizes the quality of the decoded symbols for each data group decoded from each speed. Error metrics may include the results of cyclic redundancy check, a quality metric, and error rates Yamamoto characters. These error metrics are well-known in communications systems. The processor analyzes the error metric using the new decision procedure determines the most probable rate at which the incoming symbols were encoded. The processor may provide the rate information receiver vocoder or other devices.

The foregoing, together with other features and advantages of the present invention is explained below in the following description with reference to the drawings and the claims.

The invention is explained in the following description of exemplary embodiments illustrated in the drawings in which: FIG. 1 - block diagram illustrating the present invention when used in the receiver of a cellular telephone.

Figure 2 - a block diagram of an apparatus for determining the velocity of a base station receiver of a cellular telephone system.

FIG. 3 - block diagram of an apparatus for determining the velocity of a mobile station receiver of a cellular telephone system.

4 - block diagram of a rate determination procedures.

1 illustrates a digital communications system. For example this system is described here in the context of a cellular telephone system, multiple access CDMA. However, it should be understood that the invention is applicable to other types of communication systems such as personal communication systems, wireless local communication line, private telephone stations, and other known systems. In addition, the present invention can be used in other well known transmission modulation systems, such as multiple access with time division multiplexing. The system of FIG. 1 comprises a transmitter 10 and a receiver 12 which may be either a base station receiver or a mobile station receiver. Communication from transmitter 10 to receiver 12 when receiver 12 is disposed in a mobile station is performed on the forward link, and communication from transmitter 10 to receiver 12 when receiver 12 is disposed in the base station is carried out on the reverse link.

The transmitter 10 of the embodiment comprises a vocoder 14, which encodes voice data 16 for formatting the data groups with different data rates, for example the data rates of 9600, 4800, 2400 and 1200 b / s. Vocoder 14 selects a rate in response to the magnitude of voice activity in voice data 16, as described in said U.S. Patent 5,414,796, and suitably encodes voice data. 20 vocoder data bits are received and are fed to the speed modulator 18. Modulator 18 is described in the aforementioned U.S. Patent 5,103,459 Despite the fact that in the present invention are referred to four different rates and the data transmission should be borne in mind that the concepts of the present invention are applicable to systems , which can be used more or fewer data rates. It may also be used herein for example data rates and other data rates. For example, a set of transmission rates of data groups may include 14400, 7200, 3600 and 1800 b / s.

As an example for further clarification formatting data group is given the following information about a group of data. As mentioned above, all the data groups have a duration of 20 ms. Group full rate vocoder data consists of 160 data bits and 11 internal check bits. This group of full rate vocoder data is formatted by modulator 18 into a group of data transmission at 9600 b / s, consisting of 192 bits. These 192 bits are formed from the 171 bit data formed vocoder mode bit, 12-bit cyclic redundancy check (CRC) 8 tail bits. Group half rate vocoder data consists of 80 bits and may be formatted into a group of data transmission at 4800 b / s, consisting of 96 bits. Group data transmission at 4800 b / s consists of 80 bits of a vocoder and a CRC 8 bits and 8 tail bits. Group quarter rate vocoder data consists of 40 bits and may be formatted into a group of data transmission at 2400 b / s, or 48 bits. Group data transmission at 2400 b / s, together with 40 bits of vocoder includes 8 tail bits. Finally, a group of eighth rate data vovokdera consists of 16 bits and may be formatted into a group of data transfer rate of 1200 b / d of 24 bits. Group data transmission rate of 1200 b / d includes eight tail bits along with the 16 vocoder bits.

It will be appreciated that a combination of voice and non-voice data may be formatted into a group of data transmission at 9600 b / s, when there is vocoder data is less than the number at the full rate. A mode bit and additional overhead bits are included in this type of group data indicating the speed at which the encoded speech data. Regardless of the rate of the voice data in this type of data group, the group data in the form in which it is received, is defined as a group of data at 9600 b / s, comprising an amount of data less than full-rate vocoder data. As such, the overhead bits are used to fill the output data group indicating a full rate vocoder for processing of the portion of bits in the data group, which corresponds to the volume of vocoder data, is less than full-rate vocoder data group. Furthermore, it should be understood that the vocoder data may be replaced in a full-band data transmission of non-voice data. In this case, also included in the group of control bits identifying a data group of this type. In an alternative embodiment, variable rate data may comprise variable rate non-voice data. Non-voice data could be transmitted at a maximum rate as determined at the initiation of the transmission. During transmission, data could be transmitted at the maximum rate and lower velocities with several (sub-rates), similar in different rates used for voice data. A similar rate determination process would be used to determine the rate or sub-rate non-voice data transmitted.

Modulator 18 includes circuitry (not shown) which adds a bit cyclic redundancy check (CRC) and data groups full rate and half rate, and tail bits to all speeds groups (not shown) to vocoder data bits 20. Preferably, modulator 18 includes an encoder (not shown) which produces a convolutional encoding each group of data (not shown) for forming groups of data symbols. The forward link convolutional encoding is preferably performed with the half-rate, and the reverse link convolutional encoding is preferably performed at a rate of one third.

In each group, the symbol data striping is performed by an interleaver (not shown) preferably at the bit level to increase the diversification of time to correct errors. For groups of data corresponding to data rates less than the highest data rate, e.g., 9600 b / s, modulator 18 repeats symbol data to maintain a constant symbol rate for this data group. In other words, if the selected vocoder 14 speed less than that which corresponds to the speed band of 9600 b / d, modulator 18 repeats the symbols to fill in the data group number of repetitions depending on the speed of data transmission. For the data groups corresponding to a data rate of 9600 b / s, all symbols formed by the modulator 18 in the group of interleaved data. However, for the data groups corresponding to a data rate of 4800 b / s, a modulator 18 provides twice the symbols in the interleaved data group. Similarly, for the data groups corresponding to the data rate of 2400 b / s and 1200 b / s, the modulator respectively provides four or eight times in a group of data symbols interleaved. Thus, in this embodiment, a group of symbol data consists of 384 symbols for forward link channel (half-rate coding) for a symbol rate of 19200 symbols of the group / s.

Group character data modulated binary phase shift keying (DPSK) Orthogonal overlap in place with expansion by quadrature phase shift keying (QPSK), covered symbols as disclosed in U.S. Patent 5,103,459 The forward link modulator 18 transmits the group of data in a continuous stream modulated symbol data 22 with the transmit power of each group decreased in accordance with the repetition of characters in the data group.

In the reverse link modulator 18, along with the extension by means of QPSK modulation and BPSK, uses the orthogonal signaling data as described in U.S. Patent 5,103,459 Modulator 18 also includes a data burst randomizer (not shown) which transmits a data group 22. The character data package in detail the implementation of the data burst randomizer is described in co-pending US patent application Serial 08/194893 of February 14, 1994 which is filed with the continuation of US patent application Serial 07/846312 on "data burst randomizer" on March 5, 1992 currently rejected, and assigned to the assignee of the present invention. Through the data burst randomizer with incomplete data transmission rate is transmitted in the gated time segments. The ratio of these time segments of data packets to the total time is proportional to the data rate. Thus, in the present embodiment, a group of full-data consists of 576 symbols (encoding a third speed) to speed the groups of symbols 28800 symbols / s data group half rate consists of 288 symbols at a rate of the groups of symbols 28800 symbols / s, transmitted with 50 -protsentnym working cycle, a group of a quarter rate data consist of 144 symbols at a symbol rate of 28800 symbols of the group / s, transmitted with a 25 percent duty cycle, a group of eighth rate data consists of 72 symbols at a symbol rate of the group 28,800 s / s, transmitted with 12.5 percent duty cycle.

The receiving apparatus 12 comprises demodulator 26 for demodulating and removing interleaving the received symbol data 24. Demodulator 28 provides symbol data to decoder 30, which includes a system for measuring the speed of the present invention, respectively. The demodulated symbol data 28 are "programmable data solutions" because they are real component values ​​1 and 0, the received symbol data 24, which consist of the transmitted symbol data 22 and the interferences rather than being the binary representation of a decision on the most likely transmitted symbol.

The apparatus shown in Figure 2, determines a coding rate for data transmission on the forward link. Apparatus as shown in Figures 2 and 3 to facilitate understanding of the invention, has a plurality of parallel data channels. However, it should be understood that it is preferable to use a single channel to sharing elements to thereby reduce the number of such circuit elements. In such an embodiment, a joint using elements of demodulated symbol data is stored in the buffer unit (not shown) in the form in which they are received, and supplied to the processing channel for repeating the data for each possible data rate. The decoded output for each data rate is also stored until the rate is determined. The stored decoded output corresponding to the selected data rate is then passed to subsequent stages for further processing. In the present invention the parameters and data generated by this decoder are used to determine the speed of the data group transmitted data for each of the possible groups of data transmission rates.

As shown in Figure 2, demodulated symbol data 28 are supplied to each of the adders 34, 36 and 38. As stated above, for the groups of data transmitted on the forward link, symbols are repeated for the groups of data at a lower speed to obtain a constant amount of characters in the transmitted data group. To improve the quality of the repeated symbols are summed and scaled to the receiver in order to get for each set of repeated symbols a combined symbol representing the original symbol before repetition on the transmit side. The adder 38 sums every 8 symbols and provides a scaled total symbol data 40. Summer 36 sums every 4 symbols and provides a scaled total symbol data 42. Summer 34 sums every 2 symbols and provides scaled total symbol data 44. Thus, summers 34, 36 and 38 correspond to the data transmitted at a rate of half rate to eighth rate, respectively.

Each of four Viterbi decoders - 48, 50, 52 and 54 respectively, decode symbol data 28 and convolutionally-encoded scaled total symbol data 44, 42 and 40 to provide corresponding bit data. Viterbi decoders 52 and 54 include means for generating Yamamoto Quality Metrics 60 and 62, respectively, which is fed to the microprocessor 56 both of Q4 and Q8, respectively, Yamamoto Quality Metrics 60 and 62 individually are usually presented one-bit value for each data group. Yamamoto Quality Metric is a well known indicator of data quality. In other embodiments, Viterbi decoders 48 and 50 also may form Yamamoto quality metrics. However, since the data from the higher data rates, there are other more accurate indicators of quality, the use of Yamamoto Quality Metrics is generally not necessary. In other embodiments, Yamamoto Quality Metrics 60 and 62 may be formed circuit being external to Viterbi decoders 52 and 54.

As indicated above, each of the decoders 48-54 generates Viterbi decoded symbol data or bit data 68, 70, 72 and 74, respectively. Encoders 76, 78, 80 and 82 re-encode the decoded symbol data 68-74, respectively. Comparators 84, 86, 88, and 90 compare re-encoded bit data 92, 94, 96 and 98 to demodulated symbol data 28, scaled summary character data 44, 42 and 40, respectively. Counters 100, 102, 104 and 106 count the number of characters that are incompatible with each other. Counters 100-106 form a symbol error coefficients 108, 110, 112 and 114, respectively, each represented by an eight value. Symbol error rate 108-114 represent the number of inconsistencies in the data group and supplied to the microprocessor 56 as the S1,, and respectively.

<IMG>

<IMG>

<IMG>

Circuits 116 and 118, the CRC check CRC bits of decoded symbol data 68 and 70 (bit data), respectively. Circuits 116 and CRC 118 is fed CRC results 120 and 122, respectively, to microprocessor 56 as the Q1 and Q2, respectively. In other embodiments, the circuit may also be provided to check the CRC bits of decoded symbol data (bit data) 72 and 74. In the embodiment disclosed herein and in copending patent application and U.S. Patent No. 5,103,459 results 120 and 122 are usually presented one-bit CRC value.

The reverse link decoder 30 comprises the apparatus shown in Figure 3. Programmable symbol data consists of 180 symbols of the gated packets (not shown). Modulator 18 pseudorandomly unmasks redundant symbols into groups of data transmitted at less than full speed, by using the processing described in the aforementioned U.S. Patent 5,103,459, and further described in copending U.S. Patent Application, Serial 07/846312. Again in Figure 3, as in Figure 2 - for easier understanding - the device is illustrated as having a plurality of parallel data channels. However, it should be understood that it is preferable to use one channel shared circuit elements. In the embodiment with shared elements demodulated data stored in the buffer unit (not shown) in the form in which they are received, and supplied to processing channels for reparse data group for each of the possible data rates. 3, selector 182 receives symbol data 180 and extracts a half of the symbols to generate the selected symbol data 188, the selector 184 receives selected symbol data 188 and extracts a half of the symbols to generate the selected symbol data 190, the selector 186 receives selected symbol data 190 and extracts a half of the symbols to form a selected symbol data 192. As mentioned above for the reverse link, symbols are repeated for a constant number of symbols in the data group. However, the transmission is actually transmitted only from one set of each different repeated symbols sets. At the receiving end the received symbols are treated as symbol sets for the various possible rates. Viterbi decoder 194 receives symbol data 180, Viterbi decoder 196 receives selected symbol data 188, Viterbi decoder 198 receives selected symbol data 190, Viterbi decoder 200 receives selected symbol data 192. Thus, Viterbi decoders 194-200 correspond to data encoded at rates of to complete one eighth, respectively. Viterbi decoders 194, 196, 198 and 200 form a decoded symbol data or bit data 202, 204, 206 and 208 respectively. As in the forward link, each of Viterbi decoders 194-200 most likely to generate the decoded character data 202-208, respectively, with the least errors when the data are encoded at the speed to which they correspond.

Encoders 210, 212, 214 and 216 re-encodes the decoded symbol data 202-208 respectively. Comparators 218, 220, 222, and 224 compare re-encoded symbol data 258, 260, 262 and 264 respectively with character data 180 and the dedicated character data 188, 190 and 192, respectively. Counters 226, 228, 230 and 232 count the number of characters that are not compatible with each other. Counters 226-232 form a symbol error coefficients 234, 236, 238 and 240, respectively, each represented by an eight value. Symbol error coefficients 234, 236, 238 and 240 represent the number of inconsistencies in the data group and supplied to the microprocessor 242 as the S1, respectively.

<IMG>

<IMG>

<IMG>

Viterbi decoders 198 and 200 also form the Yamamoto quality metrics 244 and 246, respectively, which is fed to microprocessor 242 like Q4 and Q8 respectively. In other embodiments, Yamamoto Quality Metrics 244 and 246 may be formed circuit being external to Viterbi decoders 198 and 200. As discussed above, the Yamamoto Quality Metric value represented by one bit.

Scheme CRC 248 and 250 control the CRC bits of decoded symbol data 202 and 204 respectively. Circuits 248 and CRC 250 is fed CRC results 252 and 254 respectively to the microprocessor 242 as the Q1 and Q2, respectively. In other embodiments, the circuit may also be provided to check the CRC bits of decoded symbol data 206 and 208. CRC results 252 and 254 typically presents one bit value each.

Microprocessors 56 and 242, the processing illustrated making binary tree in Figure 4 to determine the rate at which data is encoded in the transmission on the forward link and reverse link, respectively. Determining the velocity of the reverse link is the same as the definition of the speed in the forward communication channel - with the exception of certain thresholds in Expressions. The threshold values ​​used in the processing procedure is a function of communication, and may vary for any particular conditions. The table shows the range of values ​​for the ten thresholds of Figure 4. The inputs to the processing procedure referred to collectively as "error metrics" and comprise CRC results of Q1 and Q2, Yamamoto Quality Metrics Q4 and Q8, and Symbol Error Ratio S1, which correspond to the inputs of the microprocessor or by 2 or by 3.

<IMG>

<IMG>

<IMG>

The values ​​for T1-T10 in the form in which they are given in the table are based on the number of symbols in one data group. The number of symbols in one group of data symbols 384 is equal to a group for direct channel encoded half-rate, and a group of 576 symbols for the reverse link encoded with a rate one-third of the total, as indicated above. In the reverse link due to encoding at a rate one-third full rate encoder produces three symbols of output for each input data bit. Entries in the table represent "a shortcut" in the error comparison process on the reverse link. Instead of comparing each of the three symbols output from the encoder to the originally received symbols comparator only compares two of the three symbols. This procedure reduces the number of required parallel circuitry, providing the same average results as comparing all three with symbols. Therefore, entries in the table reflect the comparison of 384 symbols in the group (equal to two-thirds of the actual 576 symbols received each group) and a corresponding scaling in the values ​​of S1, S2, S4 and S8. The most general expression for the empirical results of the table is given in the column "% Direct communication channel" and "reverse link%" that represent T1-T10 as a percentage of the number of characters in the group.

In view of the table should be noted that the expressions for the treatment procedures in forward link and reverse link shown in Figure 4 reflect the results of empirical studies primarily voice data for a particular data group, and modulation parameters disclosed herein and in the aforementioned co- filed patent applications and U.S. Patent 5,103,459 Other expressions may provide better results when non-voice data is transmitted, e.g., facsimile data, or if the system is working in different conditions, such as indoors. Accordingly, the error rate when compared to the character you can easily use other values ​​for levels of additional comparisons and constants.

Processing procedure illustrated in FIG. 4, once for each group of data. To normalize the input data for the decision procedure, the values ​​for processing data from the partial rate multiplied by the reciprocal of the data rate. In this case: .

<IMG>

<IMG>