Method and apparatus for determining the data rate of a received signal

Background of the invention

The present invention relates generally to digital communications. More particularly, the present invention relates to a system in which variable rate data is transmitted without data rate indication and received at a communications receiver where the data rate of the transmitted data is determined for use in processing the data.

In digital communication systems, especially those using spread-spectrum modulation, a transmitter may use a vocoder or voice coding system that encodes voice information at a variable rate to reduce the data rate during (speech) pauses or in other cases of lack of voice activity to thereby reduce the interference level caused by this transmitter at receivers other than the particular receiver. At the receiver or other device associated with the receiver, a vocoder or speech encryption system is used to reconstruct or Restore the language information. It should be noted that in addition to the voice information, non-voice information alone or a mixture of the two may be transmitted to the receiver.

A vocoder suitable for use in this case is disclosed in US Pat. 5,414,796 of the 9th May 1995 entitled "VARIABLE RATE VOCODER". This vocoder generates coded data from digital samples of speech information at four different rates, for example, approximately 8,000 bits per second (bps), 4,000 bps, 2,000 bps, and 1,000 bps, based on speech activity during a 20 milliseconds (ms) frame Frame, or Time frame. Each frame or frame of vocoder data is formatted with excess bits as data frames at 9,600 bps, 4,800 bps, 2,400 bps, and 1,200 bps. The frame with the highest data rate corresponding to a 9,600 bps frame is referred to as a "full rate" frame; a 4,800 bps data frame is referred to as a "half-rate" frame. A 2400 bps data frame is referred to as a "quarter rate" frame and a 1200 bps data frame is referred to as an "eighth rate" frame. Neither the encoding process nor the frame formatting process includes information regarding the rate in the data.

Additional details regarding the formatting of vocoder data in frames or frames are described in US-A-5,504,773 entitled "METHOD AND APPARATUS FOR THE FORMATTING OF DATA FOR TRANSMISSION". The data frames may be further processed, spread spectrum modulated and transmitted as described in US Pat. No. 5,103,459 entitled "SYSTEM AND METHOD FOR GENERATING WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM" of April 7, 1992 ,

Since the rate information is not transmitted for each frame, the receiver must determine from the received data frame the rate at which the data was encoded in order for the vocoder to properly reconstruct the speech information. can restore. Although the transmitter could transmit information regarding the rate at which the frame was encoded, this would reduce the system resources available for transmitting voice and non-voice data. Furthermore, corruption or Disruption in the transmitted rate information adversely affects the entire frame. Thus, it is desirable for the receiver to determine the rate at which the frame was encoded without receiving rate information from the transmitter. These problems and deficiencies are clearly felt in the prior art and they are solved by the present invention in the following manner.

The invention

The invention is set forth in its broadest aspects in the method claim 1 and the device claims 37 and 38.

The present invention relates to a system for determining the rate at which data has been encoded by a transmitter of a communications system at a receiver of the variable rate communication system. Although the present invention may be used in many communication systems, it is particularly useful in cellular communication systems using a variable rate vocoder for encoding and decoding speech at a plurality of discrete rates or a variable rate data transfer protocol. Such communication systems include mobile phones, personal communication devices, wireless local devices or Loops and private branches, and especially those using spread spectrum modulation. The present invention may be used in receivers of both the "mobile station" and the cell or "base station" or wherever the receiving vocoder is in a system, such as a cellular or wireless cell. Cellular telephone system is arranged to provide the vocoder of the receiver with rate information, thereby allowing the vocoder of the receiver decoded the coded language or restores.

The present invention receives a frame consisting of a predetermined number of symbols representing speech that has been digitized and encoded by the vocoder of the transmitter for a predetermined period of time. The received frame may consist of multiple copies or repetitions of each symbol if the vocoder of the transmitter has coded the speech at less than a predetermined maximum rate.

Each frame of the received symbols is decoded with each of the possible rates. Error measures or Data describing the quality of the decoded symbols for each frame decoded at each rate is provided to a processor. The error measures or data can be cyclic redundancy check (CRC) results, Yamamoto quality measures or Data and symbol error rates. These error data are known in communication systems. The processor analyzes the error data using a new decision process and determines the most likely rate at which the incoming symbols were encoded. The processor may provide the rate information to the vocoder of the receiver or other devices.

The foregoing and other features and advantages of the present invention will become apparent to those skilled in the art from the following description, claims, and drawings.

Short description of the drawing

For a more complete understanding of the invention, reference is now made to the following detailed description of the embodiments illustrated in the drawing; in the drawing shows:

Fig. 1 is a block diagram showing the present invention in the receiver of a cellular telephone system;

Figure 2 is a block diagram of the rate determining apparatus of the base station receiver of a cell or cellular phone system;

Figure 3 is a block diagram of the rate determining device of the mobile station receiver of a cell or cellular telephone system; and

Figure 4 is a flowchart of a rate determination process.

Description of the Preferred Embodiment

In Fig. 1 is a digital communication system shown. For purposes of illustration, this system is described herein as a CDMA cellular or cellular telephone system. It should be understood, however, that the invention is applicable to other types of communication systems, such as personal communication systems (PCS), wireless local units or loops, private branch exchanges (PBX), and other known systems. Further, other systems using other known transmission modulation schemes, such as TDMA, may employ the present invention. The system according to FIG. 1 has a transmitter 10 and a receiver 12, which may either be a receiver of a base station (also known as cell or cell-site) or a receiver of a mobile station. Communication from the transmitter 10 to the receiver 12, when the receiver 12 is located in a mobile station, is referred to as the & quot; forward link & quot; "Forward link" is known, and the communication from the transmitter 10 to the receiver 12 when the receiver 12 is arranged in the base station as the "back link" or known as "reverse link".

The transmitter 10, in an exemplary embodiment, includes a vocoder 14 that encodes voice data 16 for formatting into data frames at different data rates, for example, frames at rates of 9,600 bps, 4,800 bps, 2,400 bps, or 1,200 bps. The vocoder 14 selects a rate responsive to the degree of speech activity in the speech data 16, as in the above-referenced U.S. Patent No. 5,149,244. 5,414,796 and encodes the speech data accordingly. Vocoder data bits 20 and the predetermined rate are provided to a modulator 18. Modulator 18 is described in the above-referenced US Pat. 5,103,459 and is briefly addressed here as background information. While the present invention will be discussed in conjunction with four different data rates, it should be understood that the teachings of the present invention are also applicable to systems where greater or lesser numbers of data rates may be used. In addition, the data rates discussed here are for example purposes only and other data rates may be used. For example, an alternative set of frame rates may be 14,400 bps, 7,200 bps, 3,600 bps and 1,800 bps.

The following data frame information is provided, for example, for a further understanding of the frame formatting. As previously described, all frames have a duration of 20 ms. A vocoder full rate frame consists of 160 data bits and 11 internal check bits. This full-rate vocoder frame is formatted by the modulator 18 into a 9,600 bps transmission frame made up of 192 bits. These 192 bits are formed from the 171 data bits generated by the vocoder, one mode bit, 12 CRC bits, and 8 tail bits. A vocoder half rate frame consists of 80 bits and can be formatted into a 4,800 bps 96 bit transmission frame. The 4,800 bps transmission frame consists of the 80 vocoder bits together with 8 CRC bits and 8 end bits. A vocoder quarter rate frame consists of 40 bits and can be formatted into a 4800 bit 2400 bps transmission frame. The 2400 bps transmission frame, together with the 40 vocoder bits, comprises 8 end bits. Finally, a vocoder eighth rate frame consists of 16 bits and can be formatted into a 1,200 bps transmission frame with 24 bits. The 1200 bps transmission frame, together with the 16 vocoder bits, comprises 8 end bits. It should be noted that a mixture of voice and non-voice data may be formatted into a 9,600 bps transmission frame if less than the full rate vocoder data is provided. The mode bit and additional excess bits are included in a frame of this type to indicate the rate at which the voice data is encoded. Regardless of the rate of speech data in a frame of this type, this received frame is recognized as a 9,600 bps frame, or which contains less than the full rate vocoder data. The excess bits are used as such to control the output or to overrule an output of a full rate frame display for the vocoder to process the portion of the bits in the frame corresponding to the less than full rate frame vocoder data. In addition, it should be noted that the vocoder data in a full-rate transmission frame can be replaced with non-voice data.

In this case, there are again excess bits in the frame identifying the frame of this type. In an alternative embodiment, the variable rate data may include variable rate non-voice data. The non-voice data could be transmitted at a maximum rate determined at the initiation of the transmission. During transmission, the data could be transmitted at the maximum rate and at several sub- or sub-rates, analogous to the different rates used for voice data. A similar rate determination procedure would be used to determine the rate or subrate of the transmitted non-voice data.

The modulator 18 includes circuitry (not shown) for adding the cyclic redundancy check (CRS) bits to full and half rate frames, as well as tail bits to all rate frames (not shown) to the vocoder data bits 20. The modulator 18 preferably includes an encoder (not shown) convolutionally encoding each frame of data (not shown) to produce frames of symbol data. In the forward link, the convolutional coding preferably has a rate of 1/2, and in the return link, the convolutional coding preferably has a rate of 1/3.

Each frame of symbol data is interleaved or interleaved by an interleaver or interleaver (not shown), preferably on a bit level basis, to increase time diversity for the purpose of error correction. For these frames, which correspond to a data rate less than the highest data rate, for example 9,600 bps, the modulator 18 repeats symbol data to maintain a constant symbol rate for the frame. In other words, if the rate selected by vocoder 14 is less than that corresponding to a 9,600 bps frame rate, modulator 18 repeats the symbols to fill the frame with the number of repetitions, depending on the data rate. For a frame corresponding to a 9,600 bps data rate, all symbols are provided by the modulator 18 in an interleaved data frame. However, for a frame corresponding to a 4,800 bps data rate, the modulator 18 provides the symbols twice in an interleaved data frame. For data frames corresponding to 2,400 bps and 1,200 bps data frames, the modulator 18 similarly provides the symbols four times and eight times in an interleaved data frame, respectively. Thus, in this exemplary embodiment, a frame of symbol data consists of 384 symbols for rate-by-half encoding for a symbol frame rate of 19,200 symbols per second (sps).

The frames of the symbol data are two-phase shift modulated or bi-phase shift key (BPSK) modulated with orthogonal coverage of each BPSK symbol along with a quadrature phase shift propagation or distribution; a quadrature phase shift key (QPSK) spread of the covered symbols as described in US Pat. 5,103,459 is described. In the forward link, the modulator 18 transmits the frame as a continuous stream of modulated symbol data 22, with the power of each transmitted frame reduced according to the symbol repetition in the frame.

In the return link, the modulator 18 uses orthogonal signaling techniques along with QPSK spreading and BPSK modulation as described in US Pat. 5,103,459 is described. The modulator 18 comprises a data burst or Burst randomization unit or a randomizer (not shown) of the frame in bumps or Bursts from symbol data 22 transmits. Further details of the Data Burst Randomizer are disclosed in Taiwanese Patent NI-072304 of 15. November 1995 entitled "DATA BURST RANDOMIZER". Using the data burst randomizer, non-full rate data is transferred in controlled segmented time segments. The ratio of the data burst segments to the total time is proportional to the data rate. Thus, in the exemplary embodiment, a frame consists of full-rate data of 576 (one-third rate) symbols for a symbol frame rate of 28,800 sps; a frame of half-rate data consists of 288 symbols at a symbol frame rate of 28,800 sps transmitted at a 50% duty cycle; a frame of quarter-rate data consists of 144 symbols at a symbol frame rate of 28,800 sps transmitted at a 25% duty cycle; a frame of eighth-rate data consists of 72 symbols at a symbol frame rate of 28,800 sps, which are transmitted at a 12.5% ​​duty cycle.

The receiver 12 has a demodulator 26 for demodulating and deinterleaving or Deinterleaving or Unlinking Received Symbol Data 24. The demodulator 26 provides symbol data 28 to the decoder 30, which includes the rate determination system of the present invention. Demodulation symbol data 28 is "soft decision data" since it is the actual values ​​of the I and Q components of the received symbol data 24, and those of the transmitted symbol data 22 and the interferences, rather than being the binary representation of a most likely transmitted symbol decision ,

The device according to FIG. 2 determines the rate at which the data was coded for forward link transmission. The apparatus shown in Figures 2 and 3, which is subsequently introduced, is shown as having a plurality of parallel data processing paths for the purpose of facilitating the understanding of the invention. It should be noted, however, that only a single path with a division or Community use of circuit elements is preferred to reduce the number of circuit elements. In this arrangement with shared or For shared elements, the demodulated symbol data is stored in a buffer (not shown) as received and delivered to the path for repeated processing of the data for each of the possible data rates. The decoded output or the output signal for each data rate is also stored until the rate determination has been made. The stored decoded output corresponding to the selected data rate is then passed to subsequent stages for further processing. In the present invention, the parameters and data generated by this decoder are used to determine the frame rate of the transmitted data from each of the possible frame rates.

In Fig. 2 Demodulated symbol data 28 is provided to each of the adders 34, 36 and 38. As previously noted, for forward link transmitted frames, lower frame rate symbols are repeated to achieve a constant number of symbols in a transmitted frame. To provide quality enhancement, the repeated symbols are summed and scaled at the receiver to provide for each set of repeated symbols a combined symbol representation of the original symbol before repetition at the transmitting end. Summer 38 sums every eighth symbol and provides scaled sum symbol data 40. Summer 36 sums every fourth symbol and provides scaled sum symbol data 42. Summer 34 sums every other symbol and provides scaled sum symbol data 44. Thus, the adders 34, 36 and 38 correspond to half-rate data to eighth-rate data, respectively.

Each of four Viterbi decoders 48, 50, 52 and 54 decodes symbol data 28 and convolutionally encoded, scaled sum symbol data 44, 42, respectively. 40 to provide appropriate bit data. The Viterbi decoders 42 and 54 comprise means for generating Yamamoto quality data or Metrics 60 or 62 to the microprocessor 56 as Q4 or Q8 will be delivered. Yamamoto quality data or Metrics 60 and 62 are typically represented by a one-bit value for each frame. A Yamamoto quality metric is a well-known indicator of data quality. In other embodiments, the Viterbi decoders 48 and 50 may also generate Yamamoto quality metrics. However, since there are other more precise quality indications for higher rate data, the use of the Yamamoto quality metrics is generally unnecessary. In other embodiments, the Yamamoto quality metrics 60 and 62 may be generated by circuits residing outside the Viterbi decoders 52 and 54.

As noted previously, each of the Viterbi decoders 48-54 generates decoded symbol data or bit data 68, 70, 72, respectively. 74th Encoders 76, 78, 80 and 82 respectively recode the decoded symbol data 68 to 74. Comparators 84, 86, 88 and 90 compare recoded bit data 92, 94, 96 and 98 with demodulated symbol data 28, scaled sum symbol data 44, 42, respectively. 40th Counters 100, 102, 104 and 106 count the number of symbols that do not match. Counters 100 to 106 generate symbol error rates 108, 110, 112 and 114 each represented by an eight-bit value. Symbol error rates 108 to 114 represent the number of mismatches in a frame and are sent to the microprocessor 56 as S1, S2 / 2, S4 / 4, and so on. S8 / 8 delivered.

Cyclic redundancy check (CRC) circuits 116 and 118 check the CRC bits of the decoded symbol data (bit data) 68, respectively. 70th The CRC circuits 116 and 118 see CRC results 120 and 120, respectively. 122 before, as Q1 or Q2 for the microprocessor 56. In other embodiments, circuitry may be provided for checking the CRC bits of the decoded symbol data (bit data) 72 and 74 if so provided. In the exemplary embodiment disclosed herein and in co-pending patent applications and US Pat. 5,103,459, CRC results 120 and 122 are typically represented by a one-bit value.

In the return connection, the decoder 30 has the device shown in FIG. Soft decision symbol data 180 have timed symbol bursts or shocks (not shown). The modulator 18 pseudorandomly covers the redundant symbols in frames transmitted at less than full rate. masks these out, using a method disclosed in the above-referenced US Pat. 5,103-, 459 and further described in the above-referenced Taiwanese Patent NI-072304. Again, in FIG. 3 as well as in Fig. 2 the apparatus is shown as having a plurality of parallel data processing paths for ease of understanding. It should be noted, however, that a single path is the shared or shared circuit elements used is preferred. In the arrangement with split or For shared elements, the demodulated data is stored in a buffer (not shown) as received and provided to the path for repeated processing of the frames for each of the possible data rates. In Fig. 3, a selector 182 receives symbol data 180 and extracts one half of the symbols to produce selected symbol data 188; a selector 184 receives selected symbol data 188 and extracts one half of the symbols for generating selected symbol data 190; and a selector 186 receives selected symbol data 190 and extracts one half of the symbols to produce selected symbol data 192. As mentioned in connection with the return link, symbols are repeated to achieve a constant number of symbols in the frame. In a transmission, however, only one set of each of the differently repeated symbol sets is actually transmitted. At the receiver end, the received symbols are treated as symbol sets for the different possible rates. A Viterbi decoder 194 receives symbol data 180; a Viterbi decoder 196 receives selected symbol data 188; a Viterbi decoder 198 receives selected symbol data 190; and a Viterbi decoder 200 receives selected symbol data 192. Thus, Viterbi decoders 194 to 200 correspond to data encoded at a full rate to eighth rate, respectively. The Viterbi decoders 194, 196, 198 and 200 generate decoded symbol data or bit data 202, 204, 206 and 208th As with the forward link, each Viterbi lyecoder is most likely to generate 194 to 200 decoded symbol data 202 to 208 with the fewest errors when the data is encoded at the rate corresponding to the decoder.

Encoders 210, 212, 214, and 216 respectively recode decoded symbol data 202 through 208. Comparators 218, 220, 222 and 224 compare recoded symbol data 258, 260, 262 and 264 with symbol data 180 and selected symbol data 188, 190 or 192nd Counters 226, 228, 230 and 232 count the number of symbols that do not match. Counters 226-232 generate symbol error rates 234, 236, 238 and 238, respectively. 240 each represented by an eight-bit value. Symbol error rates 234, 236, 238, and 240 represent the number of mismatches in a frame and are provided to the microprocessor 242 as S1, S2 / 2, S4 / 4, respectively. S8 / 8,

Viterbi decoders 198 and 200 also produce Yamamoto quality metrics 244 and 246, respectively, which are provided to the microprocessor 242 as Q4 and Q8, respectively. In other embodiments, the Yamamoto quality metrics 244 and 246 may be generated by circuitry outside the Viterbi decoders 198 and 200. As previously discussed, the Yamamoto quality metrics or data are represented by a single bit value.

Cyclic Redundancy Check (CRC) circuits 248 and 250 check the CRC bits of decoded symbol data 202 and 204, respectively. CRC circuits 248 and 250 provide CRC results 252 and 254, respectively, to the microprocessor 242 as Q1 and Q2, respectively. In other embodiments, circuitry may also be provided for checking the CRC bits of the decoded symbol data 206 and 208. CRC results 252 and 254 are each typically represented by a one-bit value.

Microprocessors 56 and 242 use a method that is characterized by the method shown in FIG. 4 shown binary decision tree for determining the rate with the data in a forward link or Reverse transmission transmission were coded. The reverse link rate determination method is the same as the forward link rate determination method except some of the thresholds in the equations. The thresholds in the method are a function of the connection and they can be used for different environmental conditions or Environments are modified. Table 1 gives a set of values ​​for the 10 thresholds in FIG. 4th The inputs or Input signals to the method are collectively known as "error metrics" or "error data", and they have CRC results Q1 and Q2, Yamamoto quality metrics Q4 and Q8, and symbol error rates S1, S2 / 2, S4 / 4, and so on Microprocessor inputs or Input signals from either FIG. 2 or FIG. 3 correspond.

The values ​​of T & sub1; T & sub1; & sub0; as expressed in Table I are based on the number of symbols / frames. The number of symbols per frame is 384 symbols / frames for the forward link communication encoded at a rate of one-half and 576 symbols / frames for a reverse link communication encoded at a rate of one-third as previously noted. At the return link, the encoder generates three output symbols for each input data bit due to the one-third encoding rate. The entries in Table I reflect an "abbreviation" in the error comparison process on the return link. Instead of comparing each of the three symbols output from the encoder to the original received symbols, the comparator compares only two of the three symbols. This method reduces the required parallel circuits while maintaining the same average results as comparing all three symbols. Therefore, the entries given in Table I reflect the comparison of 384 symbols / frames (equal to two-thirds of the actual 576 symbols received with each frame) and a corresponding scaling in the S1, S2, S4, and S8 values. The most general expression for the empirical results of Table I are given in the columns designated as forward link% and return link%, which are T & sub1; T & sub1; & sub0; as a percentage of the number of symbols in a frame. Table I

With regard to Table I, it should be noted that the terms used in both the forward link operation and the return link procedure are as shown in FIG. 4 the results of empirical studies are reflected, primarily in voice data for the here and in the aforementioned co-pending patent applications and US Pat. 5,103,459 specified frame and modulation sizes or -numbers. Other terms may yield better results when transmitting non-voice data, such as facsimile data, or when the system is operating in a different environment, such as in a local area environment. Accordingly, other values ​​at the symbol error rates can be easily compared for comparison levels and added constant values.

With reference to FIG. 4 described method is performed once for each frame. To normalize the input of the decision process, the S values ​​for the non-full rate data methods are multiplied by the inverse of the data rates. In this case S2 = 2χS2 / 2, S4 = 4χS4 / 4, S8 = 8χS8 / 8. At the beginning of the process for the frame, the microprocessor goes to node or point 126 if the expression at point or node 124 is true; if it is wrong, then the microprocessor goes to point 128. At point 124, the expression "Q1 = 1 & Q2 = 1" denotes that the CRC result Q1 is equal to one and that the CRC result Q2 is equal to one. In this embodiment, the CRC values ​​of one (1) and Zero (0) that the CRC for the received frame of data is correct or was incorrect. Across the (decision) tree, the symbol "&" denotes a Boolean AND operator, the symbol "" denotes a Boolean OR operator, and the symbols "=" and "≤" designate both relational operators.

At point 126, the expression "S1≤S2 + T₁" denotes the symbol error rate S1 is equal to or less than the symbol error rate S2 plus a threshold value T & sub1; is equal to 15 for both forward and reverse links according to Table I. If the expression at point 126 is true, then the microprocessor determines that the rate is a full rate, at output 127, and provides a corresponding frame rate indication; if it is false, then the microprocessor determines that the rate is a half rate at output 129 and provides a corresponding frame rate indication.

At point 128, the expression "Q1 = 1 & S1≤T 2" that the CRC result Q1 is one, and that the symbol error rate S1 is less than or equal to a symbol error rate of T & sub2; which is 77 for the forward link and 110 for the reverse link. If the expression at point 128 is true, then the microprocessor determines that the rate is a full rate at output 131 and provides a corresponding frame rate; if it is wrong, then the microprocessor goes to point 130.

At point 130, the expression "Q2 = 1 & S2≤T 3" denotes that the CRC result Q2 is equal to one and that the symbol error rate S2 is less than or equal to the symbol error rate T & sub3; is. If the term at point 130 is true, then the microprocessor goes to point 132; if it is wrong then the microprocessor goes to point 134.

At point 132, the expression "Q8 = 1 & (Q4 = 0 S8 ≤ S4)" indicates that the Yamamoto quality metric Q8 equals one, and the term further indicates that the Yamamoto quality metric Q4 equals zero or the symbol error rate S8 is less than or equal to the symbol error rate S4 is true. For this embodiment, the Yamamoto quality metric values ​​of one (1) and Zero (0) indicates a high or low probability of correct decoding of the symbol data by the Viterbi decoder.

If the expression at point 132 is true, then the microprocessor goes to point 136; if it is wrong then the microprocessor goes to point 138. At point 136, the expression "S2≤S8 + T₄" denotes the symbol error rate S2 is less than or equal to the symbol error rate S8 + T & sub4; is. If the term at point 136 is true, then the microprocessor determines that the rate is a half rate at output 131a and provides a corresponding frame rate indication; if it is false, then the microprocessor determines that the rate is an eighth rate at output 133 and provides a corresponding frame rate indication.

At point 138, the expression "Q4 = 1" indicates that the Yamamoto quality metric Q4 is equal to one. If the expression at point 138 is true, then the microprocessor goes to point 140; if it is false then the microprocessor determines that the rate is a half rate at output 135 and provides a corresponding frame rate indication. At point 140, the expression "S2≤S4 + T5" denotes the symbol error rate S2 is less than or equal to the symbol error rate S4 plus T & sub5; is. If the term at point 140 is true, then the microprocessor determines that the rate is a half rate at output 137 and provides a corresponding frame rate indication; if it is false, then the microprocessor determines that the rate is a quarter rate at output 139 and provides a corresponding frame rate indication.

At point 134, the expression "Q4 = 1 & Q8 = 1" indicates that the Yamamoto quality metric Q4 equals one, and that the Yamamoto quality metric Q8 equals one. If the expression at point 134 is true, then the microprocessor goes to point 142; if it is wrong then the microprocessor goes to point 144. At the point 142, the expression "S8 <S4 & S8 <T6" denotes that the symbol error rate S8 is smaller than the symbol error rate S4 and that the symbol error rate S8 is less than or equal to a Smybol error rate of T & sub6; is. If the term at point 142 is true, then the microprocessor determines that the rate is an eighth rate at output 141 and provides a corresponding frame rate indication; if it is wrong, then the microprocessor goes to point 146. At point 146, the expression "S4 <S8 & S4 <T7" denotes that the symbol error rate S4 is smaller than the symbol error rate S8 and that the symbol error rate S4 is less than or equal to a symbol error rate of T & sub7; is. If the term at point 146 is true, then the microprocessor determines that the rate is a quarter rate at output 143 and provides a corresponding frame rate indication; if it is false, then the microprocessor can not determine the rate and provides a "clear" indication on output 145. Since the receiver vocoder (not shown) can not decode a frame unless the microprocessor provides it with the rate, the receiver vocoder ignores the current frame and interpolates the speech data between the previous frame and the next frame in response to the frame delete screen.

At the point 144, the expression "Q4 = 1 & S4≤T 8" that the Yamamoto quality metric Q4 is equal to one and that the Smybol error rate S4 is less than or equal to the symbol error rate T & sub8; is. If the term at point 144 is true, then the microprocessor determines that the rate is a quarter rate at output 147 and provides a corresponding frame rate indication; if it is wrong then the microprocessor goes to point 148. At the point 148, the expression "Q8 = 1 & S8≤T9" denotes that the Yamamoto quality metric Q8 is equal to one and that the Smybola error rate S8 is less than or equal to the symbol error rate T & sub9; If the expression at point 148 is true, then the microprocessor determines that the rate is an eighth rate at exit 149 and provides a corresponding frame data indication; if it is wrong then the microprocessor goes to point 150. At the point 150, the expression "S1≤T10" denotes the symbol error rate S1 is less than or equal to the symbol error rate T & sub1; & sub0; is. If the term is true at point 150, then the microprocessor determines that the rate is likely to be a full rate but that the frame is likely to contain bit errors. Therefore, the microprocessor provides a "full rate probable" frame data display at output 151. If the printout at point 150 is false, then the microprocessor provides a clear indication at point 153.

As noted above, in the case of less than full-rate frame vocoder data may be transmitted along with non-voice data in a 9,600 bps transmission frame. Although the microprocessor will determine that the frame is a full rate frame, it will check the mode bit to determine if the frame is actually formed of full rate vocoder data. If the mode bit indicates that the frame is constructed of full rate vocoder data, then that indication is provided to the vocoder. However, should the mode bit indicate that the frame is made up of a mixture of vocoder data and non-voice data or only non-voice data as a whole, then further examination of the extra overhead bits transmitted in a frame of this type is performed. From these additional overhead bits, the rate of the vocoder data, if any, is displayed. In cases where the vocoder data is present in a frame of this type, the microprocessor provides to the receiver vocoder the indicated frame rate of the vocoder data instead of those determined from the received transmission frame. In the case where the received transmission frame as a whole is formed of non-voice data and this is indicated by the excess bits, the microprocessor provides an idle or free indication to the receiver vocoder.