Pulse code modulation translators.

The invention relates to a converter. code for modulation by PCM coded pulses for the conversion of an input PCM word, into an output PCM word, one of the words mentioned being, in accordance with a compressed code, and the other with a linear code.

Code converters are known for modulation of pulse impulses in code which makes changing a linear PCM code word into a compressed PCM code word.

These well-known solutions present the disadvantages of complex structures.

The object of the invention is to provide a code converter that can perform the selective conversion, according to law A or the law, while having a relatively simple structure. - The problem solved by the invention consists in the design of a converter that converts the binary bits of the input word into those of the output word, in accordance with either law A or law u, as selected by the binary value. of a command bit that determines the digital values ​​of a few parameters of the converter.

The code converter according to the invention removes the disadvantages of known solutions by converting a compressed PCM input word containing a three-bit segment code and a four-bit step code into a linear PCM output word by determining function:

J - (L + a. 2⁴ + b. 2 ~ '). 2^K'+ c where J is the output word mentioned; L is the step code mentioned, · a, b and c are variable; K 'is related to said segment code and depends, together with the mentioned variables a, b and c, on said command bit indicating that the input word is encoded according to law A or the law, it includes some decoding means for decoding the code segment of three bits in a code ί of 8, some logical means coupled to the decoding means controlled by the said control bit and providing the variables:

a ~ S'0 '+' A b = S'0 (S'l + A)

- S'0. A

- S'0. A + S'l the word code S7, ... Sî, S0 constituting an altered segment code having the value ze2 cimal K ', · some means for modifying the mentioned step code L by the variables α and b thus trying to obtain an altered step code L + a. 2 '* + b. 2^_1 ; some means of multiplication, coupled with the means of modification mentioned, for multiplying the altered step code by 2K 'so as to obtain the product (L + a. 2^and + b.2 ~ '). 2^K'and additive means coupled to said multiplication means and commanded by said control bit to add the variable c mentioned to the said product thus making it possible to obtain the output word J.

Another feature of the present translator is that it is adapted to translate a linear PCM input word into a compressed PCM output word, comprising a 4-bit segment code, by determining the functions:

K z = log-, l (J + c). 2L = (J + c). 2-^{/ f}· - cl where K is the segment code; L is the step code (c and d are variable, · K 'is in relation to the segment code and depends, together with c and d on the command bit mentioned, which indicates that the output word is encoded, according to law A or law μ .

From these functions it follows, again, that the operations to be performed for law A and law μ are very similar and differ only in the details because it is possible to use the same translator structure for both laws.

Another feature of this PCM converter is that it comprises:

- additive means commanded by the control bit, to add the variable c to the input word J, to obtain an altered input word J + c and to store it in a switch register;

- the decoding means coupled with the switch register, for decoding the most significant eight bits of the altered input word J + c, in a code 1 of 8; St, Sî ... SS, S'0, but taking into account only the bit activated by the highest power of the altered input word, - coding means coupled to the decoding means mentioned, for coding the mentioned code 1 of 8, in a segment of three bits, K;

- logical means which are coupled to the decoding means mentioned and controlled by the control bit and which provide the variables:

S0 - S'0.A

If - S'0. Â + i If the code word has the decimal value K ';

- multiplication means and additives for multiplying the altered entry word. J + c by 2 '^Λ"And by adding the mentioned variable - d to this product so that the step code L is obtained.

The invention also relates to a switching register cell with a data input coupled to a data output via a cascade link of an input storage circuit and an output storage circuit. This switch register cell is characterized in that it also has an auxiliary data input, said auxiliary data input and the output of said first storage circuit being coupled to the input of the second storage circuit through, respectively the first and second circuits have a common command input and so they are always in a state of opposite conductivity.

The invention also relates to a multiplier device for multiplying a binary word, stored in a first switch register, with 2^x, where χ = 0 ... K, by switching the word mentioned by x floors of the mentioned switch register.

This multiplier device is characterized in that the second switch register comprises K floors, that the output of said first switch register is coupled to the K floors of the second switch register by means of, respectively, K gate circuits that are controlled by the respective bits of a binary code 1 in K, which has the decimal value x, and that a second gate circuit is associated with each of the mentioned floors, the secondary gate circuits being commanded by the respective bits mentioned, so that when a first circuit gate establishes a connection between the output of the first switch register and one floor of the second switch register, the latter floor is isolated from the other floors of of this switch register through a secondary gate, associated with it.

The following is an example of embodiment of the invention in connection with FIG. 1 ... 5, which represents:

FIG. 1, the block diagram of a telecommunication line circuit comprising a PCM code converter, according to the invention;

FIG. 2 and 3, respectively show the detailed diagrams of the COLI and LICO parts of the code converter;

FIG. 4, a register cell;

FIG. 5, the time pulse diagram for the code converter command.

As shown in FIG. 1, the TC code converter forms part of an LC telephone line circuit connected between a LI telephone line and a SNW digital switching network and comprising the cascaded connection of an SLIC subscriber line interface capable of command and line monitoring, a DSP digital signal processor mainly adapted to perform analog-to-digital and analogue-to-digital conversion operations, the transducer circuit and a control terminal with dual DPTC processor which performs the general command of the line circuit.

The DSP processor only processes linear PCM signals, while the DPTC terminal operates mainly with compressed PCM signals. The purpose of the TC code converter and, in particular, of a COLI circuit is to translate the compressed PCM signals received from the DPTC terminal into ILC signals that are then transmitted to the DSP processor and vice versa, into a LICO circuit of the converter , ^ for signals received from the DSP and transmitted to the DPTC. The TC code converter is provided for eight DSP and SLIC circuits, but can be used for up to thirty-two DPS and SLIC circuits. Indeed, the data received in the TC and transmitted further, form a model of thirty-two channels out of which only eight are actually used and in which each channel has a repetition period of one hundred and twenty-five microseconds. The data bit exchange between TC and DSP has a rate of 4,096 Kbh / sec and each channel used contains a sixteen bit PCM signal, of which thirteen bits bl to bl3 together constitute a linear PCM signal. Bit bl is the signal bit S, and bits b2 to bl3 define the absolute magnitude J of the signal. The bl bit is preceded by two identical bits, and the bl3 bit is followed by a bit that can be used as a rounding bit. This 16-bit model is received in a form in which all bits are inverted. The data exchange between TC and DPTC has a rate of 2,048 Kbit / sec and each channel used contains an 8-bit compressed PCM signal consisting of bl to b8 bits. This PCM signal is encoded, according to the logarithmic law segmented A or μ, either 5 comprising 8 segments for each of the values ​​of the S signal, indicated by the bit bl. The three bits from b2 to b4 define a segment K of eight possible segments Ki to IL, and bits b5 to b8 define a step L of the sixteen equal possible steps in the segment. According to the law μ, the relative values ​​of the step dimensions in the segments K0 to Ev are equal, respectively, by 2 ° to 2⁷, while, according to the law A, they are respectively 2 °, 2¹, 2²...2⁷. This means that the step size in segment K0, according to law A, is twice as large as the step size in segment K0, according to law. The compressed PCM signal, bl to b8 is, for example, received from and transmitted to DPTC su'b in a form in which all bits, except the bit sign, are inverted (law μ) or in which only odd numbered bits are inverted ( law A).

Reference is further made to FIG. 2, which shows the COLI circuit of the TC circuit converter which is intended to translate an eight-bit compressed PCM signal or word into a thirteen-bit linear PCM signal or word. The COLI circuit comprises an input circuit ΙΝΡΪ, a SIPO series-input-parallel-output register, a parallel input-series-output-PlSO register, an SR switching register, an SDECi segment decoder circuit, an additive ADDi circuit, a OCi output circuit, LOGi logic circuit, bistable latch circuits. LCi, up to LC / „a circuit carries DC and a timer circuit TCC that generates time pulses of which only TP_t up to TP7 necessary for the operation of the COLI circuit, are represented in fig. 5. Latch LO, LC, LC circuits₂, LCs and LCz, are ordered by TP, respectively₂, TP₄, TP₃ and TPs, and the GC bearing circuit is controlled by TP «,

The INI input of the COLI circuit coupled, via the INPi input circuit, to the SIPOi input, whose outputs are coupled to the LCi inputs having the outputs Ri to R4. The output R1 is connected to the output circuit OCi through the latchable LC latch circuits₃ and LCz ,; R outputs₂ at R4 they are connected to the respective inputs of the SDEO, and R1 and R4 are also connected, via LC₂, at the data inputs 3 of the PC cells₂ up to PISO registry PCs. The latter comprises the cells interconnected PO to the PC₆ with common command inputs 4, commanded by time pulses TP7, as well as common command inputs 5, commanded by time impulses TPj. The output 2 of each of these cells is connected to the input 1 of the next one, except the input 1 of the PO cell that is grounded and the output 2 of the PCs cell which is connected to the common data inputs 3 of the PC11 cells at PCi8 of SR switch register. The latter cells also have the inputs, interconnected, of command 4, controlled by the TPi time pulses, as well as the individual command inputs 5. The SDEO segment decoder circuit has the outputs S '0 S'I and S₂ up to S7 of which S₂up to S7 are coupled, via latchable LC latch circuits₃ and LO and the circuit carries GC, cascaded, at the command inputs 5, the last mentioned ones, of the PCn cells up to the POe of the switching register SR. The outputs S'0 and S'EO a SDEO are coupled, via the latch LOs bistable circuit, to the LOG logic circuit inputs._t having another command input A, and the outputs a, b and Sj, S0. Command entry A indicates law A or law ·_:>, A being respectively 0 and 1. The outputs a and b are connected, through LO, to the data inputs 3, of the cells, respectively, PO and PO of the PISOi, while the outputs S0 and Si are coupled through LO and Cascades, bound in cascade, at control inputs 5, of cells, respectively, PCn and PCi₂ of the SR switching register. The output 2 of the cell PCn is coupled to the output circuit OO via an additive circuit ADDi which is also controlled by the command input A above.

Each of the PISO PCi and PO cells is of the type shown in fig. 4, considered only with the switch Si and contains two identical input and output circuits. The input circuit includes the PMOS transistors, note the PM_tand PM₂. and NMOS transistors, note NMi and NM->, whose source-to-drain and drain-to-source paths are connected in series between V +^: and table. Interconnected gates of PMi and NMs and interconnected drains of PM₂ and NM_t they constitute, respectively, the I input and the O output of the cell input circuit, the gates of NMi and PMi being, ordered directly from the control input 4 of the cell and, respectively, through the inverter INVi. The constituent components of the output circuit are indicated by the same numbers as in the case of the input circuit, however, having a prime sign ('). The gates of NM'i and PMh are now ordered, respectively, directly from the command entry 4 of the cell and through the inverter INVi. I input and output /

O 'are connected in the serial input - of data 1 and, respectively, to the serial output - of data 2 that of the cell, and a parallel input - of data 3 is connected to the output O and the input' common 'of the circuits. input and output of the cell via a switch Si. The latter comprises the PMOS transistor, denoted PMa and the NMOS transistor, denoted NMa whose source and drain electrodes are connected, respectively, to the source and drain electrodes of, respectively, NM3 and PMa, the gates of NMa and PM3 are ordered directly from the input. order 5 and respectively, through an inverter INV₂. It is clear that switch Q.Tul Si is closed when input 5 is activated (1).

Each of the cells in the PCn up to PNis of the SR register are, like the previous ones, of the type presented in fig. 4, however considered with both Si and S2 switches. Switch S₂ it has the same structure as the switch Si, but PM «and NM /, in this case, are controlled directly from the command input 5 and respectively, via the inverter INV2, so that switch 2 is closed when the command input 5 is disabled (0).

The PCi / «PISO cell circuit operates as follows.

In order to allow the input and transfer of data received at the serial input 1, the control input 4 is alternatively activated and deactivated, and the control input 5 is kept deactivated, while to allow the input and transfer of data received at the other input. data 3, command inputs 5 and 4 must be simultaneously activated and deactivated respectively. In the first case the data received from the serial input - · deduced 1 are reversed in the cell input circuit and locked in the cell under the command of the input 4 which is activated and then reversed in the cell output circuit and transferred to the output 2 of the cell below input command 4 which is disabled. In the second case, the data received at the input - parallel - of data are reversed and transferred to the output 2 of the cell under the command of the inputs 5 and which is respectively activated and deactivated.

really :

- when the control input 4 of the cell circuit is activated, NM₍ and PM2 of the input circuit of the cell lead, while PM'2 and NM'i of the output circuit of the cell are blocked, in this way, the drain electrodes of PMi and NM2 are common to the output 0 so that the input circuit of the action cell8 emerges as an inverter for the data received at inputs I or 1;

- when the command input 4 is deactivated, the roles presented above of the input and output circuits are reversed;

- When the command inputs 5 and 4 are simultaneously activated and deactivated, respectively, the data received at the input 3 are received in the output circuit of the cell through the switch Si and are reversed in it, then reaching the output 2 of the cell.

The cell circuit PCu / ie of the SS register works in a similar way, as described for the PCi / ό cell circuit, but in this case the input circuit is disconnected from the cell output circuit via switch S2 when the switch S2 is switched on. time Si is closed and vice versa these two switches being commanded by opposite control signals.

Next, an algorithm suitable for translating an eight-bit compressed PGM word is presented, comprising bits bl to b8 with the sign bit S = bl, segment code K = b2, b3, b4 and step code L - b5, b6, b7, b8, in A linear PCM word J:

J = 2 '<' (L + a.2 '¹ + b .2-¹) + c healthy 7 = J'_j_c where: c is O for law A and c —- 16 for law μ; K 'is equal to 0 to 7 for segments K0 to K7, with the exception of segment K0, in the case of law A, for which this value is 1 in ioc · of 0; a = b = 1 for segments K2 to K7, for both laws and for K1 for the law μ, such that:

J '- 2' (L + 2⁴ + 2 ~ ') a = 1 and b - o for the segment K0 the law μ) and Si (the law A); a = 1 and b = 0 such that:

J '= 2'^f(L + 2⁴) a = b = o and K '= 1 for segment K0 (law Â) such that:

7 '= 2. IT

The COLI circuit described above calculates this algorithm in the manner described below.

A compressed PCM signal at the INi input of the GOLIi circuit, having the first most significant bit (MSB) can be transformed into the INPi input circuit, and the resulting compressed PCM signal of eight bits, comprising bits bi and b.₃ (fig. 1) and defining S, K and L men91607 mentioned above, it is introduced by the serial input into SIPOi with two successive four-bit parts bi at b-, and b₅ at b% starting with the four bits bi at b. they are blocked in the bistable latch circuit LCi under the command of a first time pulse TPz (fig. 5). The sign bit S = bi is thus transmitted the two-bit segment K - bb_sb₄ is applied to the segment decoder SBd £ C |, where it is decoded into a segment code 1 of 8, consisting of bits S₇, S_â, S_s, S₄, S₃, S₂, 8% S0, which appear at the same rated outputs of SDEC. This code defines the segments K0 to

<td>circuit</td><td colspan="2">OU output while co-</td><td></td><td> 10</td>

<td></td><td></td><td>S? S₆ S₅</td><td>S₄</td><td>S₃</td>

<td></td><td>K0</td><td> 0 0 0</td><td> 0</td><td> 0</td>

<td></td><td>Kt</td><td> 0 0 0</td><td> 0</td><td> 0</td>

<td></td><td>K7</td><td> 1 0 0</td><td> 0</td><td> 0</td>

<td>So,</td><td>each of</td><td>outputs S'0; And,</td><td></td><td></td>

<td>Yeah, ... S7 away</td><td colspan="2">SDECi is enabled for</td><td></td><td></td>

<td>one of</td><td>segments</td><td>corresponding to</td><td></td><td></td>

<td>K0, Kt, Ks</td><td>: ... K7 and I am</td><td>allocated values</td><td></td><td></td>

<td>decimal K</td><td> = 0, 1, 2,</td><td>... 7, for these</td><td></td><td> 15</td>

K7, according to the following table

S2 S'i0 Decimal value K '

0 ,1 0

10 1

0 0 7 straight line of K for segment K0 in case of law A. At its outputs, a, h, s0, and the LOGi circuit provide the signals:

segments. However, according to the above algorithm this is not correct for segment K0 in the case of law A, since the value of K 'must then be equal to 1 instead of 0.

Under the command of a first time pulse T? 3, the bit bl and the output code S'0, S'i, S2, ..., S7 of the SDECs are blocked in LC3 so that bit bi and S2 to S7 are applied to the bistable circuit. latch LC-, while bits Q0 and Si are transmitted to the logic circuit LOGi, which are used to calculate the values ​​above ^of - s 0 4 ^

0/1)

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<td></td><td></td><td></td><td>Sz</td><td>If Ss</td><td>And</td><td>ss</td>

<td></td><td>K0 (μ)</td><td></td><td> 0</td><td> 0 0</td><td> 0</td><td> 0</td>

<td></td><td>K0 (A) and</td><td>Ki</td><td> 0</td><td> 0 0</td><td> 0</td><td> 0</td>

<td></td><td>K₇</td><td></td><td> 1</td><td> 0 0</td><td> 0</td><td> 0</td>

S'0, A

S.-S'qTJ-S) and from these relations it follows, according to the above algorithm, that a = b = 1 for the segments Ka up to K7 in both laws A, and p characterized by A and respectively A = 1 ; a = 1 and b - 0 for segment K0 (law, -) and K1 (law A); a - b = 0 for the segment Kț / t (law A); so the segment codes given above are now changed and give the following altered segment codes:

Ss If S0 0 0, 1 0 1 0 0 0 0 • S'0

Thus, the decimal value K '= 1 is now allocated to K0, as required by law A.

During the operations described above, the second bit part b5, b6, b7, b8, defining step code L, was introduced into SIPOi. These bits are locked in LCi under the command of a second time pulse TP2, shown, and then blocked in LC2 by the time pulse TPi. consequently, these bits b5, to b8, are applied to the data inputs 3 of the respective cells, PC2 to PC₅ go PISO.

Bits bi, S0, Si, S2 to S? as a, b from the outputs of LC3 and LOGi, are, due to a time impulse TPs, locked in the latchable circuit LC &lt;, resulting in the respective bit bi being given to OCi, the bits S being applied to the circuit carries GC and bits a and b are fed to the data inputs 3 of the PCi and PC cells. go PISO. The altered step code, consisting of bits a, bs, bs, b7, bs, b, is now introduced in PISO under the control of a second time pulse TP3 and reversed ⁴⁰ In it, it also transfers the outputs of the PC1 cells to the PCs, because the time pulse is then deactivated. Therefore, at the exits of these cells are presented a, bs, b &lt;s, b?, Ba and b.

in this way, the altered step code;

L + a. 00 b.2-i

91jS07 with inverted bits, is stored in PCi cells at ... PC «,. to which are assigned respectively the values ​​2⁴ up to 2 ~ '. As the algorithm shows, this value should now be multiplied by. to obtain the value above J '. This is described in the following.

Also, thanks to the impulse^z of negative direction time TP «and bits S0, Si and S2 to S7 are applied to the command inputs 5 of the respective cells PCu to PCis of the SR register and due to the abduction that only one of these bits is in state 1, the switches Si and S2 are , respectively, closed and open only in the cell to which this bit is applied, and the other cells are respectively open and closed. In this way, a connection is established between the output 2 of the PISO and the output 2 of the cell PCu of the register SR by means of a number of cells equal to the value of K '. For example, for segments S'0 and S7, the switches Si and S2 are closed and opened in the cells PCu and PC18, associated with these segments ^. The bits above b, b8, b7, bC, b5 and a are communicated through the series connected cells of the PISO and of the SR register under the control of six time pulses TP₇, applied to the PISO control input 4, in the first used cells of that SR under the control of six time pulses TP ?, applied to the PISO control input 4, in the first used cells of the SR taking place an inversion. In this way, the value stored in PISO is inverted and multiplied by a factor equal to 2^K'thus enhances the binary value above J' is obtained at its output

SR.

According to the algorithm above. at this value J 'must be added the value c = 0 for the law A. or the value c = —16 for the law: μ, to obtain the desired value J. This is done in the additive circuit ADSi which is controlled by the same command input A as LOGu The result J and the bit sign S are then combined in the output circuit OC, and can be transformed before reaching the OUT1 output terminal.

We refer below to the fiq. 3 which presents the LICO circuit, of the TC translator, which is adapted to translate a linear, three-bit PCM word into an 8-bit compressed PCM word.

The LICO circuit comprises an INP2 input circuit a register of. thirteen cell switching and a SRLC latch bistable circuit, two serial-parallel-output registers SÎPO2 and SIPO3 a SDEC2 segment decoder circuit and an ENC encoder circuit, an additive circuit DD2, a logic LOG circuit₂, latchable circuits latch LCs to LC7, output circuit OC2 and switches SW0 to SW7. SIPO cells₂ and SIPOa are of the type shown in fig. 4, however, being considered without Si and S₂. Their command inputs 4 are common and controlled by the TP time pulses. SW0 to SW switches? are similar to those used in the COLI circuit and as shown in fig. 4.

Entering IN₂ of the LICO circuit is connected, through the INP2 input circuit, to that of the SRLC, which contains thirteen cells and which has an output coupled to the SIPO2 input 1. An output of the first cell of the SRLC is connected to the output circuit OC2, and the additive circuit ADD₂is controlled by command input A which is the same as in the COLI circuit and. it is thus in state 0 for law A and in state 1 for law μ. SIPO2 comprises twelve interconnected cells, SC1 to SC12, having outputs that are connected to the inputs of the SDEC2 segment decoder, which has the outputs S'0, S'1, S₂... coupled to the ENC encoder via the latch LCs bistable circuit. SD02's S'0 and S't outputs are also coupled to the LOG logic circuit inputs₂, which also has the command input A and having the outputs S0 and Si which are connected to the LC₅. .These outputs, S0 to S ?, aie T, C₅ and also their inverse S0 to S₇ are connected, respectively, to the control inputs of switches SW0 to SW7. The data inputs of these switches are connected to the outputs of the respective SC cells₅ the SC12 goes PISO₂, and their data outputs are common and connected to the SIPO input. The outputs of SIPOa and those of the ENC encoder circuit are linked, through the respective latch bistable circuits, LCs and LC?, At the output of the OC2 circuit, whose output constitutes the output of the LICO circuit.

The following is an algorithm for translating a thirteen-bit linear PCM word, consisting of bits bl to b! 3, with the sign bit S - bl and magnitude J defined by bits b2 to bl3, into a PCM word compressed having the sign bit S, the segment K and the step L, given by:

K = LOG_? (J + c). 2"⁴and L - (J + c). 2'^K'- d' where c ~ 0 for law A; c = 16 for the law μ; and with K 'equal to 0 to 7 and d = 16 for segments K0 to K7, except for segment K0 in law A for which this value

9Ϊ6Θ7 is 1 instead of 0 and for which and d = 0. It should be noted that for K a lower limit was calculated.

The LICO circuit described above calculates this algorithm in the manner described below.

A linear input PCM word applied to LICO's INP input, the first bit being the least significant (LSB) can be transformed into the INP input circuit, and the resulting linear PCM word, thirteen bits, consists of bl bits to b3 ( fig. 1) with the bit sign S = bl and the magnitude J = b2, ... bl3, is stored in the SRLC register. The signal bit S - bl is applied to the output circuit OC> and bits b2 to bl-3, defining the magnitude J, are introduced, in series, in SIPO2 by the time pulses TP and through. through the additive circuit circuitDD2 where the value c - 0 or c = 16 is summed to the value J depending on a conversion required in law A or law μ. So the word stored in SIPO₂is the changed entry word, J + c. Because bit b! 3 is the least bit. significant and has 2 °, the eight bits, b2 to b9, define the value (J + c) .2 “'*

<td colspan="6">which will be used to determine:</td>

<td>K = log₂</td><td colspan="5">(J + c / 2-⁴</td>

<td></td><td>s₇</td><td>And</td><td>s₃</td><td>S₄</td><td> .¾</td>

<td>k₇</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

<td>K₄</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td>

<td>K₃</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td>

<td>K;</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td>

<td>K</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td>

<td> 40 2</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

<td>K</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

<td>K0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

For example, SDEC₂ it comprises a plurality of delayed SI gates, defining the boolean function b2; b2. b3; b2 b3.b4;

...; b2 b3 b4 b5 b6 b7 b8. The output of each of these gates is connected correspondingly to one, from the exits

S7, .. S'0, directly and through the inverter to one of the other.

The last outputs S'0, S'i ... S7 of the SDECs are associated with the respective segments K0, Ki „.., K7 to which the decimal values ​​indicated X 'are assigned.

It follows from the first table that SDEC2 actually detects the first 1 of. bit series b2 to b9, except K0, and ignores the following binary values ​​in this series. This κ

This is done only by determining the highest power of 2 in (J + c) .2 ~ ''. This highest power defines the lower boundary of the segment, as will be explained later.

For this purpose the inputs b2 to b9 of the SCi to SC3 cells of SIPOi are connected to an SDEC2 segment decoder which transforms the following-

<td colspan="3">bad codes</td><td colspan="4">input binary,</td><td>eight</td>

<td>bit.</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td>

<td>b.</td><td>b-, t</td><td></td><td></td><td> 0</td><td>b₇ 1</td><td> &lt;!</td><td>b;</td>

<td> 1</td><td>X</td><td>X</td><td>V</td><td>..V</td><td>χ</td><td>X</td><td>X</td>

<td> 0</td><td> 1</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td>

<td> .0</td><td> 0</td><td> 1</td><td>X</td><td>X.</td><td>X</td><td>X</td><td>X</td>

<td> 0</td><td> 0</td><td> 0</td><td>Þ</td><td>X</td><td>χ ·</td><td>χ</td><td> '04.</td>

<td> 0</td><td> 0 -</td><td> 0</td><td> 0</td><td> 1</td><td>X</td><td>χ</td><td>X</td>

<td> 0</td><td></td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td>X</td><td>X.</td>

<td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> .0</td><td> 0</td><td> 1</td><td>X</td>

<td>Ό</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td>Js.</td>

<td colspan="2">wherein X</td><td colspan="2">has 0</td><td colspan="4">arbitrary value, in</td>

the following corresponding segment codes, 1 of 8, provided at the outputs of the same name of the SDECs:

S'i S'0 Decimal value K '

0 7

0 6

0 5

0 4

0 3

0 2

0 1

1 0 means that it detects the highest power of 2 and does not take into account the lower powers of 2. Thus, each of the segments K0 to K7 is defined by its lower limit. K0 is detected if all bits b2 to b8 are 0 and independent of bit 9, thus being sure of segment 0.

The outputs above S'0, S'1, ..., S7 are applied to the latch LCs bistable circuit and from there, they are sent to the ENC coding circuit which translates the segment codes 1 of 8, according to the last table given, in three-bit segment codes that are supplied to the OC2 output circuit via the latch LC7 bistable circuit.

During the operations described above, the value J + was switched - in SIPO2 a step to the right, so that bits b2 to b! 3 are now present at the outputs of the respective cells, SCi to SC12.

The value of the above step:

L - (J + c). 2-^K - d is now determined. For this purpose, the above decimal value of K 'can be used for segments K0 (law (7) and K2 to K₇ (both laws), but not for segment K0 (law A) because in this case the step size is equal to that for the Ku segment. To take this into consideration, the output signals S'0 and S'l of SDEC2 are transmitted to the circuit. logical LOG₂which provides at its outputs the signals §0 and Si:

S0 = S'0. A and Si - S'0. A '+ S'i

The output signals S0 to Sz, together with S0 to Sz, are applied, respectively, to the control inputs of the switches SW0 to SWz. As a consequence and depending on the decimal value of K ', this being 0, 1, ..., 7, its output, respectively, SC12, SCu, ... SCs is coupled to the input of SIPO3. By switching the contents of the cells, the left side of the mentioned cells can be obtained:

(J + c). 2-^K'

However, are only four bits switched to four SIPO cells? So the following binary values ​​are stored in them:

- for K0 (law μ) blO bll b! 2 bl3 - for K0 (law A) b9 blO bll bl2 and Ki (laws A and μ) - for Kz (laws A and μ) b3 b4 b5 b6

Thus, each time the previous bits are ignored, these bits in state 0, except the last one which is 1 for segments K0, (law μ) and K1 at Kz (both laws) and in state K0, for segment K0 (law A). · In other words, bits b9 (K0, law μ) and b8 (K1, both laws) up to b3 (Kz, both laws) are 1, while b8 = 0 (K0, law A). If these bits are not taken into account, one can extract .1. 2⁴ or 0. 2⁴ from the value stored in SIPO₃. In this way, this value is really the 4-bit passcode:

L (J + c) 2- ~^A - 16 or L = (J + c) 2 "^ofas required.

The content of SIPO3 is blocked in LCî and thus the three-bit segment code and the four-bit pass code are applied in series at the OUT output.

The converter, according to the invention, has the advantage that it performs the conversion for both the law A and μ the selection being made through a control bit.