Pulse code modulation (pcm) translator for translating a pcm input word into a pcm output word shift register cell and multiplier device used in that translator

CODED MODULATION PUSH TRANSLATOR (PCM) FOR

TRANSLATE A PCM INPUT WORD into a PCM OUTPUT WORD; DISPLACEMENT REGISTRATION CELL AND MULTIPLIER DEVICE USED ON THIS TRANSLATOR

Mod 71-10000 ex.

Translators adapted to translate a linear PCM code into a PCM code composed according to A or mu laws and vice versa are described. · Each translator calculates a relatively simple corresponding function in which only a single parameter (K ​​·) is dependent on a control bit (A) whose value indicates law A or mu law, respectively. Also described is a shift register cell and a multiplier device used in these translators. The present invention has been implemented in a 2-mm silicon area using NP-CMOS semiconductors.

For further clarification, Figures n^fis · 1 and 4 of the drawings, as shown below

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TO 1

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FIG.4

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739

D. Rabaey - D. Iíaspeslcigh 2-2 (UK)

-χ · οοο οι - u pon

Description of the object of the invention which

INTERNATIONAL STANDARD ELECTRIC CORPORATION, North American, in dustrial, headquartered at 320 Park Avenue, New York, New York 10022, United States, would like to obtain in Portugal, FOR CODED MODULATION IMPULSION TRANSLATOR (PCM) TO TRANSLATE A KUIIA INPUT PCM OUTPUT PCM / MULTIPLIER DEVICE TRANSMITTER AND CELL, USED IN THIS MODEL TRANSLATION USES IN THIS MODEL TRANSLATOR Encoded (PCM) to translate an input PCM word into an output PCM word, one of said words according to a compressed code and the other according to a lenear code.

It is an object of the present invention to provide such a translator, which is adapted to selectively perform translation according to A-law or mu-law and yet is of a relatively simple structure.

In accordance with the present invention this object is achieved because the translator is adapted to convert the binary bits of the input word to the output word according to laws A or mu as given by the value. binary of a selectable control bit, which determines the digital values ​​of various translator parameters.

By using the selectable control bit

<img file="PT79225B_D0005.tif" />

55.739

D. Rabaey - D. IR-sposiugh 2-2 (Portugal) The translator is adapted to selectively perform a translation of accrdc with the A or mu laws and, because this bit controls various translator parameters, it can be given to this translator. The latter is a simple structure that is practically the same for both laws.

Another characteristic feature of the translator according to the present invention is that he is adapted to translate an input compressed PCi1 word, which includes a 3-bit code segment and a 4-bit stepped code into an output linear PC1i word, by determining the function

J = (L + a, 2⁴ ± b, 2 ^_1). 2^k' you

Mod. 71-10000.x -00-84 wherein J is said output word;

L is said stepped code a, b and b are variables;

K * is related to said stepped code and is dependent, along with said variables a, b and c, of said control bit (A) indicating that said input word is encoded according to laws A or mu.

It follows from this function that the operations to be performed for the Á or mu laws are very similar and only differ in detail, because it is possible to use the same translator structure for both laws, as already mentioned.

Still another characteristic aspect of the last mentioned translator is that it includes:

decoder means for decoding said 3-byte code segment into a code of 1 in 8, S7.

-255.739

D. habáey - D.Háspeslagh 2-2 (Portugal)

<img file="PT79225B_D0006.tif" />

- logic means coupled to said decoder means and controlled by said control bit, providing the variables:

a = Ξ'JD * ab = S¹! ΠΡί + a)

0 · A = S'0. X ♦ S'l constituting the codeword 37, ··. ·, Sl, S0 an altered code segment with a decimal value K ';

means for modifying said stepped code L by said variables a and b to obtain an altered stepped code.

Mod 71 - 10,000 · χL * a.2⁴ + b.2¹

means multiplier coupled to said modifying means for multiplying said scaled code alteL · I Λ r with 2 to obtain the product (L + a.2 * • b.2 '¹) . 2*’

- and additional means coupled with said multiplier means and controlled by said control bit to add said variable c to said product to obtain said output word J.

The translator is thus capable of performing a translation according to both law A and mu law under the control of a selectable control bit and by the use of relatively simple logical means.

A further characteristic feature of the translator according to the present invention is that he is adapted to translate a linear PCM input word into an output compressed PCM word that includes a 3-bit code segment and a

-355.739

D. Rubaey - D. H. speslc * gh u-2 (Portugal) ~?

Mod. 71 - 10,000 '.

<img file="PT79225B_D0007.tif" />

4-bit step code, determining the functions

K = Log₂ / \ j * c). 2^_47th L = (J + c). 2^Kwhere d is said input word;

K is said code segment;

L is said stepped code; c and d are variables

K 'is related to said code segment and is dependent, along with cad, of said control bit (A) which indicates that said output word is encoded according to laws A or mu.

From these functions it follows once again that the operation to be performed for the ae mu laws is very similar and only differs in detail due to the _HYou can use the same translator structure for both laws.

Further, a feature of the above mentioned PClí transcoder is that it includes:

adding means controlled by said control bit to add said variable c to said input word J in order to obtain an alternate input word J + c and store it in a shift register;

decoder means coupled to said shift register to decode the 8 most significant bits of said changed input word J + c into a code of 1 in 8, Σ7, C,. ·, S'l, S0, but only taking into account the higher energy activated bit of the modified input word reference;

55.739

D.Rabaey - D. iiaspesl '.gh c.-d (Portugal)

<img file="PT79225B_D0008.tif" />

Mod. 71. 10,000 encoding means coupled to said decoding means for encoding said 1 in 8 code for said 3-bit code segment K;

logic means are coupled to said decoder means and controlled by said control bit and providing the variables:

= S'0. THE

SI = S'0. a + S'l having the codeword the decimal value K *;

- means multipliers and additions to multiply

-K 'said altered input word J ♦ c by 2 and adding said -da variable of that product to obtain said stepped code L.

The present invention also relates to a shift register cell with a data input coupled to a data output via a cascade connection of an input memory circuit and an output memory circuit. This shift register cell is characterized in that it also has an auxiliary data input, said auxiliary data input and the output of said first memory circuit being coupled to the input of said second memory circuit through the respective first and second means. have a control input in common and such that they are always in a state of opposite conductivity.

The present invention further relates to a multiplier device for multiplying a binary word stored in a first 2-shift register.^X, with x = 0, ... K, moving said word through x phases of said shift register.

This multiplier device is characterized by the -5Mud ι 1 - lu UUU o *

55,739 hiSSiJ

D.Rabaey - Da-sperl-gh c .- d (Portugal) KfâggHa said displacement record including phases ia sauc. of the first shift register being coupled to the faq and K of said shift register by means of the respective first gate means of K which are controlled by respective bits of a binary code 1 in K-x and which has said decimal value because one or more of the phases are associated with a second half * of the door, the following gate means being controlled by the respective control bits all such that when establishing first gate means performing a connection between the first shift register and a phase of the second shift register, the last phase is isolated from the other phases of such a shift register by the second gate means associated therewith.

The objects and features of the present invention will become more apparent and the invention itself may be better understood by reference to the following description of an embodiment taken in conjunction with the accompanying drawings in which:

Fig. 1 is a schematic block diagram of an LC2 telecommunication line circuit including a PCM, TC translator circuit in accordance with the present invention.

THE? Fig®. 2 and 3 represent the COLI and LICO elements of this translator circuit, respectively, in greater detail;

Fig. 4 is a detail view of a schematically seated recording cell in Figs. 2 and 3}

Fig. 5 represents regulating impulses to control the translator.

As shown in Fig. 1, the TC translator or transcoder circuit is part of an LC telephone line circuit connected between an L1 telephone line and a SIIW digital switching network and comprising a connection.

-655.739

D.Rabaey - D.Haspeslagh 2-2 (Portugal)

Mod 71 - 10,000 · κ.

<img file="PT79225B_D0009.tif" />

cascading a SLIC subscriber line interface for line supervision and control, a digital DSP signal processor primarily adapted to perform analog to digital and digital to analog conversion operations, the aforesaid transcoder circuit TC is a dual processor DPTC terminal controller that deals with the overall control of the line circuit. 0 DSP only processes linear PCM signals, while DPTC only operates on composite PCM signals. The purpose of the TC transcoder circuit and more particularly of its COLI circuit is therefore to transcode compressed expanded PCM signals received from the DPTC signal into its INI input terminal into linear PCM signals which are then transmitted to the DSP via the OUTI output terminal and vice versa in the LICO circuit for signals received at input terminal IN2 from DTP and transmitted via output terminal 0UT2 to DPTC. 0 TC is used in common for eight DCP and SLIC circuits as indicated by the multiple arrows but could be used for up to 32 DPS and SLIC circuits. In fact, the data received at and transmitted by the TC is part of a 32 channel rack of which only 8 are actually used and each channel has a repeating period of 125 microseconds. The data bits exchanged between TC and DPS have a bit capacity of 4.09Ó Kbit / sec. and each of the channels used contains a 16-bit PCM signal of which the 13 bits from bl to bl3 together constitute a linear PCM signal. Bit bl is the sign bit S and bits b2 through bl3 define the absolute magnitude J of the signal. The bl bit is preceded by two identical bits and the bl3 bit is followed by a usable bit. as a rounding bit. This 16-bit pattern is received, for example, in a form in which all bits are inverted and the second's complement has been removed.

The data exchange between TC and DPTC has a bit capacity of 2,048 kbit / sec. and each of the channels used contains an 8-bit compressed-expanded PCM signal comprising bits b through b8. This PCM signal is encoded according to segmented A or mu logarithmic laws, comprising

-755.739

D.Rabaey - D.iLaspesl ^ gh 2-2 (english)

<img file="PT79225B_D0010.tif" />

'V

Mod 71 · 10 000 · χ «(Ρ * each of them 8 segments for each of the worthy values ​​Ξ indicated by bit bl. The 3 bits b2a b4 define a segment k between 8 possible segments kJP to K? bits b5 to b8 define a step L out of 16 possible steps within the segment According to law mu the relative step length values ​​in segments Kf5 to K 'are equal to 2 respectively, whereas in law A they are 2 7th

2, 2, 2, ..., 2, respectively. Does this mean that the step size in segment Kj3 according to law A is twice the size of the step in segment Kj? according to the mu law. The compressed expanded PCN signal bl through b8 is, for example, received from and transmitted to the DPTC in a manner in which all bits except the sign bit are inverted (mu law) or only the odd bits are inverted. (read).

Reference is now made to Fig.5 θ to Fig.2 which represent the CCLI circuit of the TC transcoder which is adapted to transcode a PCI signal or word! 8-bit compressed-expanded into a 13-bit linear PCK word or signal.

CCLI circuitry includes an INPI input circuit, a SIPOL serial input and parallel output register, a PISO serial input and parallel input register, an SR offset register, an SDEC1 segmental decoder circuit, an ADD1 add-in circuit, a 0C1 output circuit, an LCG1 logic circuit, LC1 to LC4 truncation circuits, a GC gate circuit, and a TC regulator circuit that generates regulator pulses of which only TP1 to TP7, required to explain the operation of the COLI circuit are shown in Fig. 5. The locking circuits LC1, LC2, LC3 θ LC4 are controlled by TP2, TP4, TP3 and TP5 respectively and the GC gate circuit is controlled by · TP6.

The INI input of the COLI circuit is coupled via the INPI input circuit to the input of SIP01, cu-855.739 iJililiMil ·

D.Rabaey - D.Haspe slagh. 2-2 (Portugal) 1¾¾¾¾¾¾The outputs are coupled to the Lcl inputs having outputs from R1 to R4. The output R1 is connected to the CCI output circuit via lockout circuits LC3 and LC4; outputs R2 to R4 are connected to their respective SDC1 inputs and R1 to R4 are further coupled via LC2 to data inputs 3 of PISO PC2 cells Pc5. The latter comprises PCI to PCC interconnected cells with common control inputs 4 controlled by the TP7 regulating pulses as well as common control inputs 5 controlled by the regulating pulses ΤΡ3. except for PCI input 1, which is connected to ground and to output 2 of PCó which is connected to common data input 3 of cells PC11 to PC18 of SR.These latter cells also have interconnected control inputs 4 controlled by TP1 i-egulatory pulses as well as individual control inputs 5. 0 SDEC1 segmental decoder circuit has outputs S'0, S'le S2 to S? of which S2 to S? are coupled via LC3 and LC4 locking circuits and cascaded GC grid circuit to the last-mentioned control inputs 5 of SR cells PC13 to PC18. SDEC1 outputs S * J3 and S'l are coupled via LC3 locking circuit to logic circuit inputs LCG1 which have another control input A, and outputs a, b, and Sl, S £>. Control input A is indicative of laws A or mu, so 0 and 1 respectively. Outputs a and b are linked via LC4 to data inputs 3 of PIS01 PCI and PC6 cells, respectively ^ while outputs S0 and Sl are cascaded to the control inputs 5 of PC11 cells cascaded via LC4 and GC and PC12 from SR, respectively. PC11 output 2 is coupled to output circuit 0C1 via an add-on circuit ADD1 which is also controlled by control input A above.

Each of the PISO PCI to PCó cells is of the type shown in Fig.4 and is considered only with switch55.739

D.Rabaey - D.Haspeslagh 2-c: (Portugal)

Mod 71 * 10 ΟΟΟ · Χ ·

<img file="PT79225B_D0011.tif" />

<img file="PT79225B_D0012.tif" />

Sl e and includes two identical input and output circuits. The cell input circuit comprises PMOS, PM1 and PM2 transistors and NMOS, NM1 and NM2 transistors whose passages from source to discharge and discharge to source are connected in series between V + and ground.

The interconnected ports of PM1 and NM2 and the interconnected discharges of PM2 and NM1 constitute input I and output 0 of the cell input circuit, respectively, and the ports of NM1 and PM1 are controlled from control input of cell 4. , directly and via INV1 inverter, respectively. The constituent components of the output circuit are indicated by the same digits as those of the input circuit to which, however, a single addition is added. The do and PM'2 ports are now controlled from the control input of cell 4 via inverter INV1 and directly respectively. Input I and output 0 'are connected to serial data input 1 and serial data output 2 of the cell, respectively, and a parallel data input 3 is coupled to the common outputs 0 and input I' of the cell input. and the output circuits through a switch Sl. The latter comprises a PMCS transistor, β and a NMOS transistor, NM3, whose source and discharge are connected to the discharge and lead electrodes of NM3 and PM3, respectively. The ports of N1T3 θ PM3 are controlled from control input 5 directly and via an INV2 inverter respectively. It is evident that switch Sl is closed when control input 5 is activated (1).

Each of the SR cells PC11 to PC18 are also of the type shown in Fig. 4, however, to be considered with both Sl and £ 2 switches. Switch S2 is of the same structure as switch SL but PM4 and N1I4 are now controlled from control input 5 directly and via inverter IHV2, respectively, so that switch S2 is closed when control input 5 is disabled (0).

A PISO PCI / 6 cell circuit operates as -1055.739

D.Rabaey - D.Haspeslagh 2-2 (Portugal)

Mod. 71-10000 ex.

Follow. For entering and transferring data from serial input 1, control input 4 is alternately activated and deactivated and control input 5 is kept disabled, while for inputting and transferring data applied to another data input 3, input inputs 5 and 4 shall be activated and deactivated simultaneously respectively. In the first instance, the data applied to the series 1 input is inverted in the cell input circuit and locked in the cell when control input 4 is activated and then inverted in the cell output circuit and transferred to cell 2 output. when control input 4 is disabled. In the second case, the data applied to parallel data input 3 is inverted and transferred to cell output 2 when control inputs 5 θ 4 are activated and deactivated respectively. Indeed:

- when control input 4 of the cell circuit is activated, the NM1 and PM2 of the cell input circuit are conductive, while Ρϊ.ί · 2 and ΝΙΙΊ of the cell output circuit are blocked *;

Thus the discharge electrodes of PH1 and KM2 are connected in common to output 0 for fear that the cell input circuit acts and an inverter for data applied to its inputs I or 1;

- when control input 4 is deactivated the above mentioned roles of the input and output circuits are inverted;

- when control inputs 5 θ 4 are simultaneously activated and simultaneously deactivated, the data applied to input 3 is applied via switch 51 to the cell output circuit and inverted there and applied to cell 2 output.

5R's PC11 / 18 cell circuit works in a similar way as described above for the

<img file="PT79225B_D0013.tif" />

PC1 / 6, but now the cell input circuit is disconnected from the cell output circuit by switch S2, when regulating switch £ 1 is closed and vice versa, since these switches are controlled by opposite control signals. .

Mod 71 - 10,000 · Χ - W-34

It can be shown that a suitable algorithm for transcoding an 8-bit compressed-expanded PCM word comprising bits bl through b8 with the sign bit S = bl the segment code K = b2b3b4 and the stepped code L = = b5bob7b8 into a 13-bit linear PCM word J. It is given by

J = 2^k'(L + 2.2⁴ + b.2¹) + c or J = J ¹ + c where:

- c = 0 for law A and c = 16 for law mu:

- K 'is 0 to 7 for segments K0 to K7, except for segment Kf5 in law A for which this value is 1 instead of 0;

a = b = 1 for segments K2 to K7 in both laws and for Kl in the mu law; so that

J '= 2^k'(L + 2⁴ + 2¹)

-a = leb = 0 for segment K0 (mu law) and Kl (law A) a = leb = 0 so that

J · = 2^k (L + 2⁴)

-a = b = 0eK '= 1 for segment K0 (law A) so that J1 = 2.L COLI circuit described above is adapted to calculate this algorithm in the manner described hereinafter.

-1275,739 gt.Rabaey - D.U.

Mod 71 - 10,000.x

<img file="PT79225B_D0014.tif" />

Is a compressed expanded PCM signal applied to the CCLI1 INI ground, with the most significant bit (ΙΤ'Έ) first, possibly transformed into the INP1 input circuit and the 8 bit compressed expanded PCM signal? The resulting sequence, comprising bits a through b8 (Fig. 1) and defining S, K and L above, is introduced serially into SIP01 as two successive sets of four bits a through b4 and b> a b8.

Starting with the four bits bl through b4, they are locked in the locking circuit LC1 under the control of a first regulating pulse TP2 (Fig. 5). ^no bit sign S = bl is thus introduced into the output circuit 0C1, while the 3 bit code segment K = b2b3b4 is applied to the SDEC1 segmental decoder where it is decoded into a 1 in 8 segmental code consisting of the bits.

S7 Only S5 £ 4 £ 3 S2 S »1 S '0

<td>proportionate</td><td colspan="2">nas r:</td><td colspan="7">similarly referred to as the</td>

<td>CDEC1. This one</td><td colspan="2">code</td><td>in</td><td>fine</td><td>the</td><td>follow nt</td><td>• the K0</td><td>to K7 of</td><td>wake up</td>

<td>with the frame</td><td colspan="3">Following</td><td></td><td></td><td></td><td></td><td></td><td></td>

<td>S7 33</td><td></td><td> £4</td><td>S3</td><td> 09</td><td>S'l</td><td> £ ’0</td><td>Value</td><td>decimal</td><td>K ·</td>

<td>K0 0 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td></td><td></td>

<td>Kl 0 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> 1</td><td></td><td></td>

<td>K7 10</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td>no t</td><td></td><td></td>

Thus each of the output terminals 5 * 0; SDEC1's S * 1, £ 2 ..., S7 is activated for one of the corresponding segments K0, Kl, K2, ... K7 θ the decimal values ​​of K '= 0, 1, 2, ..., 7 are distributed across these segments. However, according to the above algorithm, this is not correct for segment K0 in law A, since the value of K¹ must then be 1 instead of 0,

Under the control of a first TP3 throttle, -13-

<img file="PT79225B_D0015.tif" />

55-739

D. Rabaey - 3 H ^ spesi ^ gh 2-2 (United Kingdom) bit bl s the 3DEC1 output code 3 * 0, 3 * 1, 32, ... 37 are locked in LCj so that bit 12 377 are applied to the LC4 truncation circuit, while bits 3 * 0 and 3 * 1 are provided to the logic circuit L0G1 which is used to calculate the above a and b values ​​of the algorithm according to the law used (indicated by A). also to calculate the correct k * value for segment K0 in law A. At its outputs a, b, 30 and 31 of circuit L0G1 it provides the signals with the same denomination &lt;- y

Mod 71 - 10,000 ex · W-4 a = S'0 -t- ab = 375 (sTL -ra) £ &lt;0 - o * 0 »A - c * 0. λ + 3 * 1 and from these relationships it follows that as requested by the above algorithm:

a = b = 1 for segments K2 to K7 in both laws, A and mu, characterized by A = 0 and A = 1 respectively;

a - 1 and b - 0 for segment K0 (law mu) and Kl (law _THE);

a = b = 0 before segment K0 (law _Λ) so that the segmental-above data codes are now modified and provide the following changed segmental codes:

<td></td><td></td><td></td><td> 37</td><td>Only</td><td> 35</td><td> 34</td><td>S3</td><td> 32</td><td> 31</td><td> 20</td>

<td>K0</td><td>(mu)</td><td></td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td>

<td>K0</td><td>(The)</td><td> (</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td>

<td>and</td><td>Kl</td><td> (</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td>

<td>K7</td><td></td><td></td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td>

<td colspan="2">So the</td><td>value</td><td>dec:</td><td colspan="2">Lmal K¹</td><td> 1 -</td><td> 1</td><td colspan="3">is now assigned to K0 in</td>

-14Mod 71 - 10,000 · «.

<img file="PT79225B_D0016.tif" />

ccmo law is required.

During the operations described above c second bit set b ^ bó b? b8 which defines the staggered code L was introduced in CIF01. These bits are locked in LC1 under the control of the second regulating pulse TP2 represented and then locked in LC2 by the regulating pulse TP4. As a result these bits b5 to bC are applied to the data inputs 3 of the respective PISO cells PC2 to PC5.

By means of a subsequent TP5 throttle the bits bl, £ 0, 51, £ 2 to £ 7 as well as a, b on the outputs of LC3 and L0C1 are locked in the locking circuit uv 4 · θ m “resulting than the bit bl is given at 0C1, S bits are applied to the GC port circuit, and bits a and b are provided to the PISO PCI and PCó cell data inputs 3, respectively. 0 altered stepped code consisting of bits a, b>, b6, b?, b8, b is now entered into the FLOOR under control of the second TP3 regulating pulse and then inverted and transferred to the outputs of the PCI to PCó cells, because the regulating impulse TP7 θ antão deactivated. Consequently Z, b5, bo, b ', b8 and * b are then present at the outputs of these cells.

In this way the staggered code changed,

L> a.2⁴ f b.2¹ with the inverted bits, it is stored in the PCI to PC6 cells to which the values ​​4 -1 to 2 are respectively distributed. Following the algorithm this value should now be multiplied by 2 to obtain the above J value. This will be described from now on.

Because of the negatively oriented regulating pulse TP mentioned above, also bits £ 0, £ 1 and S2 to 37 are applied to control inputs 5 of the respective £ R cells PC11 to PC18 and because only one of these bits is set.

-1555.739

D.Rabaey - 0. H ^ pe-Ί-gii 2-2 (Portugal)

Mod 71 - 10,000 '.

<img file="PT79225B_D0017.tif" />

In paragraph 1, the switches Sl and £ 2 are only closed respectively, in the cell to which this bit is aborted and closed in all other cells respectively. Thus, a connection is established between PICO output 2 and SR PC11 output 2 via a number of cells equal to the value of K '. For example, for segments £ 0 and £ 7, switches Gl and S2 are closed and grounded in PCI cells! and PC18 associated with these segments.

Under the control of six TP7 regulating pulses, applied to the PISO control input 4 and the TP1 regulating pulses provided to the SR control input 4, the above bits * b, b8 t7, bu, b7 and are offset. through the cells linked in PICO and SR series, taking place an inversion of the first used GR cell. In this way the Vo.lor stored in the FLOOR is inverted and multiplied by a factor equal to ^ 2, so that the above binary value J¹ is obtained at the output of the 3R.

According to the above algorithm, both a value c - 0 for the law and a value c = 16 for the law mu must alternatively be added to that value J 'to obtain that of the value J This is done on the adDi circuit and is controlled by the same control input. _Λ as LCG1. The resulting J and the sign bit £ are then combined into output circuit 0C1 and possibly transformed before being supplied to output terminal 0UT1.

Referring now to Fig. 4 which shows the TC transcoder LICO circuit which is adapted to the TC transcoder which is in turn adapted to transcode a 13-bit linear PCM word into an 8-compressed expanded PCE word bits. Like the CCLI circuit, the LICO circuit is controlled by a regulating circuit which, however, is not now presented as it is obvious from the description of the operation of the LICO circuit which will be given below.

-ló55,739

L.Rabaey - D.Haspeslagh 2-2 (English)

<img file="PT79225B_D0018.tif" />

Mod 71 - 10,000 · μ. - 09-44 LICC circuit includes an LNP3 * input circuit, a 13 cell shift register and the CRLC coupling circuit, two IP02 and 3IP3 parallel input and serious input registers, a CLEC2 segmental decoder circuit and a ENC encoder circuit, an add circuit_ΛϋΏ2, a logic circuit L0G2, coupling circuits LC5 to LC7, output circuit 0C2 and switches

S '.'! 0 to ΞΪ.7. CIP02 and SIP03 cells are of the repeat type in lig. 4, however, to be considered without Cl and S2. Its control inputs 4 are common and controlled by TP regulating pulses (not shown). Switches C7 / 0 to 37/7 are similar to those used in the COLI circuit and as shown in Fig. 4.

The LICO circuit input 1112 is connected via the IFP2 input circuit to the CRLC which includes 13 cells and has an output coupled via the ADD2 add circuit to input 1 of the CIP02. An output of the first cell of the CRLC is connected to output circuit 0C2 and the add circuit ADD2 is controlled by control input A, which is the same as that of COLI circuit and is therefore 0 for law A and in 1 to the mu law. 0 SIP02 comprises 12 SCI to SC12 interconnected cells, which have outputs that are connected to the inputs of the segmental decoder SD2C2 which have outputs C'0, £ ', £ 2, ..., coupled, saw. LC5 coupling circuit to the ENC encoder. The outputs C'0 and C'l of the SD2C2 are also coupled to the logic circuit inputs L0G2, which is also provided with the control input A and which has outputs C0 and Cl which are connected to LC5. These outputs 20 to 27 of the LC5, as well as their inverse COs to S7, are connected to the control inputs of the switches 5Y 0 to 37/7 respectively. The data inputs of these switches are wired to the outputs of the respective DC cells> 2C12 of PIS02 and their data outputs are common and are wired to the input of CIP03. The outputs of CIP03 θ and those of the ENC encoder circuit are connected via respective coupling circuits LC6 and LC7 to the output circuit 0C2 whose

-1755.739

D. iubiesy - D. H. spesl ^ h 2-a (Portugal) exit 0UT2 constitutes the exit of LICO.

<img file="PT79225B_D0019.tif" />

It can be shown that a suitable algorithm for transcoding a 13-bit linear PCM word comprising bits bl through bl3, with the igno-bit 3 = bl and a magnitude of J defined by bits b2 through bl3 in a compressed PCM word -expanded 8-bit with a sign 3 bit, a K segment and an L phase, is given by:

K = Log₂Δ (J + c). 2^_47th and L = (J + c) .2^{k &lt;}- d where

Mod 71 - 10,000.x.

c = 0 for lei A; c = 16 for rau law;

and with K. ' 0 to 7 θ d = ló for segments K0 to K7, except for segment K.0 in law a for which this value is 1 instead of 0 and for which also d - 0. You should note that for K c a lower limit is calculated.

The LICC circuit described above is adapted to calculate this algorithm as described below.

An input linear PCE word input to the LICO INP2 input with the least significant bit (L3B) first is possibly transformed into the input circuit IIIP2 and the resulting 13-bit linear PCM word comprising bits bl through bl3 ( Fig. 1) with the sign bit = bl and the magnitude of J = b2 ....... bl3 is stored in the SRLC register. The sign bit C = bl is applied to the dc output circuit 0C2 and bits® · b2 to L13, which define the magnitude J, ® are inserted into^tNo 3IP02 by the regulating pulses TP and via aDD2 add-in circuit where c - o or c = 16 is added to the value of J, depending on whether a conversion to law A or mu law is required (as indicated by the control input THE). Consequently, the

<img file="PT79225B_D0020.tif" />

55.739

bR-baey - D. H-speslagh 2-2 (UK)

Mod 71 - 10,000M.

The word stored in CIPC2 is the changed input word J -r c. As bits I3 are the least significant and have the

At weights 2, the tits cites b2 through b9 define the Value (J + c).

2 ”\ ue now uc-do to determine

K = Log₂ (J + c). 2⁴

This is made detent of (J + c). 2^-4. This is lower than and eg only by lowering this energy, as the higher energy of 2 will be, defines the threshold explained below.

To this end, the C1P02 SCI to CCG cell inputs b2 through b9 are linked to an obvious CLECa segmental encoder, which transforms the following 3-bit binary input codes b2 b3 b4 b5 1 χ χ χ

1 XX 0 0 1 X 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 good b7 b8 b9 XXXX

XXXX

XXXX

XXXX

XXX

1 XX

0 1 X

0 0x

-19Where X has an arbitrary value in the following corresponding 1 in 8 segment codes provided on outputs with the same name as CDSC2

55.739

D. Rabaey - D. Haspeslagh 2-2 (Portugal)

Mod. 71 - 10,000 · χ.

<td></td><td>S7</td><td>Only</td><td>C 1</td><td> 5 24</td><td></td><td> 22</td><td> 2 ’</td><td> 1 2</td><td> )</td><td>Go</td><td>or</td><td>decim</td><td>ci.1 0 ©</td>

<td>K7</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td></td><td></td><td></td><td> 7</td><td></td>

<td>K6</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> )</td><td></td><td></td><td>✓ O</td><td></td>

<td>K5</td><td> 0</td><td> 0</td><td>1 i</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> )</td><td></td><td></td><td>ç' z</td><td></td>

<td>K4</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> )</td><td></td><td></td><td> 4</td><td></td>

<td>K3</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> 0</td><td> )</td><td></td><td></td><td> 3</td><td></td>

<td>K2</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> 0</td><td> )</td><td></td><td></td><td> 2</td><td></td>

<td>Kl</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> 0</td><td> )</td><td></td><td></td><td> 1</td><td></td>

<td>K0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 0</td><td> 1</td><td> )</td><td></td><td></td><td> 0</td><td></td>

<td></td><td>0 2 DEC 2</td><td colspan="2">inci</td><td>wow</td><td>rf!</td><td colspan="2">example</td><td>1c,</td><td>an</td><td>plur</td><td>al^J</td><td>Lda.de</td><td>por-</td>

<td>t CtS</td><td colspan="3">regulatory</td><td>AND</td><td>what</td><td>huh</td><td colspan="2">end</td><td>the fun</td><td>.dog</td><td>in</td><td>Eoole</td><td>b2;</td>

<td>b2.</td><td colspan="3">b3; 52 53.</td><td> 54;</td><td></td><td> •</td><td> 52</td><td>E3</td><td> 54</td><td></td><td>5th</td><td> 5 57</td><td>bb.</td>

The output of each door? is connected to a single of the corresponding output terminals 27 .... 3 * 0, directly and via inverter to the others.

The last output terminals, 2'1 ..., 27 of the

Are 2D2C2 associated with the respective segments EjP, Kl, .., K7 for which the decimal values? KJ nominees are distributed.

From the first table above, it is apparent that £ D'2C2 actually detects the first 1 of bit series b2 through b9, except for Y.0 and ignores? Mon_Ui_not_and? binary values ​​in this series. This means that it detects the highest energy of 2 and does not take into account the smallest energy of 2. Yes, each of_Qg_Rientcs K0 to K7 is defined by its lowest value. KJ3 is detected if all bits from t2 to bS are 0 and regardless of bit b9> since I fear? sure this is segment 0,

The above outputs G * 0, £ ·!, .... 27 are appli-2055 · 739 D. Rctbaey

-Li.H-speei ^ gu 2-2 (Portugal)

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each * to coupling circuit L2> '2 hence ^rA given Lh'C encoder which translates the 1 · 3 segmental codes 1 according to the table provided is finally provided in 3-bit code segments which are introduced via the LC7 coupling circuit into the output circuit. CC2.

During the * operations described above the value J + c shifted one step to the right in 2IP02, so that bits b2 ab! 3 ^andand are now present in the outputs * of the respective cells SCI to SC12 thereof.

Af phase value above

Mod 71 10,000 · κ · - Οβ-β *

L = (J + C). 2"^K-d is now determined. Coli and ** the purpose the referred decimal decimal value of K * may be_er It is used for segments K0 (law mu) and K2 to K7 (both laws), but not for segment K0 (law ã) because in this case the phase size is equal to that of segment K1. To s_s take this into account. The output parameters S'0 and 2 2D of the 2D2C2 are supplied to the logic circuit. LdC / 2 provides at its outputs 20 to 21 the signals. 20 = S'0. I and 21 = 2'0. λ + S'l

The signals 20 to 27, together with ΙΓ0 to T7, are applied to the * control * input * of switch * S '”0 to 27.'7, respectively. 2m consequence di ** o and depending on the decimal value of K 's_5r 1, ...., 7 output from 2CJ2 2CI1, ..., 2C5, respectively, and * is coupled to the input of 2IP03. Shifting the cells in the cell to the left of the last cells mentioned would give the value.

(J + c). 2^K'

However, only &lt;· β shifts four bits to a *

-2155.739

3 Rabaey - 3. Ha-po-lagh dt. (Portugal) / tuple 3IPC2 cell *, so the? value * * following * * ejaa M ^ jazenudop

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binary 'to K0 (mu law) blo Ml - to K0 (law b'9 blO b! 2 bl3 bll bI2

Mod 71 - 10,000 - κ - 00-04

-for E7 (law ae nu) bj t4 b> 5 tc a * eL · ;, each time ignore * and the preceding * bit *, * bit * en 0, with the exception of the last en 1 for * * egment *

K0 (naked law) and K1 to K7 (anta * a * law *) and 0 to * egmen to K0 (law A). another * word *, the * bit * b9 (K0, mu law) and bo (Kl, anta * a * law *) for fc3 (K7, both * a * law *) * 1, while b «C ( E0, law A.), ..does not take into account e * te * bit * * ubtrai- * and indeed 1.2 or C 2 of the * value * stored * in 31PC2. Therefore e ** and value is actually the 4 bit e * heat code *

L - (J * c) 2 “^K‘

K ' _or L = (J + c) 2 -^k , as required **

The content of the 3IP03 is coupled to LCó and as * im applied to the * Mda CC2 circuit. There * igno, the 3 bit code egmer, and the 4 bit code are entered in the 0UT2 range.

Although the principal of the present invention has been of credit for a specific purpose, it should clearly be understood that this is the case. Creation is made by way of example only and has no limit within the scope of the invention.

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The first application for the invention described above was filed in Belgium on 19 September 1933 under no.^and. 2/60209 (BE Stop 897,775).

Mod 71 - 10,000 · χ. «09-84