Continuous synchronous encryption and decryption in a wireless communications system throughout handoffs.

DESCRIPTION

CONTINUOUS SYNCHRON ENCODING AND DECODING IN A TRANSFER WIRELESS COMMUNICATION SYSTEM

Field of the Invention

The present invention relates generally to radio communication systems, and more specifically to two-way radio communication systems comprising a method and apparatus for synchronous encoding and decoding.

Background of the Invention

Synchronous counter coding techniques for complete dual digital wireless communication systems are well known in the art. Such systems usually employ separate encoding and decoding devices in each communication unit for encoding and decoding a transmission and receiving rail, respectively. The use of separate encoding and decoding devices in each communication unit makes the communication unit more expensive and bulky, making synchronizing the two devices even more complicated.

In order to maintain synchronization between the two connected communication units, conventional systems must transmit a coding sync signal (Esinc) simultaneously with the coded information. E-sinc transmission is not a problem when information consists of stored data, which can be interrupted without problems. On the other hand, transmitting an E-sync signal in a voice communication system becomes somewhat more difficult as voice information is continuous and cannot be interrupted periodically to transmit an E-sync signal.

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without noticing the presence of transmission gaps or noise in the received voice audio signal.

Some conventional voice coding systems periodically "steal" bits from voice information and use the stolen bits for E-sinc transmission, with the theory that if the bits are stolen only sporadically, its absence will not substantially degrade the voice audio signal. Still, the missing bits somewhat degrade audio voice quality, so coding systems based on the use of stolen voice signals do not rank so well in subjective audio quality tests when they are found. in a coding mode of operation as compared to classification in a non-coded mode, that is, open mode.

Another problem with conventional coding techniques used in wireless communication systems, which can transfer a portable communications unit (CPU) from one fixed communications unit (UCF) to another is associated with the transfer procedure. The problem arises because when the two communication units are connected, the communication device for the communication rail of each of the two communication units provides the decoding device E-sync signal rail in the corresponding receiving rail of the another communications unit. Thus, after a transfer to a new UCF, encoding synchronization is lost for a period of time that is required to resynchronize the decoding device in the CPU with the new UCF E-sync and the decoding device. of the new UCF with the E-sinc from the CPU.

Since the loss of coding synchronization would cause all reported information to be lost during the time frame to be synchronized subsequent to the transfer, conventional coding systems for sending continuous information such as voice must be returned. to clean operation before each transfer, followed by a return to

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operation after sufficient time has elapsed to allow coding synchronization to be restored. This will. obviously imply that the transfer is accompanied by a brief period during which the security of the information transmitted is compromised.

Consequently, what is needed is a coding technique that overcomes the aforementioned problems inherent in coding techniques. That is, a coding technique that can continue to function in coded mode during transmission without loss of information. A coding technique that does not degrade voice quality is required. In addition, a coding technique is required which can be performed at a lower cost and smaller size than conventional coding techniques allow.

United States Patent No. No. 5,081,679 includes a description of a coding and decoding system in a dual radio cellular system in which the coded call can be switched from one cell to another.

Summary of the Invention

The present invention consists of a method and apparatus for maintaining synchronized encoding and decoding of information without interruption during a transfer as set forth in Claims 1 and 5.

Brief Description of the Drawings

Fig. 1 is a block diagram of a wire communication system according to a preferred embodiment of the present invention.

Fig. 2 is a diagram illustrating the contents of a multiple access time division and a time division double access (MDAM / DDT) elaborated according to the Digital European Cordless Telecommunications ( DECT) as used according to the preferred embodiment of the present invention.

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Fig. 3 is a block diagram of a fixed communications unit (UCF) according to the preferred embodiment of the present invention.

Fig. 4 is a block diagram of a portable communications unit (CPU) according to the preferred embodiment of the present invention.

Fig. 5 is a block diagram of a coding synchronization counter (CSC) according to the preferred embodiment of the present invention.

Fig. 6 is a flow chart of a method for synchronized encoding and decoding information generating a unique coding sequence according to the preferred embodiment of the present invention.

Fig. 7 is a flow chart of a method of maintaining a synchronized encoding and decoding of uninterrupted information during a transfer in accordance with the preferred embodiment of the present invention.

Description of a Preferred Embodiment

Referring to Fig. 1, a preferred embodiment of a wireless communication system according to the present invention comprises a plurality of fixed communication units (UCFs) 102 which provide radio coverage in a plurality of wireless coverage areas. 108, 110, 112. The UCFs are connected to a Public Telephone Network (RTP) 114 via a plurality of telephone lines 116. Those skilled in the art will recognize that the wireless communication system according to the present invention may also be used with systems other than RTP, for example with a private switch (PBX). The system further comprises at least one portable communication unit (CPU) 120 having transfer and transmit and receive capabilities in a time division and dual time division digital access (MDAM / DDT) format. The system further comprises at least one corded telephone apparatus 124 for sending and receiving calls from a CPU 120. A CPU 120 may

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still communicate with another CPU 120 through one or more UCFs 102.

Further enabling the wireless communication system according to the present invention is the use of a standard protocol for communications between the plurality of UCFs and at least one CPU. The standard protocol defines messages and procedures for requesting and establishing wireless communications connections, for transmitting and receiving signaling data, for transmitting and receiving user communications, and for defining the MDAM / DDT format used. An example of this standard protocol is the Digital European Cordless Telecommunications (DECT) standard. The DECT standard is defined in European Telecommunications Standard document prETS 300 175 entitled “Digital European Cordless Telecommunications Common Interface”, dated August 1991, and produced by the European Telecommunications Standards Institute, where the applicable provisions two, three, five and seven of said document are hereby incorporated by reference.

Referring to Fig. 2, an MDAM / DDT 201 made in accordance with the DECT standard as used in accordance with the preferred embodiment of the present invention comprises twelve time slots 202 for UCF transmission and twelve time slots 203. for CPU transmission. Time slots 202, 203 are paired based on position for transmitting and receiving information. For example, a UCF 102 (Fig. 1) to transmit in time slot 202 labeled "0" would receive time slot 203 also labeled "0". Each time slot 202, 203 comprises a synchronization portion 204 comprising a synchronization marker for synchronizing a connected CPU 120 (Fig. 1) and a UCF 102, and a data portion 205. Data part 205 comprises a control part 206 for passing control information, for example, time and space IDs and other messages between the connected CPU 120 and UCF 102, and a data part 208 designed to carry user data, for example speech.

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Synchronization part 204 and control part 206 are used to synchronize the encoding and decoding of information carried on user data part 208 as well as any user signaling that is carried on control part 206 according to the present invention. . By synchronizing the encoding and decoding processes achieved by using existing portions 204, 206 of the DECT time slot 202, 203 it is not necessary to steal bits from the user data portion 208. Thus, the coding and decoding technique according to the present invention does not degrade voice quality, as with conventional coding and decoding techniques which use bit theft for synchronization. Additionally, by synchronizing encoding and decoding circuits via synchronization signals already available on UCF 102 and CPU 120 (Fig. 1) fewer parts are required for synchronization, thus reducing the cost and size of CPU 120 and of UCF 102.

During operation, the timing synchronization portions of the MDAM / DDT circuits within UCF 102 and CPU 120 (described below) allow information to be encoded and decoded during transmission of user data portions 208 and during transmission of control portion 206 when control portion 206 comprises user signaling information. MDAM / DDT circuits disable encoding and decoding during all other parts of the transmission.

Referring to Fig. 3, a preferred embodiment of UCF 102 (Fig. 1) according to the present invention comprises a radio frequency (RF) transmitter and receiver 302 for transmitting and receiving radio signals comprising transmitted digital information. and received in an MDAM / DDT format. The RF transmitter is connected to a microprocessor 304 for controlling transmitter and receiver 302 through an input 306. Microprocessor 304 is connected by input 306 to a momentum system synchronization circuit 307 to maintain momentum synchronization between all system UCFs. The current sync circuit 307 receives a sync signal from the main system on the

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If the connection to RTP 114 (Fig. 1) is digital, the main synchronization signal may, for example, be derived from the synchronization markers contained therein, after the differential offset adjustments have been made. RTP 114 and the plurality of UCFs 102 (Fig. 1).

The RF transmitter and receiver 302 is also connected to an MDAM / DDT circuit 308 to link RF transmitter and receiver 302 via two module adder 309 to a plurality of CODECs 310 for making audio to digital conversions and from digital to audio signals transmitted and received respectively by the UCF 102. The plurality of CODECs 310 are connected to a plurality of telephone connections 312 for connecting a plurality of telephone lines 116 to CODECs 310. The two module adder 309 is connected to a coding synchronization counter (CSC) 314 operated by an increment clock generator 315, operating at the serial bit rate of the MDAM / DDT circuit 308 and CODECs 310 and being synchronized by MDAM / DDT circuit 308 relative to the main synchronization signal to provide encoding and decoding of information passing between CODECs 310 and circuit

MDAM / DDT 308 according to the present invention.

The MDAM / DDT circuit 308, CODECs 310, the clock increment generator 315, the CSC 314, and telephone connections 312 are also all connected to input 306 to allow control by microprocessor 304. A memory 316 is also connected to the microprocessor for storing program control software and for storing values ​​in a plurality of memory locations 320 reserved for CSC content and a corresponding plurality of memory locations 318 reserved at the times that transfers take place. be completed, each corresponding to the two corresponding pluralities of memory locations 320, 318 being associated with a corresponding plurality of associated receive and transmit MDAM / DDT time slots 202, 203 (Fig. 2) that are used by UCF 102.

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When one of the plurality of MDAM / DDT receive and transmit time slots 202, 203 (Fig. 2) is actively carrying user information, the value of the CSC content at the end of each MDAM / DDT time slot DDT

202, 203 is stored at memory location 320 which is reserved for CSC content corresponding to that associated with the plurality of paired MDAM / DDT receive and transmit time slots 202, 203, while corresponding memory location 318 that is reserved for the end of transmission time is not used. The value stored at the memory location 320 reserved for the CSC content is then used to reactivate the CSC 314 at the beginning of the corresponding time slot between the MDAM / DDT receive and transmit time slots 202, 203. Using memory 316 as just described with the present invention, a single CSC provides information encoding and decoding of all MDAM / DDT 202, 203 time slots used throughout the UCF, thereby reducing the cost and the size of the UCF.

When a pair of transmit and receive time slots are not actually carrying information but are instead waiting for either a start or end connection for a pending transmission, memory location 320 reserved for CSC content corresponding to the timeout pair is used to store a start or resume value sent by a CPU that initiates the connection or the pending transmission, respectively. When there is a pending transmission directed to an MDAM / DDT time slot pair, the memory location 318 destined for the transmission time corresponding to the MDAM / DDT time slot pair is used to control the timing of the pending transmission accordingly. with the present invention.

Referring to Fig. 4, CPU 120 (Fig. 1) according to the preferred embodiment of the present invention comprises an RF transmitter and receiver 402 for transmitting and receiving audio signals comprising digital information transmitted and received in a format. MDAM / DDT. The RF transmitter and receiver are connected to a microprocessor 404 to control the RF transmitter and receiver 402 via an input 406. The RF transmitter and receiver 402 is also connected to an MDAM / DDT circuit 408 to connect a transmitter and receiver 402 via the two module adder 409 to a CODEC 410 for audio to digital and digital to audio conversions. audio signals transmitted and received respectively by CPU 120. The two module adder 409 is connected to a CSC 414 operated by an increment clock generator 415 operating at the serial bit rate of the MDAM / DDT 408 and CODEC 410 circuitry to provide encoding and decoding of the passing information. between CODEC 410 and the MDAM / DDT 408 circuit according to the present invention. By using the unique CSC 414 for MDAM / DDT information encoding and decoding, CPU size and cost are reduced when compared to conventional encoding and decoding techniques using separate transmission rail devices and reception.

The clock increment generator 415 is synchronized by the MDAM / DDT circuit 408 with a momentum marker received over a wireless connection from UCF 102. The marker being synchronized within UCF 102 by the main signal synchronization system in the terminal 305 (Fig. 3). CODEC 410 is connected to audio connections 412 to send and receive audio signals from and intended for a user of CPU 120. The MDAM / DDT 408 circuit, the CODEC 410, the clock boost generator 415, the CSC 414, and the audio connections 412 are all also connected to input 406 to allow control by microprocessor 404. It is also connected to the microprocessor 404 to store program control computer programs and to store a pair of CSC content values ​​419, 420 and time to finish transmission, respectively. The values ​​419, 420 are determined by the microprocessor and are subsequently transmitted from the CPU to a UCF for the initiation of connection and for transmission transmission according to the present invention. Also connected to the microprocessor 404 is a display 417 for displaying the information sent by the microprocessor 404 and a keyboard 416 for receiving reception control data from the user.

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Referring to Fig. 5, the preferred embodiment of CSC 314,414 according to the present invention comprises an alternator 502 having a parallel data input 504 which is activated by a parallel activator 506 for charging a start value or continuation inside the alternator 502 from microprocessor 304, 404 (Figs. 3, 4). Alternator 502 has a clock input 508 driven by the increment clock generator 315, 415 (Figs. 3, 4) whenever the microprocessor 304,404 activates a clock activator 510 for enabling and disabling the encoding and decoding of information passing between CODECs 310, 410 and the MDAM / DDT circuit 308, 408 (Figs. 3 4) according to the present invention. The alternator is used as a linear power alternator which features recharging of its last output 512 and intermediate outputs 518, 514 back to series data input 522 via module two adders 516, 520. Connected in this way, the The alternator generates at the last output 512 a predefined sequence of bits for synchronizing the encoding and decoding of the information.

More preferably, for added security, the serial sequence of the bits at the last output 512 is sent through an algorithm generating device 524 which is triggered by a variable key provided by microprocessor 304,404 (Figs.

4) at a KV input 528 to produce a secure coding sequence at a final output terminal 526. An example of such a device is TRN4836A manufactured by Motorola, Inc. of Schaumburg, Illinois. The serial signal at the output terminal 526 is added to the two module adder 309, 409 (Figs. 3, 4) to encode and decode the information transmitted and received by UCF 102 and CPU 120.

Even more preferably, in UCF 102 a separate and unique variable key can be used for each MDAM / DDT time slot pair 202, 203 (Fig. 2). The separate and unique variable key for each MDAM / DDT time slot pair 202, 203 would be stored in memory 316 (Fig. 3) and transferred to input KV 528 by microprocessor 304 (Fig. 3) at the beginning of each MDAM / DDT time slot 202, 203 associated. Using a separate and unique variable key as described for each time pair provides a degree

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security coding security while maintaining the possibility of using a single CSC comprising generating a one-key current algorithm device 524 for all MDAM / DDT time slots 202, 203 in the UCF 102.

Referring to Fig. 6, a method for performing synchronized encoding and decoding of information by generating a unique encoding sequence according to the preferred embodiment of the present invention comprises receiving 602 on a UCF 102 (Fig. 1) information of a CPU 120 (Fig. 1) while establishing a connection between CPU 120 and UCF 102. The registration information comprises a coded personal identification number (CPIN). In response to receiving registration information, UCF 102 decodes 604 a corresponding personal identification number (PIN) using a predetermined algorithm and stores the PIN in a memory location 320 reserved for CSC content (Fig. 3) corresponding to the time slot. used by UCF 102 for the connection. As the PIN is also stored in CPU 120, microprocessors 304, 404 (Figs. 3, 4) on both UCF 102 and CPU 120 will load 606 identical PIN values ​​into the respective CSCs 314,414 (Figs. 3, 4) at the appropriate time as described below.

When establishing a connection proceeds to a point where the connection is ready for consumer use, microprocessors 304, 404 carry 608 PIN in CSCs 314, 414 in UCF 102 and CPU 120 (Fig. 1), respectively, and simultaneously activate the respective clock trigger 510 (Fig. 5) for the CSCs 314, 414 at the next sync marker in the synchronization portion 204 (Fig. 2) of the signal transmitted by the UCF 102 in the UCF transmission space 202 (Fig. 2) which is being used. Those skilled in the art will recognize that the synchronization portion 204 of the signal transmitted by CPU 120 in the transmission time slot UCP 203 (Fig. 2) could alternatively be used to activate the respective incremental clock generators 315,415 provided that same signal is used on both UCF 102 and CPU 120 to activate clock activator 510 on CSCs 314,414 at the same time.

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In the course of the established connection, the clock increment generators 315,415 of the CSCs 314,414 are synchronized 609 with each other via the MDAM / DDT circuits 308, 408 (Figs. 3, 4), respectively, in response to the repetitive sync marker on synchronization portion 204 (Fig. 2) of the signal transmitted by UCF 102 (Fig. 1).

As is well known to those skilled in the art, if a first serial bit stream is added to a first module two adder (XOR logic gate) with a second pseudo random serial bit stream synchronized with, and having the same speed of series bit, a new (coded) series bit stream is then output to the output of module adder two. If the resulting new (encoded) bit stream is again added to a second module two adder with a third pseudo random series bit stream synchronized with, and identical to, the second pseudo random bit stream, then a current Serial bit stream identical to the first serial bit stream is output to the second module two adder output. Thus, the present invention provides an apparatus and method for performing synchronized encoding and decoding of information by generating a unique coding sequence for controlling synchronized encoding and decoding taking place at UCF 102 and CPU 120.

Referring to Fig. 7, a method for maintaining synchronized encoding and decoding of information without interrupting the transfer according to the preferred embodiment of the present invention comprises a CPU 120 (Fig. 1) connected to a first UCF 120 ( Fig. 1) determining 701 a need for a transfer to a second UCF 120 and then selecting the moment in time for the transmission to complete, the momentum being simultaneous with a future sync marker at synchronization part 204 (Fig. 2) of the signal transmitted by the first UCF 102 at the transmission time UCF 202 (Fig. 2) used to connect with the first UCF 102. This follows in the same step 701 with the CPU 120 calculating a continuation value for the transmission, ie an expected value

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on CSC 414 (Fig. 4) of CPU 120 at the selected time for transmission to complete.

Thereafter, CPU 120 702 establishes a second wireless connection with second UCF 102 and transmits the continuation value and the selected time for transmission to complete. As the time for transmission to complete is simultaneous with a future sync marker on synchronization part 204 (Fig. 2) of the signal transmitted by the first UCF 102 in the transmission UCF space 202, and since all system UCFs 102 are synchronized by the main system synchronization signal at terminal 305 (Fig. 3) in UCF 102, the second UCF 102 may determine the timing of the transmission with great accuracy.

The second UCF 102 (Fig. 1) stores 706 the continuation value and the time at which transmission is completed at memory location 320 for CSC content (Fig. 3) and at memory location 318 for the time of transmission. completes the transmission (Fig. 3), respectively, with memory locations 320, 318 being those associated with the MDAM / DDT time slot used by UCF 102 for the second wireless connection.

When the selected time has come for the transfer to complete, microprocessor 304 (Fig. 3) accesses its memory 316 to collect the continuation value, loads the continuation value 708 into CSC 314 (Fig. 3) and activates the increment clock for CSC 314, thus starting CSC 314 of the second UCF 102 at the value that CSC 414 (Fig. 4) of CPU 120 reached simultaneously.

During the second wireless connection, the incremental clock generators 315, 415 of the CSCs 314, 414 in the second UCF 102 and CPU 120, respectively, are synchronized 709 with each other via MDAM / DDT circuits 308, 408 (Figs. 3, 4), respectively, in response to the repetitive sync marker in the synchronization part 204 (Fig. 2) of the signal transmitted by the second UCF 102 (Fig. 1).

Thus, the present invention comprises a method and apparatus for performing synchronized encoding and decoding of information generating a sequence

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A single encoding device for controlling synchronized encoding and decoding taking place at UCF 102 and CPU 120. Additionally, the present invention comprises a method and apparatus for keeping synchronized encoding and decoding of information without interruption during a transfer. . Accordingly, the present invention provides a coding technique that overcomes the aforementioned problems arising from conventional coding techniques by providing: (a) a coding technique that may continue to operate in coded mode during a lossless transfer of information, (b) a non-bit-stealing coding technique that degrades voice quality, and (c) a technique coding that can be performed at a lower cost and smaller than a conventional coding system.