Architecture for a universal serial bus-based pc flash disk

(54) Title: ARCHITECTURE FOR A UNIVERSAL SERIES BUS-BASED PERSONAL LIGHTNING DISC (57) Summary:

EP 1 548 604 / EN

RESUME

Architecture for a universal series bus-based personal lightning disk

A storage unit consisting of a flash array (58) and a universal serial bus (USB) controller (56) are implemented to be compatible with the USB specification. Unit 46 includes memory modules 58 which can accept write commands and read commands from a main platform 44 which can be deleted and are not volatile, referred to as flash modules. ) (58). 0 USB / lightning (flash) driver (56) is configured to ensure USB functionality and compatibility in conjunction with common lightning operations such as programming, reading and deleting lightning modules (58).

Fig. 5 Main platform computer system with a USB flash memory device

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DESCRIPTION

Architecture for a universal series bus-based personal lightning disk

FIELD AND BACKGROUND OF THE INVENTION The present invention relates to semiconductor memory devices and, in particular, disposable and programmable nonvolatile memory modules which are connected to a main platform via the USB PC bus.

Disposable and programmable non-volatile memory modules, hereinafter referred to as flash memories or flash devices, are known in the art for storing information. Lightning devices include electronically programmable, erasable read-only (EEPROM) memories consisting of flash-type floating-gate transistors and are non-volatile memories with similar functionality and performance to EPROM memories, with additional functionality that allows the operation of a programmable circuit to clear pages of memory. An example of one embodiment of such a lightning device is given in US Patent No. 5,799,168.

This document introduces a lightning flash memory controller that reports the number of lightning flash integrated circuit chips present. By using the ID read mode inherent in lightning chip inserts (where reading any address causes one of several fixed codes identifying the manufacturer and type of chip to be returned), the standard controller identifies dynamically grouping elements you are managing by issuing read ID commands for parent addresses, in order to identify the presence of integrated circuit inserts at that position and thereby automatically detect the number of integrated circuit inserts and inserts.

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Lightning devices have the advantage that they are relatively inexpensive and require relatively little power compared to traditional magnetic storage disks. However, on a lightning device, it is not practical to rewrite a previously written memory area without previously deleting a page from the area. This limitation of lightning devices results in them being incompatible with typical existing operating system programs, since data cannot be written to a memory area on the lightning device in which data was previously written unless unless the area was first cleared. 0 US 5,404,485 discloses a flash memory controller that provides a completely rewritable virtual address space for the flash memory to emulate a random access memory in which the controller updates an address translation table.

US 5,404,485 discloses a flash memory controller which provides a fully rewritable virtual address space so that the flash memory emulates a random access memory where the controller updates an address translation table.

At present, these flash memory devices have a second limitation, which is that they must be statically connected to the main platform or dynamically switched on and off using a PCMCIA interface. Both implementations have drawbacks, including usability difficulties and high cost.

A more useful embodiment should follow the USB standard as described in USB Specification Version 1.1. The USB standard ensures a lower form factor and greater ease of use for the end user, while reducing the cost of implementation. This standard is specifically intended to be a large industrial application standard promoted by companies such as Compaq Computer Corporation, Microsoft, IBM and Intel to serve as an extension to the single-use PC architecture.

ΕΡ 1,548,604 / ΡΤ focus on integrating computer telephony (CTI), consumer telephony and productivity applications.

The Universal Serial Bus Mass Storage Class Specification OverView VI.0 of October 22, 1998 suggests the use of USB for mass storage devices and involves existing storage protocols for mass storage devices with a USB package. One of the protocols considered in this document is Reduced Block Commands (RCB) which is typically used for lightning devices.

Criteria that have been applied to define the architecture for the USB standard include ease of scalability of PC (personal computer) peripherals, low cost, transfer rate compatibility up to 12 Mb / s and full compatibility for real-time data, voice. , compressed audio and video. This standard also guarantees protocol flexibility for mixed mode isochronous data transfer and asynchronous messaging, integration into useful device technology and ensures a standard interface for quick integration into any given core product. In addition, the USB standard represents a unique model for connection and wiring plugs, so that all details of electrical functions, including bus terminals, are isolated from the end user. Peripheral devices are typically self-identifying and support automatic mapping of functions with one unit. In addition, the standard allows all peripheral devices to be dynamically connected and reconfigured.

A system built to the USB standard is described by three defined and separate areas: USB interconnection, USB devices and the main USB platform. USB interconnection is the way USB devices are connected and communicate with the main platform. Associated functions and components include the bus topology, which is the connection model between USB devices and the main platform.

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The USB physical interconnect has a star wired topology. A nucleus is in the center of each star. Each wire segment is a point-to-point link between the main platform and a core or function or a core attached to another core or function.

In terms of a stacking capacity, the USB tasks that are performed at each layer in the system include a data flow model and planning. A data flow model is the manner in which data travels in the system over USB between data producers and data consumers. Planning determines access to the interconnection, which is shared. This planning allows isochronous data transfers to be supported and eliminates arbitrage overhead.

USB itself is a selection bus. The master controller on the master platform initiates all data transfers. All bus transactions involve the transmission of up to three packets. Each transaction begins when the master controller, on a planned basis, sends a USB packet, which describes the type and direction of the transaction, the USB device address, and the endpoint number. This package is referred to as the core package. 0 USB device, where the packet is directed, is automatically selected by decoding the appropriate address fields transferred either

In a given transaction, the data is from the main platform to one of a device to the main platform. The direction of data transfer is specified in the core package. The transaction source then sends a data packet or indicates that the source has no data to transfer. The destination generally responds with a connection establishment protocol packet indicating whether the transfer was successful.

A USB data transfer model between a source and destination on the main platform and an endpoint on a device is referred to as a channel. There are two types of channels: sequence and message. Sequence data has no USB-defined structure, whereas message data has. In addition, channels have bandwidth associations.

Data, type of transfer service and endpoint characteristics such as directionality and buffer dimensions. Most channels become active when a USB device is configured. A message channel, the default control channel, exists whenever a device is powered to ensure access to configuration, status, and control information for the device.

Transaction planning for the USB standard allows flow control for some sequence channels. At the physical level, this avoids situations where buffers experience underloading or overloading by using NAK connection protocol to model data throughput. With the NAK connection protocol, a transaction is retried when bus time is available. 0 Flow control mechanism allows the construction of flexible schedules that accommodate concurrent service from a heterogeneous mix of sequence channels. Thus, multiple sequence channels can be handled at different intervals with packets of different sizes.

The USB standard, as described, has three main types of packets, including core packets, data packets, and connection protocol packets. An example of each packet type is shown in Figs. 1 to 3 of the prior art. Prior art Fig. 4 shows an exemplary USB abstract device.

A core packet 10, as shown in Fig. 1 of the prior art, has a PID (packet identification) field 12 that specifies one of three packet types: IN, OUT, or SETUP. If field PID 12 specifies the IN packet type, the data transaction is defined from a function to the main platform. If field PID 12 specifies the OUT or SETUP packet type, the data transaction is defined from the main platform to a function.

An ADDR 14 field specifies the address, while an ENDP 16 field specifies the endpoint for the packet.

Witness 10. For OUT and SETUP transactions, where PID field 12 specifies that witness packet 10 is an OUT packet type or a SETUP packet type, field ADDR 14 and ENDP field 16 uniquely identifies the endpoint for receiving the subsequent data packet, shown in Fig. 2, which follows after the core packet 10. For IN transactions, where PID field 12 specifies that core packet 10 is a type of IN packet, field ADDR 14 and field ENDP 16 uniquely identify the endpoint that transmits a data packet. A CRC5 field 18 contains the checksum to determine which core packet 10 was received without corruption. Only the main platform can issue core packets 10 such that core packets 10 provide control over the transmission of subsequent data packets.

As shown in prior art Fig. 2, a prior art USB data packet 20 also performs a PID (packet identification) field 22 for data packet type identification. Data packet 20 also executes a data field 24 to contain option data and a CRC field 26 to contain the checksum as described above.

Prior art Fig. 3 shows a prior art USB connection protocol packet 28 which executes only one PID (packet identification) field 30. Connection protocol packets 28 are used to report the state of a data transaction and may return values ​​that indicate successful data reception, command acceptance or rejection, flow control, and suspend conditions. Only transaction types that support flow control can return connection protocol packets 28. Connection protocol packets 28 are always returned at the connection phase of a transaction and can be returned instead of the connection packets. data 20 in the data phase of a transaction.

These three different types of packets are exchanged during various phases of the transaction including a device.

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USB A schematic block diagram of the functional blocks in a typical USB device 32 is shown in Fig. 4 for a prior art USB abstract device. The USB device 32 typically includes a USB 34 electrical interface featuring a cable and plug which is a physical interface for receiving and transmitting electrical signals that are compatible with the USB specification as described above. The signals are then passed to a logic interface 36, which includes one or more buffers, the device address decoder for decoding the source device address for the signals, and a SYNC field synchronizer for signal synchronization. Information and structures required for managing the USB 32 abstract device as a USB device are stored in a USB class enumeration and control engine 38. A function and device motor 40, also called the application, controls and manages the specific functions and properties of the USB 32 abstract device. In addition, the function and device motor 40 also consumes and produces most data on the USB bus. .

The USB specification, however, does not define the relationship between different entities in the UBS 32 abstract device. In contrast, the USB specification only describes the requirements for packets and for the electrical and physical connection between the USB 32 abstract device and the bus. Accordingly, the connections and relationships shown in Fig. 4 of the prior art are merely an example of an embodiment that meets the requirements of the USB specification. Thus, any specific device to meet the USB specification must have a specifically defined and described architecture.

Unfortunately, there is no such architecture for a flash memory device, which contains one or more flash memory modules, which enable the flash memory device to connect to a bus, defined according to the USB specification, and thus being part of a USB system on a main platform. For example, US Patent No. 5,799,168 does not teach or suggest such an embodiment for the lightning device. As noted earlier, such an architecture would be

It is particularly useful for a number of reasons, including low cost, ease of use and transparency for the end user.

There is thus a need and it would be useful to have an architecture for defining and describing a flash memory device that was compatible with a USB system and that complied with the USB specification, so that the flash memory device could fit on a bus with USB setting and communicate with the main platform through this bus.

Brief Description of Drawings

Fig. 1 is a schematic block diagram of a prior art USB core packet structure;

Fig. 2 is a schematic block diagram of a prior art USB data packet structure.

Fig. 3 is a schematic block diagram of a prior art USB connection protocol data packet structure;

<td>Fig. 4</td><td>is</td><td>a diagram</td><td>in</td><td>schematic blocks</td><td>on one</td>

<td>USB device</td><td>gives</td><td colspan="2">prior art</td><td>exemplary;</td><td></td>

<td>Fig. 5</td><td>is</td><td>a diagram</td><td>in</td><td>schematic blocks</td><td>on one</td>

system with a flash (USB) device functionality in accordance with the present invention;

Fig. 6 is a schematic block diagram of the USB flash disk;

Fig. 7 is a schematic block diagram of a flash identification request packet (flash);

Fig. 8 is a schematic block diagram of a lightning identification state packet;

Fig. 9 is a schematic block diagram of a flash write request packet;

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<td>The package</td><td>Fig. 10 of state</td><td>is a lightning block writing diagram;</td><td>schematic</td><td>in</td><td>one</td>

<td>The package</td><td>Order Fig. 11</td><td>is a lightning block reading diagram;</td><td>schematic</td><td>in</td><td>one</td>

<td>The package</td><td>Fig. 12 of state</td><td>is a lightning block reading diagram;</td><td>schematic</td><td>in</td><td>one</td>

<td>The package</td><td>Fig. 13 of request</td><td colspan="2">is a lightning-eliminating schematic block diagram; and</td><td>in</td><td>one</td>

<td>The package</td><td>Fig. 14 of state</td><td>It is a block diagram of lightning eliminate.</td><td>schematic</td><td>in</td><td>one</td>

Summary of the Invention

The present invention is a flash memory device, which contains one or more flash modules, where flash memory is mapped to the address space of an ASIC or controller that has a USB-defined electrical interface and a logic interface with USB setting. This / ASIC controller (hereinafter referred to as the controller) supports USB functionality according to the USB standard, thus supporting USB bus enumeration as well as receiving and transmitting data on USB channels to and from USB endpoints. This controller also supports the functionality and control of the flash memory device as well as command controller processing and data packets. 0 The master controller uses one of several possible protocols, both standard and proprietary, to signal the next command to be performed for the USB flash controller. Thus, the entire device acts as a dynamically removable, non-volatile storage device for the main platform.

In accordance with the present invention, there is provided a USB flash memory device and method as defined in the attached independent claims.

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Hereinafter, the term computer includes, but is not limited to, personal computers (PCs) with an operating system such as DOS, Windows, OS / 2, or Linux; Macintosh computers; JAVA-OS computers as an operating system and graphical workstations such as Sun Microsystems ™ and Silicon Graphics ™ computers and other computers with some version of the UNIX operating system such as AIX ™ or SOLARIS ™ from Sun Microsystems ™; or any other known and available operating system, including operating systems such as Windows CE ™ for embedded systems, which include mobile phones, handheld computing devices, and pocket computing devices, and any other computing device that may be connected to a network. Hereinafter the term Windows ™ includes but is not limited to Windows95 ™, Windows3.x ™ where x is an integer such as 1, WindowsNT ™, Windows98 ™, Windows CE ™ and any updated versions of these operating systems from Microsoft Inc. (Seattle, Washington, USA).

Detailed Description of the Invention

The present invention is of a flash memory device containing one or more flash modules, where flash memory is mapped to the address space of an ASIC or controller which has a USB-defined electrical interface and a Logic interface with USB setting. This ASIC controller (hereinafter referred to as the controller) supports USB functionality according to the USB standard, thus supporting USB bus enumeration as well as receiving and transmitting data on the USB channels to and from USB endpoints. This controller also supports the functionality and control of the flash memory device as well as the processing of data packet commands from the master controller. The master controller uses one of several possible protocols, both standard and proprietary, to signal the next command to be performed for the USB flash controller. Thus, the entire device acts as a dynamically removable, non-volatile storage device for the main platform.

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Although the invention is susceptible of various modifications and can be implemented by using many alternative forms, the embodiment is shown by way of example in the drawings and will be described in detail on the following pages. It should be understood that one of ordinary skill in the art will appreciate that the present invention could be implemented in various other ways. The intention is to cover all modifications and alternatives that fit the spirit of the present invention.

The principles and operation of a USB flash system and device according to the present invention may be better understood with reference to the accompanying drawings and description, it should be understood that these drawings are provided for illustration purposes only and are not intended to be limiting.

Referring now to the drawings, Fig. 5 is a schematic block diagram of the main components of a flash memory system and device in accordance with the present invention. A flash memory system 42 includes a main platform 44 as shown. The main platform 44 operates the USB flash device 46 as a nonvolatile storage space.

The main platform 44 is connected to the USB lightning device 46 according to the present invention via a USB 48 cable. The main platform 44 connects to the USB 48 cable through a USB 50 host plug, while the USB lightning device 46 connects to the USB cable 48 via a USB lightning device plug 52. The main platform 44 configures a USB 54 main controller for controlling and managing all USB transfers on the USB bus.

The USB lightning device 46 configures a USB lightning device controller 56 to control the other USB lightning device components 46 and to provide an interface for the USB lightning device 46 to the USB bus, to the USB lightning device plug 52 and at least a flash memory module 58. The flash memory module 58 is preferably a

Grouping of flash memory modules 58 in which data is stored.

and mode 46. Although you configure that

USB flash device only and unintentionally

Each time the USB flash device 46 connects to the main platform 44, a normal USB enumeration process is performed. In this process the main platform 44 configures a USB flash device 46 communicating with the USB flash device there are many different methods for

46, for reasons of clarification, the present invention is explained in more detail below with respect to a method whose main platform 44 issues commands and requests to the USB flash device 46 through an endpoint. Main platform 44 interrogates USB flash device 46 through another endpoint about state changes and receives related packets if any packets are waiting to be received.

The main platform 44 requests services from the USB lightning device 46 by sending request packets to the USB 54 main controller. The USB 54 main controller transmits packets on the USB 48 cable. These requests are received by the USB lightning device controller 56 when the USB flash device 46 is the device at the endpoint of the request. 0 USB flash device driver 56 then performs various operations such as reading, writing, or deleting data to or from flash memory module (s) 58 or supports basic USB functionality such as device enumeration and configuration. 0 USB flash device driver 56 controls flash memory module (s) 58 by using a control line 60 to control power to flash memory module (s) 58 and also by various other signals such as enabling the insert integrated circuit and read and write signals, for example. Lightning memory modules 58 are also connected to the USB lightning device controller 56 via an address / data bus 62. Address / data bus 62 transfers commands to perform read, write or delete commands on flash memory module (s) 58, as well as the addresses and data for them

54 1 548 604 / ΡΤ commands as defined by the manufacturer of the flash memory module (s) 58.

In order for the USB lightning device 46 to notify the main platform 44 of the result and status for different operations requested by the main platform 44, the USB lightning device 46 transmits state packets using the state endpoint. According to this procedure, the main platform 44 checks (interrogates) for state packets and the USB flash device 46 returns an empty packet if there are no packets for new status messages or, alternatively, returns the state pack itself.

A more detailed structure of the functional components of the USB lightning device 46 is shown in Fig. 6. The USB lightning device 46 includes the physical and electrical interface defined for the USB standard, shown here as a USB lightning device plug 52 and a plug interface. 64. USB Lightning Device Plug 52 receives electrical signals from the USB 48 cable that carries electrical signals from the main controller (not shown). These signals are then passed through the plug interface 64. Each millisecond, a USB frame is carried on the USB-defined bus, such that packets could be sent to the USB flash device 46.

The plug interface 64 then receives these packets via a first interface component, which is a combined physical and logical interface 66. A functional interface 68 is specifically adapted for receiving core packets as defined in the USB specification and as described above in relation to Fig. 1. These core packets relate only to particular functional aspects of the USB flash device 46 which are required by the USB standard and have no relation to the particular application of the USB flash device 46 as a flash disk according to the present invention. These core packets and their respective returned data packets enable USB main controller 54 (not shown) and main platform 44 (not shown) to identify USB flash device 46 and assign

Features for the USB 46 lightning device on the USB-defined bus. Thus, functional interface 68 only supports the USB functionality required for identification and registration of the USB flash device 46 on the USB bus.

USB flash device 46 also embodies an application package extraction device 70 which extracts application commands and data from USB application packages, such that application package extraction device 70 supports only application-related packages. Subsequently, any requests to USB flash device 46 by main platform 44 (not shown), in the form of read, write, identify and delete commands, are interpreted by an application command interpreter 72. For any commands involving data or an address, such as read, write, and delete commands, an address resolution module 74 converts the address from the logical address space to the physical address space. Main platform 44 (not shown) refers to a linear address space of logical addresses, while the USB flash device 46 contains at least one and preferably a plurality of flash modules 58, each of which which has a physical address space. Thus, a conversion must be performed between the main platform logical address space 4 (not shown) and the physical address space or spaces of the USB flash device 46. There are many embodiments of such a conversion that are suitable for the present invention. An example of a suitable embodiment of an address translation method is described in relation to US Patent No. 5,404,485, which teaches a method for managing a flash memory like a flash disk and which is suitable for operating with the present invention. .

A data manipulation device 76 manages data aspects of any commands received and transmits the data via the functional interface 68 to and from lightning module (s) 58. Optionally and preferably, the data manipulation device 76 embodies any of the error detection and correction methods. The device of

54 1,548,604 / ΡΤ application command interpretation 72, data manipulation device 76, and address resolution module 74 all operate with an underlying memory technology unit (MTD) 78 for writing, reading, or deleting in a module particular lightning strike 58 and the desired address on that lightning strike module 58.

The main platform 44 checks status changes on USB flash device 46 and reads status packages from USB flash device 46 when a new status pack is available. Using these status packets, the USB flash device 46 can transmit to the main platform 44 the results of different commands issued by the main platform 44 in its requests (not shown). For example, the read command state packet contains one of the available status words such as success, error, or invalid address, which enables the main platform 44 to determine the read command result (not shown). Similarly, the delete status package contains a status word that indicates the completion of the delete process. A write state packet is used by the USB flash device 46 to notify main platform 44 of the result of the write command, for example if the command was successful or in error, and whether the USB flash device 46 is ready for requests to write. additional writing from the main platform 44.

A memory technology unit or MTD 78 typically contains read, write, and delete routines in the lightning memory device controlled by the controller operating the MTD 78. In addition, MTD 78 optionally contains an identification routine for recognizing the appropriate type of lightning memory device to which MTD 78 has been adapted, so that the controller can determine which MTD to activate after interaction with a particular grouping of flash memory devices. In addition, an identification routine should be able to detect the size of the flash memory array, including the number of flash memory devices in the array, and various features of the flash array geometry, such as

54 1 548 604 / ΡΤ interleaved and bus width. This information later enables the main platform 44 for determining the address space and the size of the storage media.

US Patent No. 5,799,168 discloses an example of such an MTD for a lightning device. Using the protocol and architecture described above, the main platform 44 may optionally deploy any application that can be deployed with any 1/0 mapped normal memory or lightning mapped memory device. For example, main platform 44 may provide a standard block device interface for each application, such as a magnetic storage medium hard disk drive, as disclosed in US Patent No. 5,404,485 described above.

As an example of a preferred embodiment of the present invention, operation of a main system connected to a USB flash device in accordance with the present invention is described with respect to the identification, programming, reading and deletion process in the flash device. For illustration purposes only and without limitation by any means, the exemplary USB flash device has a grouping of two flash memory modules, each of which is 64 Mbit in size. The address translation table is on the lightning device for the platform to operate with logical addresses. All return codes and commands between the lightning device and the main platform are carried in the USB data packets and are transferred through the USB data channels. The exact structure of packets, channels and timings are described in the USB specification.

The operation of the exemplary system and device according to the present invention is as follows. When the USB lightning device is first connected to the main platform, the USB main controller assigns an address to the USB lightning device on the USB bus and also assigns features as described in the USB specification. The USB flash device actually asks the main platform to

Allocate these resources and must inform the main platform how many of these resources are required. Thus, the USB flash disk can optionally support lower device speeds if the USB main platform has already allocated resources to other devices.

The USB controller also deals with lightning modules and determines the size and type of manufacture of these modules. The controller then constructs an identification structure containing this information as well as the translation table and the logical address space.

After the USB master controller identifies the USB flash device, the master platform often updates a USB client drive. The unit issues an ID request command to the USB master controller, which forces the controller to transmit an ID data packet 80, shown in Fig. 7. ID packet 80 contains a PID field 22 and a sum field. 26 as previously described for prior art Fig. 2. The identification packet 80 also contains an operation identification code in an operation code field 82. The USB flash device packet extractor receives an identification data packet 80 and transfers the operation code of the identification command to the device for interpreting application commands.

In response to the identification command, the lightning device then sends an identification data packet 84, shown in Fig. 8. In addition to the fields shown in Fig. 7, the identification data packet 84 also contains information about the size of the lightning device in a lightning device size field 86, as well as minimum disposal unit size information to eliminate lightning memory in a disposal unit size field 88.

All packets described in this example are only data packets that are sent on the USB bus. Before each data packet is sent, a USB core packet

54 1,548,604 / ΡΤ is transmitted to instruct the USB controller with the identity of the device endpoint to which the data packet is to be transmitted. Upon successful reception of the packet, the USB controller issues a USB ACK packet as described in the USB specification.

Once the device control units on the main platform receive this status pack, the control units can start issuing read and write commands to the USB flash device with the application commands. When a write request is sent, a USB data packet with the operation code for the write command and the buffer containing the data is transferred to the USB flash device. A write data packet 90 is shown in Fig. 9, which again includes the fields shown previously in Fig. 8, except the writing data packet 90 which also includes a writing field 92 with the writing operating code; an ADDR field 94 with the logical address to write; a LEN 96 field with the length to type; and a DATA field 98 containing the actual data to write. The packet extractor extracts the operational code from the write data packet 90 and transfers this code to the application command interpreter. The logical address is transferred to the address resolution module which translates this logical address to a physical address in one of the lightning modules. The data manipulation device optionally calculates error detection and correction mechanisms employed by the USB flash device. Once all the flash memory modules are ready, a write command is sent to the flash module or modules containing the physical address, which may optionally cover more than one flash module for the MTD block. The MTD block then issues a data bus / address write command, which connects the flash modules to the USB device driver. Once the operation is complete and a status packet is returned to the MTD, the result of the operation is transmitted to the main controller and passed to the device unit on the main platform.

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When the flash controller completes the writing process, the controller signals the main platform that the state of the USB flash memory device has changed by sending a writing state packet 100 as shown in Fig. 10. In place of the data field 98, write state packet 100 contains a state field 102. The main platform reads the state packets from the flash memory device and the write state pack 100, the main platform retrieves information on the completion state of the write command by reading the state field 102. In this example, the read device flash memory repeats field ADDR 94 and field LEN 96 so that the main platform has a reference to the state packet specific command 100.

As shown in Fig. 11, a read request packet 104 contains the operation code for the read command in a read field 106 and the desired location logical address from which the lightning controller should read in an ADDR field 108. Upon receipt of this command, the lightning controller issues a read command to the MTD block after the address resolution module has transferred the address contained in field ADDR 108 to a specific physical address in one of the lightning (flash) components.

When the lightning controller receives data from the lightning device, either after the read command is issued or an error has occurred, the lightning controller sends a signal to the main platform to indicate that a new status packet must be read. The main platform issues a read request and receives a read state packet 110 as shown in Fig. 12. The read state packet 110 contains the read data address in the ADDR field 108 as well as the length of the read data in a LEN field 112 and the data itself in a data field 114. The read state pack 110 also features the status word, according to which the operation was completed, in a state field 116. The read operation can be completed with many different state situations such as success, failure, error detected, invalid address, invalid length and so on.

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When the main platform needs to delete a disposal unit on the lightning device, the main platform issues a delete request packet 118, shown in Fig. 13. This packet contains the delete operation code in a delete field 120 and the address unit logic in an ADDR 122 field. Upon receipt of such a request, the lightning controller converts the logical address to a physical disposal unit address into one of the physical address spaces of the lightning modules and issues a delete command to the MTD block.

The delete command usually takes longer than a read or write process. When this deletion process is complete, the controller notifies the primary platform that a new status pack is ready for transmission. The controller then transmits a delete state packet 124 as shown in Fig. 14. The deletion state packet 124 contains the address of the deleted unit in field ADDR 122, thereby providing the main platform with a reference to the deletion requests. The state according to which the operation was completed is provided in a state field 126.

Lisbon, 2010-02-12

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