Architecture for a universal serial bus-based PC flash disk

Field and Background of the Invention

0001The present invention is related to semiconductor memory devices, and in particular to erasable and programmable nonvolatile memory modules which are connected to a host platform using the USB PC Bus.

0002Erasable and programmable non-volatile memory modules, hereinafter referred to as flash memory or flash devices, are known in the art for storage of information. Flash devices include electrically erasable and programmable read-only memories (EEPROMs) made of flash-type, floating-gate transistors and are non-volatile memories similar in functionality and performance to EPROM memories, with an additional functionality that allows an in-circuit, programmable, operation to erase pages of the memory. One example of an implementation of such a flash device is given in <patcit id="pcit0001" dnum="US5799168A"><text>U.S. Patent No. 5,799,168</text></patcit>.

0003This document discloses a flash memory controller which reports the number of flash chips present. Using the Read ID mode inherent in flash chips (in which reading from any address returns one of several fixed codes that identify the chip's manufacturer and type), the standardized controller dynamically identifies the array it is handling by issuing Read ID commands to ascending addresses in order to identify the presence of chips at that location, and in this manner to automatically detect the number of chips and the interleaving.

0004Flash devices have the advantage of being relatively inexpensive and requiring relatively little power as compared to traditional magnetic storage disks. However, in a flash device, it is not practical to rewrite a previously written area of the memory without a preceding page erase of the area. This limitation of flash devices causes them to be incompatible with typical existing operating system programs, since data cannot be written to an area of memory within the flash device in which data has previously been written, unless the area is first erased.

0005The document <patcit id="pcit0002" dnum="US5404485A"><text>US5404485</text></patcit> discloses a flash memory controller that provides a fully rewritable virtual address space so that the flash memory emulates a random access memory wherein the controller updates an address translation table.

0006Currently, these flash memory devices have a second limitation, which is that they must be either attached statically to the host platform, or attached and detached dynamically using the PCMCIA [Personal Computer Memory Card International Association] interface. Both implementations have drawbacks, including difficulty of use and high cost.

0007A more useful implementation would follow the USB standard, as described in the USB Specification Version 1.1. The USB standard offers a smaller form factor and greater ease of use for the end user, while lowering the cost of the implementation. This standard is specified to be an industry-wide standard promoted by companies such as Compaq Computer Corporation, Microsoft, IBM and Intel to serve as an extension to the PC architecture with a focus on Computer Telephony Integration (CTI), the consumer, and productivity applications.

0008The "Universal Serial Bus Mass Storage Class Specification Overview V1.0" of 22 October 1998 suggests to use USB for mass storage devices and wrap existing storage protocols for mass storage devices with a USB packet. One of the protocols considered in this document is the "Reduced Block Commands (RBC)" which is typically used for flash devices.

0009The criteria which were applied to define the architecture for the USB standard include the ease of PC (personal computer) peripheral expansion, low cost, support of transfer rates up to 12Mb/second and full support for real-time data, voice, audio, and compressed video. This standard also offers protocol flexibility for mixed-mode isochronous data transfers and asynchronous messaging, integration in commodity device technology and provision of a standard interface for rapid integration into any given host product. In addition, the USB standard represents a single model for cabling and attaching connectors, such that all of the details of the electrical functions, including bus terminations, are isolated from the end user. Through the standard, the peripheral devices are self-identifying, and support automatic mapping of functions to a driver. Furthermore, the standard enables all peripheral devices to be dynamically attachable and re-configurable.

0010A system constructed according to the USB standard is described by three separate, defined areas: USB interconnection, USB devices and the USB host platform. The USB interconnection is the manner in which USB devices are connected to, and communicate with, the host platform. The associated functions and components include the bus topology, which is the connection model between USB devices and the host platform.

0011The USB physical interconnection has a tiered star topology. A hub is at the center of each star. Each wire segment is a point-to-point connection between the host platform and a hub or function, or a hub connected to another hub or function.

0012In terms of a capability stack, the USB tasks which are performed at each layer in the system include a data flow model and a schedule. A data flow model is the manner in which data moves in the system over the USB between data producers and data consumers. A schedule determines access to the interconnection, which is shared. Such scheduling enables isochronous data transfers to be supported and eliminates arbitration overhead.

0013The USB itself is a polled bus. The host controller on the host platform initiates all data transfers. All bus transactions involve the transmission of up to three packets. Each transaction begins when the host controller, on a scheduled basis, sends a USB packet describing the type and direction of transaction, the USB device address, and endpoint number. This packet is referred to as the "token packet." The USB device, to which the packet is addressed, selects itself by decoding the appropriate address fields. In a given transaction, data is transferred either from the host platform to a device or from a device to the host platform. The direction of data transfer is specified in the token packet. The source of the transaction then sends a data packet or indicates that the source has no data to transfer. The destination, in general, responds with a handshake packet indicating whether the transfer was successful.

0014The USB data transfer model between a source and destination on the host platform and an endpoint on a device is referred to as a "pipe". There are two types of pipes: stream and message. Stream data has no USB-defined structure, while message data does. Additionally, pipes have associations of data bandwidth, transfer service type, and endpoint characteristics like directionality and buffer sizes. Most pipes come into existence when a USB device is configured. One message pipe, the default control pipe, always exists once a device is powered, in order to provide access to the configuration, status, and control information for the device.

0015The transaction schedule for the USB standard permits flow control for some stream pipes. At the hardware level, this prevents situations in which buffers experience underrun or overrun, by using a NAK handshake to throttle the data rate. With the NAK handshake, a transaction is retried when bus time is available. The flow control mechanism permits the construction of flexible schedules which accommodate concurrent servicing of a heterogeneous mix of stream pipes. Thus, multiple stream pipes can be serviced at different intervals with packets of different sizes.

0016The USB standard, as described, has three main types of packets, including token packets, data packets and handshake packets. An example of each type of packet is shown in background art <figref idref="f0001">Figures 1-3</figref>. Background art <figref idref="f0002">Figure 4</figref> shows an exemplary USB abstract device.

0017A token packet <b>10</b>, as shown in background art <figref idref="f0001">Figure 1</figref>, features a PID (packet identification) field <b>12,</b> specifying one of three packet types: IN, OUT, or SETUP. If PID field <b>12</b> specifies the IN packet type, the data transaction is defined from a function to the host platform. If PID field <b>12</b> specifies the OUT or SETUP packet type, the data transaction is defined from the host platform to a function.

0018An ADDR field <b>14</b> specifies the address, while an ENDP field <b>16</b> specifies the endpoint for token packet <b>10</b>. For OUT and SETUP transactions, in which PID field <b>12</b> specifies that token packet <b>10</b> is an OUT packet type or a SETUP packet type, ADDR field <b>14</b> and ENDP field <b>16</b> uniquely identify the endpoint for receiving the subsequent data packet, shown in <figref idref="f0001">Figure 2</figref>, which follows after token packet <b>10</b>. For IN transactions, in which PID field <b>12</b> specifies that token packet <b>10</b> is an IN packet type, ADDR field <b>14</b> and ENDP field <b>16</b> uniquely identify which endpoint stransmit a data packet. A CRC5 field <b>18</b> contains the checksum, for determining that token packet <b>10</b> has been received without corruption. Only host platform can issue token packets <b>10</b>, such that token packets <b>10</b> provide control over transmission of the subsequent data packets.

0019As shown in background art <figref idref="f0001">Figure 2</figref>, a background art USB data packet <b>20</b> also features a PID (packet identification) field <b>22</b> for identifying the type of data packet. Data packet <b>20</b> also features a data field <b>24</b> for optionally containing data, and a CRC field <b>26</b> for containing the checksum as previously described.

0020Background art <figref idref="f0001">Figure 3</figref> shows a background art USB handshake packet <b>28</b>, which features only a PID (packet identification) field <b>30</b>. Handshake packets <b>28</b> are used to report the status of a data transaction and can return values indicating successful reception of data, command acceptance or rejection, flow control, and halt conditions. Only transaction types which support flow control can return handshake packets <b>28</b>. Handshake packets <b>28</b> are always returned in the handshake phase of a transaction and may be returned, instead of data packets <b>20</b>, in the data phase of a transaction.

0021These three different types of packets are exchanged during various phases of the transaction which includes a USB device. A schematic block diagram of the functional blocks in a typical USB device <b>32</b> is shown in <figref idref="f0002">Figure 4</figref> for an abstract background art USB device. USB device <b>32</b> typically includes a USB electrical interface <b>34</b>, featuring a cable and a connector, which is a physical interface for receiving and transmitting electrical signals which are compatible with the USB specification as previously described. The signals are then passed to a logical interface <b>36</b>, which includes one or more buffers, the device address decoder for decoding the address of the source device for the signals, and a SYNC field synchronizer for synchronizing the signals. Information and structures required for management of USB abstract device <b>32</b> as a USB device are stored in a USB class control and enumeration engine <b>38.</b> A function and device engine <b>40,</b> also termed the "application", controls and manages the specific functions and properties of USB abstract device <b>32.</b> In addition, function and device engine <b>40</b> also consumes and produces most of the data over the USB bus.

0022The USB specification does not define the relationship between different entities in USB abstract device <b>32,</b> however. Rather, the USB specification describes only the requirements for the packets, and for the electrical and physical connection between USB abstract device <b>32</b> and the bus. Therefore the connections and relationships shown in background art <figref idref="f0002">Figure 4</figref> are only one example of an implementation which fulfills the requirements of the USB specification. Thus, any specific device for fulfilling the USB specification must have a specifically defined and described architecture.

0023Unfortunately, no such architecture exists for a flash memory device containing one or more flash memory modules, which would enable the flash memory device to connect to a bus defined according to the USB specification and thereby to form part of a USB system on a host platform. For example, <patcit id="pcit0003" dnum="US5799168A"><text>U.S. Patent No. 5,799,168</text></patcit> does not teach or suggest such an implementation for the flash device. As mentioned previously, such an architecture would be particularly useful for a number of reasons, including low cost, ease of use and transparency to the end user.

0024There is thus a need for, and it would be useful to have, an architecture for defining and describing a flash memory device which is compatible with a USB system and which follows the USB specification, such that the flash memory device could sit on a USB-defined bus and communicate with the host platform through this bus.

Brief Description of the Drawings

0025<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">FIG. 1</figref> is a schematic block diagram of a background art USB token packet structure;</li><li><figref idref="f0001">FIG. 2</figref> is a schematic block diagram of a background art USB data packet structure;</li><li><figref idref="f0001">FIG. 3</figref> is a schematic block diagram of a background art USB handshake data packet structure;</li><li><figref idref="f0002">FIG. 4</figref> is a schematic block diagram of an exemplary background art USB device;</li><li><figref idref="f0003">FIG. 5</figref> is a schematic block diagram of a system with a flash USB device functionality according to the present invention;</li><li><figref idref="f0004">FIG. 6</figref> is a schematic block diagram of the USB Flash disk;</li><li><figref idref="f0005">FIG. 7</figref> is a schematic block diagram of a flash identification request packet;</li><li><figref idref="f0005">FIG. 8</figref> is a schematic block diagram of a flash identification status packet;</li><li><figref idref="f0005">FIG. 9</figref> is a schematic block diagram of a flash write request packet;</li><li><figref idref="f0006">FIG. 10</figref> is a schematic block diagram of a flash write status packet;</li><li><figref idref="f0006">FIG. 11</figref> is a schematic block diagram of a flash read request packet;</li><li><figref idref="f0006">FIG. 12</figref> is a schematic block diagram of flash read status packet;</li><li><figref idref="f0007">FIG. 13</figref> is a schematic block diagram of a flash erase request packet; and</li><li><figref idref="f0007">FIG. 14</figref> is a schematic block diagram of a flash erase status packet.</li></ul>

Summary of the Invention

0026The present invention is of a flash memory device, containing one or more flash modules, in which the flash memory is mapped to the address space of an ASIC or a controller which has a USB-defined electrical interface and a USB-defined logical interface. This controller/ASIC (hereinafter termed a "controller") supports the USB functionality according to the USB standard, thereby supporting enumeration onto the USB bus, as well as data reception and transmission over USB pipes to and from USB endpoints. This controller also supports the functionality and control of the flash memory device, as well as the processing of command and data packets from the host controller. The host controller uses one of several possible protocols, either standard or proprietary, to signal the next command to be performed to the USB flash controller. Thus, the entire device acts as a dynamically attachable/detachable non-volatile storage device for the host platform.

0027According to the present invention, there is provided a USB flash memory device and method as defined in the appended independent claims.

0028Hereinafter, the term "computer" includes, but is not limited to, personal computers (PC) having an operating system such as DOS, Windows™, OS/2™ or Linux; Macintosh™ computers; computers having JAVA™-OS as the operating system; and graphical workstations such as the computers of Sun Microsystems™ and Silicon Graphics™, and other computers having some version of the UNIX operating system such as AIX™ or SOLARIS™ of Sun Microsystems™; or any other known and available operating system, including operating systems such as Windows CE™ for embedded systems, including cellular telephones, handheld computational devices and palmtop computational devices, and any other computational device which can be connected to a network. Hereinafter, the term "Windows^TM" includes but is not limited to Windows95™, Windows 3.x™ in which "x" is an integer such as "1", Windows NT™, Windows98™, Windows CE™ and any upgraded versions of these operating systems by Microsoft Inc. (Seattle, Washington, USA).

Detailed Description of the Invention

0029The present invention is of a flash memory device, containing one or more flash modules, in which the flash memory is mapped to the address space of an ASIC or a controller which has a USB-defined electrical interface and a USB-defined logical interface. This controller/ASIC (hereinafter termed a "controller") supports the USB functionality according to the USB standard, thereby supporting enumeration onto the USB bus, as well as data reception and transmission over USB pipes to and from USB endpoints. This controller also supports the functionality and control of the flash memory dev, as well as the processing of command and data packets from the host controller. The host controller uses one of several possible protocols, either standard or proprietary, to signal the next command to be performed to the USB flash controller. Thus, the entire device acts as a dynamically attachable/detachable non-volatile storage device for the host platform.

0030While the invention is susceptible to various modifications and can be implemented using many alternative forms, the embodiment is shown by way of example in the drawings and will be described in details in the following pages. It should be understood that one of ordinary skill in the art appreciates that the present invention could be implemented in various other ways. The intention is to cover all modifications and alternatives falling within the spirit of the current invention.

0031The principles and operation of a USB flash device and system according to the present invention may be better understood with reference to the drawings and the accompanying description, it being understood that these drawings are given for illustrative purposes only and are not meant to be limiting.

0032Referring now to the drawings, <figref idref="f0003">Figure 5</figref> is a schematic block diagram of the main components of a flash memory device and system according to the present invention. A flash memory system <b>42</b> includes a host platform <b>44</b> as shown. Host platform <b>44</b> operates USB flash device <b>46</b> as a non-volatile storage space.

0033Host platform <b>44</b> is connected to USB flash device <b>46</b> according to the present invention through a USB cable <b>48</b>. Host platform <b>44</b> connects to USB cable <b>48</b> through a USB host connector <b>50</b>, while USB flash device <b>46</b> connects to USB cable <b>48</b> through a USB flash device connector <b>52</b>. Host platform <b>44</b> features a USB host controller <b>54</b> for controlling and managing all USB transfers on the USB bus.

0034USB flash device <b>46</b> features a USB flash device controller <b>56</b> for controlling the other components of USB flash device <b>46</b> and for providing an interface for USB flash device <b>46</b> to the USB bus, USB flash device connector <b>52</b> and at least one flash memory module <b>58</b>. Flash memory module <b>58</b> is preferably an array of flash memory modules <b>58</b> in which the data is stored.

0035Whenever USB flash device <b>46</b> becomes connected to host platform <b>44</b>, a standard USB enumeration process takes place. In this process host platform <b>44</b> configures USB flash device <b>46</b> and the mode of communication with USB flash device <b>46</b>. Although there are many different methods for configuring USB flash device <b>46</b>, for the purposes of clarity only and without intending to be limiting, the present invention is explained in greater detail below with regard to a method in which host platform <b>44</b> issues commands and requests to USB flash device <b>46</b> through one endpoint. Host platform <b>44</b> queries USB flash device <b>46</b> through the other endpoint for status changes, and receives related packets if any such packets are waiting to be received.

0036Host platform <b>44</b> requests services from USB flash device <b>46</b> by sending request packets to USB host controller <b>54.</b> USB host controller <b>54</b> transmits packets on USB cable <b>48</b>. These requests are received by USB flash device controller <b>56</b> when USB flash device <b>46</b> is the device on the endpoint of the request. USB flash device controller <b>56</b> then performs various operations such as reading, writing or erasing data from or to flash memory module(s) <b>58</b>, or supporting basic USB functionality such as device enumeration and configuration. USB flash device controller <b>56</b> controls flash memory module(s) <b>58</b> by using a control line <b>60</b> to control the power of flash memory module(s) <b>58</b>, and also through various other signals such as chip enable, and read and write signals for example. Flash memory module(s) <b>58</b> are also connected to USB flash device controller <b>56</b> by an address/data bus <b>62</b>. Address/data bus <b>62</b> transfers commands for performing read, write or erase commands on flash memory module(s) <b>58</b>, as well as the addresses and data for these commands as defined by the manufacturer of flash memory module(s) <b>58</b>.

0037In order for USB flash device <b>46</b> to notify host platform <b>44</b> on the result and status for different operations requested by host platform <b>44</b>, USB flash device <b>46</b> transmits status packets using the "status end point". According to this procedure, host platform <b>44</b> checks (polls) for status packets and USB flash device <b>46</b> returns either an empty packet if no packets for new status messages are present, or alternatively returns the status packet itself.

0038A more detailed structure of the functional components of USB flash device <b>46</b> is shown in <figref idref="f0004">Figure 6</figref>. USB flash device <b>46</b> includes the physical and electrical interface defined for the USB standard, shown here as USB flash device connector <b>52</b> and a connector interface <b>64</b>. USB flash device connector <b>52</b> receives the electrical signals from USB cable <b>48</b> which carries electrical signals from host controller (not shown). These signals are then passed through connector interface <b>64</b>. Every millisecond, a USB frame is carried on the USB-defined bus, such that packets could be sent to USB flash device <b>46</b>.

0039Connector interface <b>64</b> then receives these packets through a first interface component, which is a combined physical and logical interface <b>66</b>. A functional interface <b>68</b> is specifically designed to receive token packets as defined in the USB specification and as previously described with regard to <figref idref="f0001">Figure 1</figref>. These token packets are related only to particular functional aspects of USB flash device <b>46</b> which are required for the USB standard, and do not have any relation to particular application of USB flash device <b>46</b> as a flash disk according to the present invention. These token packets and their respective returned data packets enable USB host controller <b>54</b> (not shown) and host platform <b>44</b> (not shown) to identify USB flash device <b>46</b> and allocate resources for USB flash device <b>46</b> on the USB bus. Thus, functional interface <b>68</b> only supports USB functionality needed for the identification and registration of USB flash device <b>46</b> on the USB bus.

0040USB flash device <b>46</b> also features an application packet extractor <b>70</b> which extracts the application data and commands from the USB application packets, such that application packet extractor <b>70</b> supports only application related packets. Next, any requests to USB flash device <b>46</b> by host platform <b>44</b> (not shown), in the form of read, write, identify and erase commands, are interpreted by an application command interpreter <b>72</b>. For any commands which involve data or an address, such as read, write and erase commands, an address resolve module <b>74</b> translates the address from the logical address space to the physical address space. Host platform <b>44</b> (not shown) relates to a linear address space of logical addresses, while USB flash device <b>46</b> contains at least one, and preferably a plurality of, flash modules <b>58</b>, each of which has a physical address space. Thus, a translation must be performed between the logical address space of host platform <b>44</b> (not shown) and physical address space or spaces of USB flash device <b>46.</b> There are many ways to implement such a translation which are suitable for the present invention. One example of a suitable implementation of an address translation method is described with regard to <patcit id="pcit0004" dnum="US5404485A"><text>U.S. Patent No. 5,404,485</text></patcit>, which teaches a method for managing a flash memory as a flash disk and which is suitable for operation with the present invention.

0041A data handler <b>76</b> handles data related aspects of any received commands, and conveying the data through functional interface <b>68</b> to and from flash module(s) <b>58</b>. Optionally and preferably, data handler <b>76</b> performs any error correction and detection methods. Application command interpreter <b>72</b>, data handler <b>76</b> and address resolve module <b>74</b> all operate with an underlying Memory Technology Driver (MTD) <b>78</b> to write, read or erase a particular flash module <b>58</b> and the desired address on that flash module <b>58.</b>

0042Host platform <b>44</b> checks for status changes in USB flash device <b>46</b> and reads status packets from USB flash device <b>46</b> when a new status pacis available. Using these status packets, USB flash device <b>46</b> can transmit, to host platform <b>44</b>, the results of different commands issued by host platform <b>44</b> in its requests (not shown). For example, the read command status packet contains one of the available status words such as "success", "error" or "invalid address", which enables host platform <b>44</b> to determine the result of the read command (not shown). Similarly, the erase status packet contains a status word indicating the completion of the erase process. A write status packet is used by USB flash device <b>46</b> to notify host platform <b>44</b> about the result of the write command, for example whether the command was successful or erroneous, and whether USB flash device <b>46</b> is ready for additional write requests from host platform <b>44</b>.

0043A Memory Technology Driver, or MTD <b>78</b> typically contains routines to read, write and erase the flash memory device controlled by the controller operating MTD <b>78</b>. In addition, MTD <b>78</b> optionally contains an identification routine for recognizing the proper type of flash memory device for which MTD <b>78</b> was designed, so that the controller can determine which MTD should be activated upon interacting.with a particular flash memory device array. In addition, an identification routine should be able to detect the size of the array of flash memory devices, including the number of flash memory devices within the array, and various features of the flash array geometry, such as interleaving and bus width. This information later enables host platform <b>44</b> platform to determine the address space and size of the storage media. <patcit id="pcit0005" dnum="US5799168A"><text>U.S. Patent No. 5,799,168</text></patcit>, discloses an example of such an MTD for a flash device.

0044Using the above described protocol and architecture, host platform <b>44</b> can optionally implement any application which is implementable with any regular memory mapped or I/O mapped flash memory device. For example, host platform <b>44</b> can give a standard block device interface to each application, such as a magnetic storage medium "hard disk" drive, as disclosed in the previously described <patcit id="pcit0006" dnum="US5404485A"><text>U.S. Patent No. 5,404,485</text></patcit>.

0045As an example of a preferred embodiment of the present invention, the operation of a host system connected to a USB flash device according to the present invention is described with regard to the processes of identifying, programming, reading and erasing the flash device. For the purposes of illustration only and without intending to be limiting in any way, the exemplary USB flash device has an array of two flash memory modules, each of which is 64Mbit in size. The address translation table is within the flash device so that host platform operates with logical addresses. All commands and return codes between the flash device and the host platform are carried on USB data packets, and are transferred through USB data pipes. The exact structure of the packets, pipes and timings are described in the USB specification.

0046The operation of the exemplary device and system according to the present invention is as follows. When the USB flash device is first connected to the host platform, the USB host controller assigns an address to the USB flash device on the USB bus, and also assigns resources as described in the USB specification. The USB flash device actually asks the host platform to assign these resources, and must inform the host platform how much of these resources are needed. Thus, the USB flash disk can optionally support slower device speeds if the USB host platform has already allocated resources to other devices.

0047The USB controller also negotiates with the flash modules and determines the size and manufacturing type of these modules. The controller then builds an identification structure holding this information, as well as the translation table and logical address space.

0048After the USB host controller identifies the USB flash device, the host platform often uploads a USB client driver. The driver issues an identification request command to the USB host controller, causing the controller to transmit an identification data packet <b>80</b>, shown in <figref idref="f0005">Figure 7</figref>. Identification packet <b>80</b> contains PID field <b>22</b> and checksum field <b>26,</b> as described previously for background art <figref idref="f0001">Figure 2</figref>. Identification packet <b>80</b> also contains an "identify" operation code in an operation code field <b>82</b>. The packet extractor of the USB flash device receives identification data packet <b>80</b> and transfers the operating code of the "identify" command to the application command interpreter.

0049In response to the "identify" command, the flash device then sends an identification data packet <b>84</b>, shown in <figref idref="f0005">Figure 8</figref>. In addition to the fields shown in <figref idref="f0005">Figure 7</figref>, identification data packet <b>84</b> also contains information about the size of the flash device in a flash device size field <b>86</b>, as well as information about the size of the minimal erase unit for erasing the flash memory in an erase unit size field <b>88</b>.

0050All of the packets described in this example are only data packets which are sent on the USB bus. Before each data packet is sent, a USB token packet is transmitted, instructing the USB controller as to the identity of the device end point to which the data packet should be transmitted. Upon successful reception of the packet, the USB controller issues a USB ACK packet as described in the USB specification.

0051Once the device drivers in the host platform receive this status packet, the drivers can start issuing read and write commands to the USB flash device with the application commands. When a write request is sent, a USB data packet with the operation code for the "write" command, and the buffer containing the data, is transferred to the USB flash device. A write data packet <b>90</b> is shown in <figref idref="f0005">Figure 9</figref>, which again includes the fields shown previously in <figref idref="f0005">Figure 8</figref>, except that write data packet <b>90</b> also includes a write field <b>92</b> with the "write" operational code; an ADDR field <b>94</b> with the logical address to be written; a LEN field <b>96</b> with the length to be written; and a DATA field <b>98</b> which contains the actual data to write. The packet extractor extracts the operational code from write data packet <b>90</b> and transfers this code to the application command interpreter. The logical address is transferred to the address resolve module which translates this logical address to a physical address on one of the flash modules. The data handler optionally calculates error correction and detection mechanisms if employed by the USB flash device. Once all of the flash memory modules are ready, a "write" command is sent to the flash module or modules containing the physical address, which may optionally span across more than one flash module to the MTD block. The MTD block then issues a "write" command on the data/address bus which connects the flash modules to the USB device controller. Once the operation is complete and a status packet is returned to the MTD, the result of the operation is transmitted to the host controller and passed to the device driver in the host platform.

0052When the flash controller finishes the writing process, the controller signals to the host platform that the status of the USB flash memory device has changed, by sending a "write status" packet <b>100,</b> as shown in <figref idref="f0006">Figure 10</figref>. In place of data field <b>98,</b> write status packet <b>100</b> contains a status field <b>102.</b> The host platform reads the status packets from the flash memory device, and from write status packet <b>100,</b> the host platform retrieves information on the completion status of the write command by reading status field <b>102.</b> In this example, the flash memory device repeats ADDR field <b>94</b> and LEN field <b>96</b> in order for the host platform to have a reference to the specific command related to status packet <b>100</b>.

0053As shown in <figref idref="f0006">Figure 11</figref>, a "read request" packet <b>104</b> contains the operation code for the "read" command in a read field <b>106</b>, and the logical address of the desired location from which the flash controller should read in an ADDR field <b>108</b>. Upon receiving this command, the flash controller issues a read command to the MTD block, after the address resolve module has translated the address contained in ADDR field <b>108</b> toa specific physical address in one of the flash components.

0054When the flash controller receives the data from the flash device, either after the read command was issued, or if an error occurred, the flash controller sends a signal to the host platform to indicate that a new status packet must be read. The host platform issues a read request and receives a "read status" packet <b>110</b> as shown in <figref idref="f0006">Figure 12</figref>. Read status packet <b>110</b> contains the address of the read data in ADDR field <b>108</b>, as well as the length of the read data in a LEN field <b>112</b> and the data itself in a data field <b>114</b>. Read status packet <b>110</b> also features the status word, according to which the operation was completed, in a status field <b>116</b>. The read operation can be completed with many different status situations such as success, fail, error detected, invalid address, invalid length and so forth.

0055When the host platform needs to erase an erase unit in the flash device, the host platform issues an "erase request" packet <b>118</b>, shown in <figref idref="f0007">Figure 13</figref>. This packet contains the "erase" operation code in an erase field <b>120,</b> and the logical address of the erase unit in an ADDR field <b>122.</b> Upon receiving such a request, the flash controller translates the logical address to a physical erase unit address on one of the physical address spaces of the flash modules, and issues an erase command to the MTD block.

0056The erase process generally takes more time then a read or write process. When this erase process is finished, the controller notifies the host platform a new status packet is ready to transmit. The controller then transmits an "erase status" packet <b>124</b>, as shown in <figref idref="f0007">Figure 14</figref>. Erase status packet <b>124</b> contains the address of the erased unit in ADDR field <b>122</b>, thereby providing the host platform with a reference to the erase requests. The status according to which the operation was completed is provided in a status field <b>126</b>.