Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

Present The present The receiving The receiving The receiving The receiving The receiving The receiving The receiving The The The The The The The The The The The The The The The. .

[0002] As digital broadcasting technologies have developed, users have been receiving a high resolution moving image

HD)

With the continuous development of the algorithms and high in the future, users will have a better environment (environment). A digital TV system (DTV) can be used, as well as an audio signal.

[0003] US 2006/221810 discloses a method for synchronizing receiver clocking to a received orthogonal frequency multiplexing (OFDM) signal. The first timing is performed with a multiplexed time pilot signal (TDM) to determine the course of the OFDM signal. A second timing is carried out with the second one. The TDM is a symbol of the received OFDM signal. In the second timing acquisition, the cumulative energy of the accumulated energy curve is detected.

[0004] With the development of digital broadcasting technologies, (FT) for information, requirements for services such as video signal and signal

The size of the channels is the same.

[0005] Therefore, the present invention is a method of receiving and receiving a signal receiving from a prior art problem.

[0006] The object of the present invention is to provide a method for receiving and receiving a signal.

[0007] Another object of the present invention is a signal for the reception configuring bits.

[0008] These and other objects are subject to the claim 11. Additional benefits, objectives, and features person after reading the application of the invention. Предпределение на предложение на следнические следнители.

The accompanying drawings, which is incorporated into the concept of the invention. Invention. In the drawings:

[0010] FIG. 1 is a view showing a signal frame for transmitting a service;

[0011] FIG. 2 is a view of the first pilot signal P1 of the signal frame;

[0012] FIG. 3 is a view showing a signaling window;

53 / 55P2208 [0013] FIG. 4 is a view showing the device for transmitting a signal;

[0014] FIG. 5 is a view showing an example of an input processor 110;

[0015] FIG. 6 is a view of the coding and modulation unit;

[0016] FIG. 7 is a view showing an embodiment of a frame builder;

[0017] Fig. 8 is a view of the mappers 131a and 131b perform hybrid symbol mapping;

[0018] FIG. 9 is a view showing a mappers 131 a and 131 b perform hybrid symbol mapping;

[0019] FIG. 10 is a view showing the number of symbols and numbers of bits per cell word LDPC mode;

[0020] FIG. 11 is a view showing another example of the number of symbols in the LDPC mode;

[0021] FIG. 12 is a view showing another example of the number of symbols in the LDPC mode;

[0022] FIG. 13 is a view showing the number of symbols in the LDPC short mode;

[0023] FIG. 14 is a view of the LDPC short mode;

[0024] FIG. 15 is a view showing another example of the number of symbols in the LDPC short mode;

53 / 55P [0025] FIG. 16 is a view of the element symbol 131a and 131b depicted in FIG. 7;

[0026] FIG. 17 is a view showing another embodiment of each symbol mapping member 131a and 131b;

[0027] FIG. 18 is a view showing another symbol of the symbol of mapper;

[0028] FIG. 19 is a view showing another embodiment of each symbol mapping member 131a and 131b;

[0029] FIG. 20 is a view showing the idea of ​​interleaving bits by bit interleavers 1312a and 1312b;

[0030] Fig. 21 is a view of the 1331 and 1312b types of the interleavers 1312a and 1312b according to the types of symbol mappers 1315a and 1315b;

[0031] Fig. 22 is a view of the intersection 1312a and 1312b according to the types of symbol mappers 1315a and 1315b;

[0032] FIG. 23 is a view showing the idea of ​​an interleaver;

[0033] FIG. 24 is a view showing another embodiment of bit interleaving;

[0034] FIG. 25 is a view showing another embodiment of bit interleaving;

[0035] FIG. 26 is a view showing the idea of ​​demultiplexing input bits of demuxs 1313a and 1313b;

[0036] FIG. 27 is a view of demultiplexing;

53 / 55P [0037] FIG. 28 is a view showing an example of a demultiplexing type according to a a symbol mapping method; [0038] FIG. 29 is a view showing an embodiment of demultiplexing type;

[0039] FIG. 30 is a view showing a demultiplexing type of error correction coding and the symbol mapping method;

[0040] FIG. 31 is a view showing an example expressing the method of demultiplexing by the equation;

[0041] FIG. 32 is a view of the mapping a symbol by a symbol mapper;

<td>[0042] FIG. 33 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>multi-path signal encoder; [0043] FIG. 34 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>implementation of the modulator; [0044] FIG. 35 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>implementation of an analog processor [0045] FIG. 36 presents</td><td>160; view</td><td>illustrating</td><td>example</td>

<td colspan="2">making the receiving device</td><td colspan="2">signal capable of</td>

<td>receiving a signal frame; [0046] FIG. 37 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>implementation of the signal receiver; [0047] FIG. 38 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>making the demodulator; [0048] FIG. 39 presents</td><td>view</td><td colspan="2">illustrating multi-way</td>

<td>signal decoder; [0049] FIG. 40 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>implementation of the frame parser; [0050] FIG. 41 presents</td><td>view</td><td>illustrating</td><td>example</td>

<td>implementation of each element</td><td>247a</td><td>and 247p</td><td>vice versa</td>

mapping symbols;

53 / 55P [0051] FIG. 42 is a view showing another symbol of demappers 247a and 247p;

[0052] FIG. 43 is a view showing another symbol of demappers 247 a and 247 p;

[0053] FIG. 44 is a view showing another symbol of demappers 247a and 247p;

[0054] FIG. 45 is a view of multiplexing a demultiplexed sub stream; [0055] FIG. 46 is a view illustrating {eg} an example of a decoding and demodulation unit;

[0056] FIG. 47 is a view showing an exemplary embodiment;

[0067] FIG. 48 is a view showing a signaling mechanism;

[0068] FIG. 49 is a view of receiving a signal frame for receiving a signal frame;

[0059] FIG. 50 is a view of the first pilot signal;

[0060] FIG. 51 is a view showing the embodiment of the message. 50 and estimate the time shift and frequency offset;

[0061] FIG. 52 is a view showing another structure of a first pilot signal;

[0062] FIG. 53 is a view of the first remote control signal shown in FIG. 52 and measuring the time shift and frequency offset;

53 / 55P [0063] FIG. 54 is a view of the first and second shift signal;

[0064] FIG. 55 is a view showing a method for transmitting a signal;

[0065] FIG. 56 is a view of receiving a signal; and [0066] FIG. 57 is a flowchart illustrating the change in the demodulation process.

[0067] Preferred embodiments of the present invention. Wherever possible, the same reference numerals will be used in the same design.

In the present specification, the term "service" or the provision of a device.

[0069] Before an apparatus for transmitting and receiving a signal, please contact present invention.

[0070] FIG. 1 shows a signal frame for transmitting a service. [0071] The signal frame shown in FIG. 1 shows an exemplary signal frame for transmitting a broadcast service including audio / video (A / V) streams. In this case, a single service is multiplexed in time and multiplexed service is transmitted. The above scheme of signal transmission

53 is a time-frequency slicing (TFS) scheme. Band RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF. RF band that it can he obtains a multiplexing increase capable of transmitting more services. The signal transmitting / receiving device transmits / receipts / frequency.

[0072] First to third services (Services 1 ~ 3) are transmitted to four RF bands (RF1 ~ RF4). However, this number is forbidden. Two reference signals (ie, the first pilot signal (P1) and the second pilot signal (P2)) are located at the beginning of the signal frame. For example, in the case of the RF1 band, the first pilot signal (P1) and the second pilot signal (P2) are located at the beginning of the signal frame. RF1 contains three slots associated with Service 1, two slots associated with Service 2, and a single slit related to the Service 3. Slots 4 ~ 17) located behind a single slot tied to the Service 3.

[0073] The RF2 band includes a first pilot signal (P1), and the second pilot signal (P2), and other slots 13-17. In addition, the RF2 band includes three slots associated with Service 1, two slots associated with Service 2, and a single associated slit. with Service 3.

[0074] Services 1 - 3 are multiplexed, and are transmitted to the RF3 and RF4 bands according to the partitioning scheme.

Time / Frequency (TFS). The modulation scheme for an orthogonal frequency multiplexing (OFDM) scheme.

[0075] In the signal frame, individual services are shifted to the RF bands (in this case there are a plurality of RF bands in the signal frame) and a time axis.

[0076] If signal frames are equal to the above signal frames, they can consist of different signal frames. The predicted extension frame may also be placed among different signal frames. If the expected extension frame is located, the super-frame may end in the expected extension frame.

[0077] FIG. 2 shows the first pilot signal (P1) included in the signal frame of FIG. 1 according to an embodiment of the present invention.

[0078] The first pilot signal P1 and the second pilot signal. The first remote signal P1 is modulated by the 2K FFT mode, and may be transmitted simultaneously with ¼ of the guard. In FIG. 2, the 7.61Mhz band from the first remote signal P1 contains the band 6.82992MHz. The first remote signal uses 256 carriers from 1705 active carriers. A single active carrier is used on average for every 6 carriers. The carrier data compartments may be arranged irregularly in order of 3, 6, and 9. In FIG. 2, the busier, the middle line, the middle carrier

In the first pilot signal, the BLC can be modulated. The size of the carrier should be pseudo-random

53 used for the second pilot signal may be indicated by different PRBS.

[0079] The signal reception apparatus detects a structure with a pilot signal and recognizes a time-frequency slicing (TFS) using the detected structure. The signal reception apparatus acquires the same signal, and acquires time synchronization.

[0080] In the first remote signal, a signal transmission type and a transmission parameter may be set.

[0081] The second pilot signal P2 may be transmitted. In the second pilot signal, a single carrier is used. The signal reception apparatus compensates for a fine frequency synchronization using a second pilot signal, and performs fine time synchronization. The second pilot signal transmits the first layer of information (L1) from the Open Systems Interconnection (OSI) layers. For example, the second pilot signal may include a physical parameter and frame construction information. The second pilot signal transmits the Physical Service (PLP) Service Stream.

[0082] L1 (Layer 1) information contained in the second pilot signal P2 is as follows.

[0083] The Layer-1 (L1) information includes a length, L1 and L2 information. The Layer-1 (L1) FEC (Forward Error Correction) for the FEC (Forward Error Correction)

53, contain various slots. On the physical, and the actual number of FECs. In this case, the frequency indicator indicates the RF channel.

[0084] Layer-1 (L1) information on the subject of OFDM carrier capability contained in the OFDM symbol, slot length, slots corresponding to the carrier OFDM, number of bits filled in the last. OFDM carrier, service modulation information, service mode, information rate, and schematic information. Multiple Inputs. Multiple Outputs (Multi-Input-Multi-Output

DESPITE).

[0085] The Layer-1 (L1) information may include a cell ID, a service flag as a notification service message (eg, a threat message), a number of current frames, and a number of additional bits for future use. In this case, the cell ID shows the broadcast area.

[0086] The second pilot signal P2 is adapted to perform a channel signal in the P2 signal. The second pilot signal P2 may be used for the next data symbol. The second pilot signal P2 may also transmit Layer-2 information (L2). For example, the second pilot is able to describe the Layer-2 (L2) information. The signal transmission device decodes the second remote control signal (TFS). Meanwhile, this Layer-2 (L2) information can be included in a specific pipe

53 / 55P29208PL00

PLP TFS frame. According to another case, the L2 information may be included in a specific PLP. [0087] For example, the second pilot signal may include an OFDM symbol of the 8k FFT mode. Essentially, the second pilot signal may be any single OFDM symbol from the 32K FFT mode, a single OFDM symbol from the 16k FFT mode, two OFDM symbols from the 8k FFT mode, four OFDM symbols from the 4k FFT mode, and eight OFDM symbols from the 2k FFT mode.

In other words, a single OFDM symbol having a large FFT size, may be included in the second remote signal. P2, such a bandwidth maintained. .

[0089] If the signal has to be transmitted, then the pilot has to be the second pilot of the signal, OFDM symbol of the second pilot signal. L1 (Layer1) and L2 (Layer2) information contained in the second remote control signal is error-corrected and then interleaved so that the impulse noise.

[0090] As described before, the PLP conveying the service description information.

[0091] FIG. 3 shows a signaling window. The time-frequency division frame (TFS) presents the idea of ​​shifting signaling information. The Layer-1 (L1) information contained in the process of the device. Thus, if the information is provided at the second pilot signal is contained

For a second pilot signal, the second pilot signal is sent to the second pilot signal.

[0092] Thus, as shown in FIG. 3, the L1 information contained in the second pilot signal (P2). This information is provided by the remote control signal by shifting the signaling. window. [0093] In the meantime, it is a performance symbol of the data symbol constructing the service, the data symbol may include a scatter pilot and a continual pilot.

[0094] Hereinafter, a signal transmission / reception system capable of transmitting / receiving signal frames in FIG. 1 -3. Individual services can be transmitted and received by individual RF channels. The path is called the PLP. The PLP can be distributed among the times-divided slots in several RF channels in a single RF band. This signal frame may carry a time-divided PLP to at least one RF channel. In other words, a single PLP can be transmitted through at least one RF channel with time-divided regions. In the following, the signal transmission / reception systems will be described. RF band.

[0094] FIG. 4 is a block diagram illustrating an apparatus for transmitting a signal. Regarding FIG. 4, the coding engine apparatus 110, a coding and modulation unit 120, a constructor 130

Each of the basic frames, the MIMO / MISO encoder 140, a plurality of modulators (150a, ..., 150r) of the MIMO / MISO encoder 140, and a plurality of analogue processors (160a, ..., 160r).

[0096] The input processor 110 is the number of streams containing services, generates a P number of band frames that contain the coding and modulation information.

[0097] The coding and modulation unit 110 receives the channel coding and interleaving result.

The frame builder 130 creates frames that transmit the baseband frames in the R number of the PL Rs. number of RF channels. Individual services can be multiplexed in a single RF channel over time. The signal frames from a frame builder 140 may include a time-frequency slicing (TFS) structure in multiplexed.

[0099] The MIMO / MISO encoder 140 encodes are transmitted to the R number of RF channels, and the number of antennas (where A is a natural number). The MIMO / MISO encoder 140 sends a signal from the MIMO (Multiple Input Multiple Outputs) MIMO (Multiple Input Multiple Outputs) structure - (Multi-Input-Multi-Output) or MISO (Multi-Input Single Output) (Multi-Input-Single-Output).

[0100] The modulators (150a, ..., 150r) modulate frequency-domain signals entered through the path

53, corresponding to each RF channel to time domain signals. The modulators (150a, ..., 150r) modulate the input signals according to orthogonal frequency multiplexing (OFDM) scheme, and outputs the modulated signals.

[0101] The analytical processors (160a, ..., 160r) convert input signals to RF signals so that RF signals can be sent to RF channels.

[0102] The signal transmission apparatus (150a, ... 150r) corresponds to the number of analog processors (160a, ..., 160r) corresponding to the number of RF channels. However, in the case where the MIMO scheme is used, the number of analog processors is equal to the product of R (ie, the number of RF channels) and A (ie, the number of antennas).

[0103] FIG. 5 is a block diagram illustrating an input Regarding FIG. 5, the input processor 110 includes a first stream multiplexer 111a, a first service splitter 113a, and a plurality of first constructors (115a, ..., 115m) of baseband (BB) frames. The input processor 110 includes a second stream multiplexer 111b, a second service splitter 113b, and a plurality of second constructors (115n, ..., 115p) of the baseband (BB) frames.

[0104] For example, the first stream multiplexer 111a receives several MPEG-2 transport streams (TSs), multiplexes the received MPEG-2 TS streams, and outputs the MPEG-2 TS multiplexed streams. The first service splitter 113a receives the multiplexed streams, splits the input streams of individual services, and sends the split streams. As described above, the first service splitter 113a separates the service,

Each PLP sends to encapsulation) a multiplexer that is to be transmitted a distributed service.

[0105] The first constructors (115a, ..., 115m) of the batch of data in the form of a specific frame. The first constructors (115a, ..., 115m) of the BB field. Header The synchron The synchron The synchron The synchron The synchron The synchron The synchron The. Synchronization the input streams.

[0106] The second stream multiplexer 111b has several streams, multiplexes input streams, and outputs the multiplexed streams. For example, the second stream multiplexer 111b may multiplex the Internet Protocol (IP) streams instead of the MPEG-2 TS streams. These streams may be encapsulated using a generic stream encapsulation (GSE - generic stream). The streams multiplexed by the second erythematous 111b may be any streams, thus, the above-described streams that differ TS is referred to as streams from MPEG-2 genre streams (GS streams).

[0107] The second service splitter 113b has the multiplexed generic streams, splits the received generic streams according to this individual services (ie, PLP types), and outputs the split GS streams.

[0108] The second constructors (115n, ie, create service data, have an individual). Frame format created by the second constructors (115n, .. ., 115p) of the frames the BB band may be

115p) BB band frames to be transmitted to

In the case of necessity, the format of the frame, 115p) frames, if necessary, is the format of the first constructors (115a, ..., 115m) of the BB bands. In the case of the constructors (115a, ..., 115m) of the BBs. The TS MPEG-2 Further stream includes the same Synchronization Word that is not included in the GS Stream gives ce the headers.

[0108] FIG. 6 is a block diagram illustrating the present invention. The coding and modulation unit includes a first interleaver 123, a second encoder 125, and a second interleaver 127.

[0110] The first encoder 121 acts as an outer coder of the input baseband frame, and is able to perform the error correction encoding. The first encoder 121 performer error correction using the Bose-ChaudhuriHocquenghem (BCH) scheme. The first interleaver 123 performs interleaving of the encoded data. The first interleaver 123 may not be included in the above-mentioned embodiment.

[0111] The second encoder 125 acts as an inner coder, and is able to perform the error correction encoding. As an error, correction coding scheme, a low density parity (LDPC) bit pattern can be used. The second interleaver 127 mixes the error-correction-coded data generated by the second encoder 125, and outputs the mixed data. First interleaver 123 and second element

The interleavers 127 are able to perform interleaving of data in bit units.

[0112] The coding and modulation unit 120 related to a single PLP stream. The PLP stream is error-correction-coded and modulated by the coding and modulation unit 120, and then transferred to the frame builder 130.

[0113] FIG. 7 is a block diagram illustrating a frame builder. Regarding FIG. 7, the frame builder 130, streams of individual paths from the coding and modulation unit 120, and arranges the received streams in a single signal frame. For example, the frame builder may include a first mapper 131a and a first time interleaver 132b in a second track 132b in a second path. The number of input streams is transmitted to each other by PLPs

PLP.

[0114] The first mapper 131a performs the mapping scheme. For example, the first element is mapped using a QAM scheme (eg, 16 QAM, 64 QAM, and 256 QAM). [0115] If the first mapper 131a performs mapping of the symbol, the input may be mapped systems. For example, the first mapper 131 a classifies input in a baseband frame unit and a baseband frame subunit. Individual classified data can be hybridized to symbols by at least two

53 QAM schemes (eg, 16 QAM and 64 QAM). Thus, data contained in a single symbol can be mapped in individual intervals.

[0116] The first time interleaver 132 a, the symbol of the sequence mapped by the first mapper 131 a, and is able to perform interleaving in the time domain. The first mapper 131 a cartridges are in the frame of the unit with the error correction received from the coding and modulation unit 120, into symbols. The first time interleaver 132 a, the symbol of the sequence mapped by the first mapper 131 a, and interleaves the received symbol sequence in the error correction unit units.

[0117] In this way, the p-th mapper 131p or p-th time interleaver 132p The service data is transmitted to the p-th PLP, maps the service data to symbols according to the p-th symbol mapping scheme. The mapped symbols can be interlaced in the time domain. It is a symbol of the first time interleaver 132 a and the first mapper 131 a.

[0118] The symbol of the mapping scheme of the first mapper 131 a may be equal to the p-th mapper 131 p. The first mapper 131a and the p-th mapper 131p are able to map input data to individual symbols using the same or different hybrid symbol mapping schemes.

[0119] Time data of interleavers placed in individual paths (ie, the data is interleaved by the first time interleaver.

53 / 55P29208 with RF channels.

received above the signal frame, and said p-th time interleaver, 132p) are interleaved, such that the RF channel is interleaved.

[0120] In connection with streams received in as many as PLS, the TFS frame builder 133 creates a TFS signal frame, as is the aforementioned signal frame, so that the service is shifted in time according to TFS Frame Constructor 133 allocates service bs.bn.nl.wikipedia.org.

[0121] The TFS frame builder 133 the first and the second remote signaling unit (denoted by the Ref / PL signal) 135, arranges the first and the second pilot signals in inserts the signaling signal (L1 and L2 ) of the physical layer in the second signal. remote. In this case, the first and the second pilot signals are signaled in each. The TFS signal frames received from the signaling information unit (Ref / PL signal) 135. As shown in FIG. 2, the first pilot signal may be a transmission type, and the second pilot signal may include a physical parameter and frame creation information. also,

[0122] The R number of frequency interleavers (137a, ..., 137r) interleave. The frequency interleavers (137a, ..., 137r) can interleave the OFDM symbol.

[0123] The service may be transmitted to a specific frequency domain.

[0124] FIG. 8 is a view of the mappers 131 a and 131 b perform hybrid symbol mapping. This Figure shows the number of bits transmitted by one subcarrier (cell) if the error is encoded and the error is corrected by the LDPC error correction coding mode.

[0125] For example, if the mappers 131a and 131b perform symbol mapping using 256QAM, 64800 bits are mapped to 8100 symbols. If the mappers 131a and 131b perform hybrid symbol mapping (Hyb 128-QAM) using 256QAM and 64QAM with a 3: 2 ratio, the number of symbol symbols mapped number of mapped symbols. The number of transmitted bits per subcarrier (cell) is 7.0588.

[0126] If a symbol mapping method of 64QAM is used, the input may be mapped to 10800 symbols and six bits per cell may be transmitted. If the data is mapped by 6480AM and 16QAM (64QAM: 16QAM = 3: 2, Hyb32-QAM), the five bits can be transmitted over one subcarrier (cell).

[0127] If the data is mapped to 1616AM symbols, the data is mapped to 16200 symbols, each of which is used to transmit four bits.

[0128] Similarly, 16QAM hybrid symbol mapping method and QPSK

256QAM is 4860 and 64QAM is 4320.

(16QAM: QPSK = 2: 3, Hyb8-QAM), three bits can be transmitted by one subcarrier (cell).

[0129] If the data is mapped to symbols by the QPSK method, the data may be mapped to 32400 symbols, each of which is used to transmit two bits.

[0130] FIG. 9 illustrates methods of mapping error-correction error symbols coding method (the length of the error-correction code is 16200 bits), which are equal to the symbol mapping methods of FIG. 8, and the number of bits per subcarrier according to the symbol mapping methods.

[0131] The number of bits transmitted by the subcarrier is equal to the normal mode (64800 bits) according to the symbol mapping methods such as 256QAM, Hyb 128-QAM, 64-QAM, Hyb 32-QAM, 16QAM, Hyb8 -QAM and QPSK, but the number of symbols is different from the normal mode. For example, 16200 bits are transmitted over 2025 symbols in 256QAM, 16200 bits are transmitted over 1215 symbols according to 256QAM and 1080 symbols according to 64QAM (total of 2,295 symbols) in Hyb 128-QAM.

[0132] Accordingly, the data rate per subcarrier (cell) for each PLP can be adjusted according to a hybrid symbol mapping method or a single symbol mapping method.

[0133] FIG. 10 is a view showing the number of symbols in the LDPC normal mode. If the TFS signal frame includes at least one RF channel, the symbols configuring the specific PLP may be uniformly allocated to the RF channels. Locations of PLP symbols allocated to RF channels can be more efficiently

53 / 55P29208PL. Addressed. Accordingly, when the signal receiving device selects the RF, the PLP can be reduced.

[0134] In this drawing, the symbol mapping method represented by 256-QAM indicates a method of mapping bits configuring a single block subjected to error

256QAM: 64QAM = 8: 1. According to the symbol mapping method, the number of bits in a single error, the coded block is the 256-QAM method is 57600, the number of bits in the single error 256-QAM method is 1200, the number of bits per cell is 8400, and the number of bits per cell word is 7.714285714.

[0135] The symbol mapping method represented by Hyb 128-QAM indicates a method of mapping bits configuring a single error correction encoded block into symbols with a coefficient of 256QAM: 64QAM = 8: 7. According to the Hyb 128-QAM symbol mapping method , the number of all symbols in the single error is coding block is 9600, and the number of bits per cell word is 6.75. [0136] According to the symbol mapping method represented by 64 QAM, the number of errors in the single error is coding block is 10800 and the number of bits per cell word is 6.

[0137] The symbol mapping method represented by Hyb 32-QAM indicates a method of mapping bits configuring a single error correction encoded block into symbols with a coefficient of 64QAM: 32QAM = 5: 4. According to the Hyb 32-QAM symbol mapping method , the number of all symbols in the error is 8,200 and the number of bits per cell word is 4.9090909. [0138] The symbol mapping method represented by 16 QAM indicates a configuration mapping method

A single error correction coded block to symbols with a 16QAM: QPSK = 1: 8 ratio. According to the 16 QAM mapping method, the number of symbols in one block is corrected for error 15600, and the number of bits per cell word is

4.153846154.

[0139] The symbol mapping method represented by Hyb 8-QAM indicates a method of mapping bits configuring a single error. According to the symbol-mapping method Hyb 8QAM, the number of symbols in the error is 21600, and the number of bits per cell word is 3.

[0140] According to the symbol, the mapping method is depicted by QPSK, the number of symbols in one error is 32400 and the number of bits per cell word is 2.

[0141] When symbols configuring the PLP are allocated to RF channels, the increase in the frequency domain of the RF. If the maximum of six is ​​the most common divisor of symbol numbers mapped to one error, the coded block is 1200. Accordingly, if the total multiple of 1200/60 = 20 symbols is allocated to each of the RF channels, the symbols can be homogeneously allocated to all RF channels. At this time, if 20 symbols are considered as a group, and the group is addressing the head of log2 (20) 4. 4.32 bits can be compared to the other.

[0142] FIG. 11 is a view of the symbol of the number of symbols according to the symbol mapping method

LDPC normal mode. In the example of the drawing, the 256-QAM method is used as the symbol mapping method using the 256QAM and 64QAM symbols (256QAM: 64QAM = 4: 1), the Hyb 128-QAM method using the 256QAM and 64QAM symbols (256QAM: _64QAM = 8: 7), 64QAM method, Hyb 32-QAM method using 64QAM and 8QAM symbols (64QAM: 8QAM = 3: 2), 16 QAM method using 16QAM and QPSK symbols (16QAM: QPSK = 1: 14), Hyb 8 -QAM method using 16QAM: QPSK = 2: 1 and the QPSK method. The largest common divisor (GCD) for the numbers of all error-correction-coded block symbols (normal mode) according to the symbol mapping methods is 720. Accordingly, if the total multiple of 12 (= 720/60) symbols is allocated to each of the RF channels can be homogeneously allocated to all RF channels. At this time, if the 12 symbols are considered as a group, the addressing overhead of log2 (12) ~ 3.58 bits can be compared to the other. The signal receiving device may collect the allocated PLP symbols.

[0143] FIG. 12 is a view of the mapping method in LDPC normal mode. In the example of the drawing, the scheme 256QAM, the Hyb 128-QAM scheme, the 64QAM scheme, the Hyb 32-QAM scheme, the QAM scheme 16, the Hyb 8-QAM scheme and the QPSK scheme were used as a symbol mapping method. The 256QAM symbol mapping method uses 256QAM and 64QAM symbols (256QAM: 64QAM = 44: 1) and the Hyb 128-QAM symbol mapping method uses the 256QAM and 64QAM symbols (256QAM: 64QAM = 28: 17). The Hyb 32-QAM method uses the 64QAM and 8QAM symbols (64QAM: 8QAM = 3: 2), the 16QAM symbol mapping method uses the 16QAM and QPSK symbols (16QAM: QPSK = 1: 14),

Hb 8-QAM symbol mapping uses the symbols 16QAM and QPSK (16QAM: QPSK = 2: 1). The GCD of the numbers of all error-correction-coded block symbols (normal mode) according to the symbol mapping methods is 240. Accordingly, if an integer multiple of 240/60 = 4 symbols are allocated to each of the RF channels, the symbols may be uniformly allocated to all RF channels. At this time, if the group is being addressed, it should be referred to as the group. Accordingly, even the number of PLP symbols may be homogeneously allocated to the RF channels.

[0144] FIG. 13 is a view showing the number of symbols in the LDPC short mode. As described above, the PLP symbols may be uniformly allocated to the RF channels and the PLP symbol addressing overhead can be reduced. The symbol mapping methods are depicted in this figure. 10. However, since the number of bits of the shortened LDPC mode is different from the number of bits of the normal mode, the GCD of the numbers of the error. is 300, differently than for FIG. 10. Accordingly, if the total multiple of symbols 300/60 = 5 is allocated to all RF channels. At the same time, if five symbols are considered, including the addressing overhead of log2 (5) bits reduced compared to the case. According

In other embodiments, the addressing bits are stored using log2 (5) bits when the divided PLP symbols are addressed.

[0145] FIG. 14 is a view of the LDPC short mode. The methods of mapping in FIG. 11. In this example, the GCD of the total number of error-coded block symbols (short mode) according to the symbol mapping methods is 180, which can be used to allocate . In this embodiment, the addressing bits are stored using log2 (3) bits.

[0146] FIG. 15 is a view showing another example of the number of symbols in the LDPC short mode. These symbols are mapping equal to those in FIG. 12. In this example, the GCD of the total number of error-coded block symbols (short mode), according to the symbol mapping methods is 60. In this embodiment, the addressing bits are stored using log2 (1) bits (ie the addressing bit is not saved).

[0147] FIG. 16 is a view of the symbol of mappers 131 a and 131 b shown in FIG. 7. Each of the symbol mappers 131a and 131b includes a first order mapper 1315a, second order mapper 131b, merger symbol 1317, and error correction block merger 1318.

[0148] The bit stream parser 1311 receives a PLP service stream from the coding and modulation of the received service stream.

[0149] The first order symbol mapper 1315 a maps symbol mapping method to symbols. Element

Order the second order symbols mapper 1315b maps mapping method to the symbols. For example, in the above example, the first order symbol, mapper 1315a may map the bit stream to symbols according to 256QAM and the second order symbol mapper 1315b may map the bit stream to symbols according to 64QAM. [0150] The symbol merger 1317 combines symbols output from the symbol mappers 1315a and 1315b is one symbol of stream and output symbol streams. The symbol combiner 1317 may send a stream of symbols in one PLP.

[0151] The error correction block merger 1318 may send one of the symbols stream connected by the symbol merger 1317 in the error correction coded unit unit. The error message block merger 1318 may be a block of the error error correction code coded for the TFS signal frame. The error correction block Merger 1318 may send a block symbol with error code error with error code coded block. For example, four blocks of error-coded block symbol symbols can be combined into one symbol block.

[0152] The error correction block Merger 1318 may split the symbol stream to the number of RF bands. If the maximum number is 5, the error block is a 13/16 symbol that can be divided by a total number of symbols. , 5 and 6.

[0153] The symbol contained in the output symbol block may be arranged to be homogeneously allocated to six RF bands. Accordingly, although the error mapping method is combined, the PLP configuration symbols are homogeneously allocated to the RF bands.

[0154] FIG. 17 is a view showing another shape of each symbol mapping member 131a and 131b. The embodiment of FIG. 16 except that it further includes a first power calibration unit 1316a and a second power calibration unit 1316b.

[0155] The first order power calibration unit 1316 a calibrates the power symbol of the mapped 1315a symbol according to the size of the constellation and sends the calibrated symbols. The second order power calibration unit 1316b calibrates the power of the symbols mapped by the second order mapper 1315b according to the size of the constellation and the symbols calibrated. Accordingly, although the symbol is mapping changes in one PLP or varies among the plurality of PLPs, if the symbol is a symbol of the mapping method.

[0156] The symbol merger 1317 combines the symbols calibrated by the power calibration units 1316a and 1316b and it is one symbol stream.

symbols sends a way [0157] FIG. 18 is a view showing another symbol of the symbol of mapper. In the embodiment of this Figure, the symbol mapper includes a second encoder 125 and a second interleaver 127 included in the coding and modulation unit. That is, if this embodiment is used, the coding and modulation unit

It may contain only the first encoder 121, the first interleaver 123 and the second encoder 125.

[0158] The embodiment of the symbol mapper 1311 includes a bit stream bitinter 1311a, the first order bit interleaver 1312b, the second order bit interleaver 1312b, the first order demux 1313a, the second order demux 1313b, and the first order symbol mapper 1315a, a symbol for mapper 1315b of the order and the element connecting 1317 symbols.

[0159] When the second encoder 125 performs the LDPC error correction coding block (eg, 64800 bits and 16200 bits in length) may vary according to the LDPC mode. If the bits are included in the error, the coded block is mapped to the error. For example, the cell word that is a symbol may be determined by the symbol of the error. Mapping is a symbol of the mapping method. lower order). If the error correction code is LDPC, the error error correction capability variation on the bits in the error. For example, the reliability of bits coded according to the matrix. H error in the irregular LDPC error correction coding method may vary according to the location of the bits. Accordingly, the row of bits configuring the word error in the error correction in the error adjusted. the correct answer can be found in the LDPC error correction coding method can vary according to the location of the bits. Accordingly, the row of bits configuring the word error in the error correction in the error. the correct answer can be found in the LDPC error correction coding method can vary according to the location of the bits. Accordingly, the row of bits configuring the word error in the error correction in the error adjusted.

[0160] First, the second encoder 125, eg performs error PLP using the LDPC error correction coding method.

[0161] The bit streamper 1311 receives a service stream in accordance with the PLP and splits the received service stream.

[0162] The interleaver interleaves the bits included in

1312a, first order bits, the first bitstream of the separated service streams. Similarly, the second order bit interleaver 1312b interleaves the bits included in the second bitstream of the separated service streams.

[0163] The first order bit interleaver 1312a and the interleaver correspond to the second

1312b, the second order bits may be an interleaver 127 used as an inner interleaver. Hereinafter, a method of interleaving the first order bit interleaver 1312b and the second order bit interleaver 1312b will be described.

[0164] The first order demux 1313a and the second order demux 1313b demultiplex the bits of the bit streams interleaved by the first order bit interleaver 1312b.

Demultiplexers 1313a

1313b divides the stream of input bits into the bit substreams that will be mapped on the real axis and the bit substream. the symbols map the axis of the imaginary constellation and send

The mappers 1315 a and 1315 b are the bit substreams demultiplexed by the demuxs 1313 a and 1313 b to the respective symbols.

[0165] The bit interleavers 1312a and 1312b and the demuxs 1313a and 1313b have the characteristics of the symbol mapping constellation according to the constellation. A detailed embodiment of the first order demux 1313a and 1313b will be described later.

[0166] The first order symbol mapper 1315 and performs the first order symbol mapping, eg, higher order symbol mapping, and the second order symbol mapper 1315b performing symbol mapping of the second order, eg, mapping the lower order symbols. The first order mapper 1315 and the symbol maps the sub-bit streams. 1300 the maps of 1313b maps the bitstreams out of the second order demuxs 1313b to the symbols. [0167] The symbol merger 1317 combines symbols mapped by the first order symbol symbol 1315a and the second order symbol mateator 1315b is one symbol stream and output a symbol stream.

[0168] As described above, in the LDPC, the error correction capability of the bits may be the error correction coded block. Accordingly, if the bit interleaver and the demultiplexer are controlled by the LDPC encoder 125, then the error correction capability at the level can be maximized.

[0169] FIG. 19 is a view showing another shape of each symbol mapping member 131a and 131b. The embodiment of FIG. 18 except for the first order power calibration unit 1316a and the second order power calibration unit 1316b are included in addition.

[0170] The first order power calibration unit 1316a calibrates the symbol of mapper 1315a according to the size of the constellation and sends the calibrated symbols. The second order power calibration unit 1316b calibrates the power of the symbols

They are represented by the second order symbol, manger 1315b, on the size of the constellation and send the calibrated symbols. Accordingly, although the symbol mapping scheme is changed in PLPs, it is a symbol of the power of the PLPs.

[0171] Symbol combiner 1317 combines symbols calibrated by power calibration units 1316a and 1316b and it is one symbol stream.

[0172] FIG. 20 is a view showing the idea of ​​interleaving bits by interleavers 1312a and 1312b of the bits of FIG. 18 and 19.

[0173] For example, the input bits are stored and read from a matrix-formed memory. The are When are When column When column When column When column When column When column When column When column When column. When the stored bits are read, the bits are read in the first row. In other words, when bits are stored, the bits are stored in rows. And when the stored bits are read, they must be stored in a row. In this figure,

[0174] In order to mapping the error-correction-coded bits, the LDPC and the error-correction block 1316a and 1312b can change the number of rows and

53/55 memory columns according to the type of the symbol mappers 1315a and 1315b.

[0175] Fig. 21 is a view of the 1322a and 1312b types of the 1322a and 1315b, and the LDPC mode is the normal mode.

[0176] For example, if the symbol mapper 1315 a maps the bits is 256QAM symbols, the first order interleaver 1312 and interleaves the bits by a memory having 8100 rows of columns.

If the symbols are represented by 64QAM, the first order interleaver 1312a interleaves the bits of the memory having 10800 rows and 6 columns. If the symbols are mapped by 16QAM, the first order interleaver 1312a interleaves the bits of the memory having 16200 rows and 4 columns.

[0177] For example, if the symbol mappers 1315a and 1315b map the bits to the Hyb128-QAM symbols, the first order interleaver and the first order interleaver 1312a interleaves the bits using a memory of 4860 rows and 8 columns, the second order interleaver 1312b interleaves the bits using memory 4320 rows and 6 columns.

Similarly, if the symbol mappers 1315a map symbols using Hyb 32-QAM, the first order interleaver 1312a interleaves the bits by using 6480 rows and 6 columns, the second order interleaver 1312b interleaves the bits using a memory having 6,480 rows and 4 columns.

[0179] Fig. 22 is a view of the 1322a and 1312b types of the 1322a and 1315b, and the LDPC mode is the short mode.

[0180] For example, if the symbol mapper 1315a maps the bits is 256QAM symbols, the first order interleaver 1312a interleaves the bits by memory

53 / 55P29208 having 2025 rows and 8 columns. If the symbol mappers 1315a and 1315b map symbols using Hyb128QAM, the first order interleaver 1312a interleaves the bits using the memory of 1215 rows and 8 columns, and the second order interleaver 1312b interleaves the bits using a memory having 1080 rows and 6 columns.

[0181] If bit is interleaving, it is performed with the error, the coded block may be changed.

[0182] FIG. FIG. 23 is a diagram showing the idea of ​​an interleaving a bit interleaver. In the embodiment of the bits are stored in the column. When the recorded bits are read, bits from the cyclic shifted locations are read in the row direction. In each row, bits written in each row are cyclically shifted. If the bits are written, the cyclic shifting method is a twisted bit-interleaving. Embodiment This embodiment This embodiment This using This using This using This using This using This using This.

[0183] In this embodiment, N denotes the length of the error. When the bits are written in the first column (represented by shading) in the order 1, 2, 3, 4, ..., and C and the rings in the second column in the order C + 1, C + 2, C +3, ....

(X1 is bit in. Bits are read. [0184] The recorded bits are twisted in the column direction by column.

[0185] If the recorded bits are read, the twisted bits are read in the direction. For example, in this embodiment, the first row of the order 1, C + 1, ... and the bits are in the order of X1, 2, C + 2, first column of the second row) row by row and cyclically moved bits are read. Of course, instead of shifting the stored bits in the memory. [0186] FIG. 24 is a view showing another embodiment of bit interleaving. In this embodiment, N denotes the length of error. When the bits are written, the bits are written in the first column 1, 2, 3, 4, ..., C-1, and C and the bits are written in the second column in order

C + 1, C + 2, C + 3, ....

[0187] The recorded bits are double-twisted in a row two columns through two columns. If the recorded bits are read, bits moved cyclically in a row. This method can be called the method of double-twisted bit interleaving.

[0188] FIG. 25 is a view showing another embodiment of bit interleaving. In this embodiment, N denotes the length of error. The bits are written in the first column in the order 1, 2, 3, 4, ..., C-1, and C and the column in the order C + 1, C + 2, C + 3, ....

[0189] When the recorded bits are read in the first region, the bits may be read using the bit interleaved twisted method.

[0190] In the second region of the lines, the bits can be read by the double-twisted method of interleaving.

[0191] In the third region of the rows, the bits can be read by the twisted bit interleaving method. [0192] If the bits are interleaved, the bits in the error, the coding block may be mixed more randomly.

[0193] FIG. 26 is a view showing the idea of ​​multiplexing input bits of demuxs 1313a and

1313b.

[0194] The bit interleavers 1312a and 1312b interleave the input bits x0, x1, ..., and xn-1 and output the interleaved bits. The interleaving method is already described above.

[0195] The demux 1313a and 1313b demultiplex the interleaved bit streams. The demultiplexing method may vary according to the error. The coding method is the mapping method of the symbol mapper. If the symbol method of the symbol of mapper is QPSK, the input bits, for example, are interleaved into the two sub- streams and the symbol of mapper maps. the constellation. For example, the first bit y0 of the demultiplexed first sub stream corresponds to the real axis and the first bit of the second sub stream corresponds to the imaginary axis.

[0196] If the symbol method of the symbol mapper is 16QAM, the input bits, for example, are demultiplexed to four subframes. The symbol of mapper selects the bits in the four subdivisions.

[0197] For example, the bits y0 and y2 of the demultiplexed first and third sub streams correspond to the real axis, and the bits y1 and y3 of the demultiplexed second and fourth sub streams correspond to the imaginary axis.

[0198] Similarly, if the symbol method of the symbol mapper is 64QAM, the input bits may be demultiplexed to six bit streams. The symbol mapper maps six sub-streams to symbols. For example, the demultiplexed first, third and fifth sub streams of bits y0, y2 and y4 corresponds to the real axis, and the demultiplexed second, fourth and sixth sub streams bits y1, y3 and y6 correspond to the imaginary axis.

[0199] Similarly, if the symbol method of the symbol mapper is 256QAM, the input bits may be demultiplexed to eight strats of bit rates. The symbol mapper maps eight sub-streams to symbols. For example, first, the demultiplexed first, third, fifth and seventh substreams bits y0, y2, y4 and y6 corresponds to the real axis, and the demultiplexed second, fourth, sixth and eighth sub streams bits y1, y3, y6 and y7 to the imaginary axis.

[0200] If the symbol mapper maps the symbols, the sub streams are demultiplexed by the demux.

[0201] The bit-interleaving method described above, the demultiplexing method, and the symbol mapping method are exemplary, and can be used as a method of selecting the sub-patterns of demultiplexing by the demux may correspond to the real axis and the imaginary axis of the constellation.

[0202] The cell word mapped to symbols may vary according to the error bitstream according to the coding efficiency, the method of interleaving the bit streams, the demultiplexing method, and the symbol mapping method. The MSB of the cell word correction. The codebase of the error in the MSB.

[0203]

Accordingly, although the correct symbol is used in the irregular way, the LDPC method, the error is the mapping of the system performance.

[0204] FIG. 27 is a view of the demultiplexer.

[0205] If the symbol mapping method is QPSK, two bits are mapped to one symbol and the two bits of one symbol are in the order of the bit indexes (indexes 0 and 1 of b).

[0206] If the symbol mapping method is 16QAM, 4 bits are mapped to one symbol and four bits of one symbol are demultiplexed according to the result of modulo-4 bit index calculations (indexes 0, 1, 2 and 3 from) .

[0207] If the symbol mapping method is 64QAM, 6 bits are mapped to one symbol and six bits of one symbol unit are demultiplexed according to the result of modulo-6 bit indices calculation (indexes 0, 1, 2, 3, 4 and 5 zb).

the bit can be efficiently mapped and can be adjusted

[0208] If the symbol mapping method is 256QAM, 8 bits are mapped to one symbol and eight bits of one symbol unit are demultiplexed according to the modulo-8 bit index calculations (indexes 0, 1, 2, 3, 4 , 5, 6 and 7 zb).

[0209] The order of demultiplexing the sub-jets is exemplary and can be modified.

[0210] FIG. 28 is a view showing an example of a demultiplexing type according to a a symbol mapping method. The symbol mapping method includes QPSK, 16QAM, 64QAM and 256QAM, and the demultiplexing type includes types 1-8.

[0211] The first type of subscribers (0, 2, 4, 8, ...) (or the real axis of the constellation) and successively corresponds to the indexes with the odd numbers (1, 3, 5, 7, ...) (or the imaginary axis of the constellation). Hereinafter, bit-demultiplexing of the first type may be represented by the demultiplexing identifier (binary 1010, location 1 is the MSB location.

[0212] The second type of example, ie, the LSB input bits successively correspond to the even numbered indices (6, 4, 2, 0) (or the real axis of the constellation) and the odd number index (1, 3, 5, 7, ...) (or the imaginary axis of the constellation). Thereafter, the demultiplexing of the second type of bits may be represented by the demultiplexing identifier (binary number 0101).

[0213] The third type is an example of the bits of codeword become the MSB. The input bits are rearranged so they can fill the code word. Thereafter, bit-type demultiplexing of the third type may be

53 / 55P depicted by the demultiplexing identifier 9 (a binary number of 1001).

[0214] A compact type is an alternative for MSB values. Bit bit bit bit bit bit bit bit The The The The The The The The The The The The. Thereafter, the demultiplexing of the fourth type of bits may be represented by the demultiplexing identifier 6 (the binary number equals

0110).

[0215] The bits are demodiplexed so that the last codeword bit takes the MSB values ​​and the first bit takes the first bit of the codeword takes on; MSB values, and its last bit takes LSB values. Thereafter, the demultiplexing of bits of the fifth type may be represented by the demultiplexing identifier 12 (a binary number of 1100).

[0216] As described above, the demultiplexing type may vary according to the symbol correction coding method. That is, a different type of demultiplexing can be used for the mapping method or coding efficiency changes.

[0217] FIG. 29 is a view showing an embodiment of demultiplexing type. This generation may include bit interleavers 1312a and 1312b, demux 1313a and 1313b and mappers 1315a and 1315b.

[0218] The bit interleavers 1312a and 1312b interleave the PLP service streams with encoded error correction. For example, the bit interleavers 1312a and 1312b may perform a bit interleaving in the error correction coding units according to the error correction coding mode. The bit interleaving method is already described above.

[0219] The demux 1313a and 1313b may comprise the first type of demodiplexer 1313a1 and 1313b1, ..., and the nth type demodiplexer 1313a2 and 1313b2. In this case, n is an integer. The methods of bit demultiplexing with types of demultiplexers in accordance with FIG. 17. For example, the first type demuxs may correspond to the first type bit demultiplexing (1100) and the second type demultiplexers (not shown) may correspond to bit demultiplexing (0011) Demultiplexer 1313b the nth type input bit stream to the nth type bits (eg. identifier and sends the demultiplexed stream and 1313b3 receive the second type of signal signal demultiplexes multiplexing 1100 bit demultiplexing. Selectorors 1313a3 of a demultiplexing type demultiplexer suitable for input bits and output a demultiplexed bit stream and the demultiplexer selection signal. The demultiplexer selection signal may have the error mapping method of the constellation. Accordingly, the demodiplexing type can be described in accordance with the coding mode of the mapping method. The demultiplexer selection signal may have the error mapping method of the constellation. Accordingly, the demodiplexing type mapping the method of the mapping method of the mapping and the error. The demultiplexer selection signal may have the error mapping method of the constellation. Accordingly, the demodiplexing type can be described in accordance with the coding mode of the mapping method.

error correction and / or constellation. Detailed

[0220] The mappers 1315a and 1315b may map the demultiplexed sub-beams to symbols according to a a symbol selection signal.

[0221] FIG. Demultiplexing, the efficiency of symbol mapping coding.

[0222] In the demultiplexer, it presents and is a mapped view showing the type determined by the error correction method of the 4QAM symbol mapping method, coding method of the error correction coding method.

LDPC is any from, 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10, stream bits can be demultiplexed according to all types of demultiplexing (denoted by all).

16QAM symbol mapping, if the error correction of the LDPC error correction, the coding method is 1/4, 1/3, 2/5 and 1/2, the symbols can be mapped without the bit-interleaving and bit de-multiplexing (denoted by No-Int and NoDemux). If the error is coding is 3/5, the bit may be demultiplexed by any of the 10 and 12 demultiplexing. If the error correction is 2/3, 3/4, 4/5, [0223] In the method of coding efficiency of the identifiers 9, the coding efficiency

5/6, 8/9 and 9/10, demultiplexed demultiplexing. [0224] In the method, the stream of input bits can be according to the identifier 6

64QAM symbol mapping, if the error correction, LDPC encoding efficiency is 1/4, 1/3, 2/5 and 1/2, the symbols can be mapped without performing bit-interleaving and bit demultiplexing. If the coding efficiency is 3/5, the bits may be demultiplexed according to any of the demultiplexing identifiers 9 and 10. If the coding efficiency is 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10, bits can be

53, which is demultiplexed according to the demultiplexing identifier 6.

[0225] In the 256QAM symbol mapping method, if the error correction, LDPC encoding efficiency is 1/4, 1/3, 2/5 and 1/2, the symbols may be mapped without interleaving and bit demultiplexing. If the coding efficiency is 3/5, the bits may be demultiplexed according to the demultiplexing identifier 9. If the coding efficiency is 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10, the bits can be demultiplexed according to the demultiplexing identifier 6.

[0226] As described above, the type of bit demultiplexing may vary according to code of the code. Accordingly, the error correction can be adjusted by mapping the demultiplexed sub-streams to symbols. Accordingly, it is possible to optimize the resistance in the bit level.

[0227] FIG. 31 is a view of the demultiplexing method by the equation. For example, if the symbol mapping method is QPSK, the input bits (xi xN / 2 + and correspond to the demultiplexed bits y0 and y1. If the symbol mapping method is 16QAM, the input bits^x2 N ^{, x}3 N ^{, x}1 ^{, x}n - + and 4 7 corresponds to the demultiplexed bits y0, 4 4 4 y1, y2 and y3.

[0228] If the symbol mapping method is 64QAM, the input bits ^x4N ^{, x}5N ^{, x}2N ^{, x}3N ^x1^{, x}N

- + 1 - + 1 - + 1 - + 1 - + 1

V 6 6 6 6 6 7 the demultiplexed bits y0, y1, y2, y3, y4 the symbol mapping method is 256QAM, responds and y5. Hedge bits

53 / 55P29208PL00 ^x6N ^{, x}7N ^{, x}4N ^{, x}5N ^{, x}2N ^x3N ^xand^{, x}N + i + i + and correspond to the demultiplexed bits y0, y1, y2, y3, y4, y5, y6 and y7.

[0229] In this case, N is the number of bits in the symbol of the bit interleaver.

[0230] FIG. 32 is a view of the mapping a symbol by a symbol mapper. For example, in the QPSK symbol mapping method, the symbols on the constellation corresponds to the bit value y0 of the demultiplexed first sub stream.

[0231] In 16QAM, bits of the demodiplexed and third sub-streams (bits separated from the MSB locations by 0 and 2) and its imaginary axis corresponds to the bits of the demultiplexed second and fourth sub streams (bits separated from the MSB location by 1 and 3).

[0232] In 64QAM, the real axis of the constitution corresponds to the bits of the demultiplexed first, third and fifth sub streams (bits separated from the MSB location by 0, 2 and 4) and its imaginary axis corresponds to the bits of the demultiplexed second, fourth and sixth sub streams (bits separated from the location of the MSB by 1, 3 and 5).

[0233] Accordingly, the symbol config bits may be mapped to the cell in the demultiplexing order. If the bits are configuring the cell word are demultiplexed, MSB and LSB, the LDPC encoded error bits varies according to the locations.

[0234] FIG. 33 is a block diagram illustrating a MIMO / MISO encoder according to an embodiment of the invention. The MIMO / MISO encoder input from

And profitable gain using the MIMO / MISO encoding scheme, and sending coded data to individual paths. If the end device receives the signal, it is able to obtain a gain (also a multiplexing).

[0235] The MIMO / MISO encoder 140 encodes are in the form of an encoder.

[0236] FIG. 34 is a block diagram illustrating a modulator. The modulator comprises a first power controller (PAPR Reduce1) 151, a time-domain transform unit (IFFT) 153, and a second power controller (PAPR Reduce2) 157, and a guard-interval inserter 159.

[0237] The first power controller 151 reduces the PAPR (average to peak power ratio).

[0238] The time-domain transform (IFFT) unit 153 converts the received frequency-domain signals into time-domain signals. For example, signals in the field are converted to IFFT algorithm. Thus, the data can be modulated according to the OFDM scheme.

[0239] The second power controller (PAPR Reduce2) 157 reduces the PAPR (Peak-to-Average Power Ratio). In this case, a tone reserved scheme can be used, as well as an active constellation extension (ACE) for extending the symbol constellation.

Frequencies can be a time domain according to

[0240] The guard-interval inserter 159 OFDM symbol, and the result of the inserted result. As described above, the aforementioned exercise may be performed in the R signal.

[0241] FIG. 35 is a block diagram illustrating an analog cpu 160 in accordance with the present invention. The analog processor 160 includes a digital-to-analog converter (DAC) 161, an upstream frequency conversion unit 163, and an analog filter 165. [0242] The DAC 161 converts the input to an analog signal, and an analog signal . The uplink frequency conversion unit 163 converts the frequency domain to the RF region. The analog filter 165 filters the signal in the RF area, a filtered RF signal.

[0242] FIG. 36 is a block diagram of the device for receiving a signal. The second signal receiver 210n, the first demodulator 220a, an nth demodulator 220n, a MIMO / MISO decoder 230, a frame parser 240, and a decoding demodulator 250, and an output processor 260.

[0244] In the case where the signal is received by the TFS signal frame, individual services are multiplexed to R channels, and then they are time shifted.

[0245] The receiver may receive at least one RF receiving signal. The TFS signal frame transmitted to the R number (where R is the natural number). A by the number of antennas. A Antenas have been used for R RF, the total number of antennas is R x A.

[0246] The first signal receiver 210a is able to select one of the various RF channels. For example, the first signal receiver can receive a signal from MIMO / MISO scheme through different paths.

[0247] The first signal receiver 210a, and the n-th signal receiver 210n can receive several number of RF channels, as a single PLP. Namely, this embodiment presents the signal of receiving the RF number. Thus, if this the same as a single RF channel, only the first receiver 210a i need it.

[0248] The first demodulator 220a and the n-th demodulator 220n receive the first and the n-th signal receivers 210a and 210n according to the OFDM scheme, and output the demodulated signals.

[0249] The MIMO / MISO decoder 230 decodes service data received via a different transmission path. If this is the number of people who want to use the MIMO / MISO decoder, they may have the same number of services. (R x A) of the number. The number of receipts.

[0250] The frame parser 240 parses the TFS signal frame, and the parsed service data.

[0251] The decoding demodulator 250 performs error error in the analysis of data in the analysis of data.

[0252] Output processor 260 decodes a stream, including reverse-mapped bit data, and outputs a decoded stream.

[0253] In the above-mentioned description, each frame parser 240, and a decoding demodulator 250, and the output processor 260 receive different service. [0254] FIG. 37 is a block diagram illustrating a signal receiver. The signal receiver may include a tuner 211, and down frequency converter 213, and an analog-digital converter (ADC) 215.

[0255] Tuner 211 performs hopping of some RF channels, RFPs, RFPs, RFPs, RFPs, RFPs, RFPs The tuner 211 performs hopping of the RF channels in the TFS signal frame. If the signal is transmitted, the tuner is 215 performs tuning to the corresponding RF channel, and the receipt of signals via the number of antennas.

[0256] The down-conversion frequency converter 213 performs down-conversion of the RF frequency band tuned by the tuner 211, and outputs the frequency down-conversion result. ADC 215 converts the analog signal to a digital signal.

[0257] FIG. 38 is a block diagram illustrating a demodulator. The demodulator includes a frame detector 221, a frame synchronization unit 222, a safety component deleting 223, a frequency transforming unit 224 (FFT), channel estimator 225, channel equalizer 226, and signaling information extractor 227.

[0258] If the demodulator obtains service transmitted to a single PLP stream, the next demodulation of the signal will be performed. A detailed description will be presented below.

[0259] The frame detector 221 identifies the reception signal reception system. For example, the frame detector 221 determines whether the signal is a DVB-TS signal or not. And, the frame detector 221 may also determine whether the signal is TFS signal frame or not. The frame synchronization unit 222 obtains synchronization in the TFS signal frame.

[0260] The guide interval controller 223 removes a guard interval between OFDM symbols from the time domain. The frequency domain converter (FFT) 224 converts the reception signal to the frequency domain.

[0261] The channel estimator 225 performs the transmission of the symbol of the frequency domain. The channel equalizer 226 performs the channel estimation 225.

[0262] The signaling information extractor 227 may obtain signaling information of the physical layer determined in

The first and second pilot signal in the channel equalizer receiving data.

[0263] FIG. 39 is a block diagram illustrating a MIMO / MISO decoder in accordance with the present invention. The signal receiver and the demodulator are intended for the signal received in a single track. If the signal receiver and the demodulator receive service, the MCP / MIMO decoder 230 sends a signal in a different way. single PLP. Thus, the MIMO / MISO decoder 230 may obtain a PLP.

[0264] The MIMO / MISO decoder 230 receives a multi-path transmission signal from several antennae, and is able to decode a signal using a single signal. Otherwise, the MIMO / MISO decoder 230 is able to recover a signal using a multi-path transmission signal.

[0265] Therefore, if the signal is transmitted via the R number of RF channels (where R is a natural number), the MIMO / MISO decoder can be received via the RF channel. If the value is "1", the signals can be decoded using the MISO scheme. If the value is greater than "1", the signals can be decoded using the MIMO scheme.

[0266] FIG. 40 is a block diagram illustrating a frame parser. The frame parser includes a first frequency de-interleaver 241a, an r-th frequency 241r interleaver, and 243 frame parser, and first

A time interleaver 245a, a p-time time interleaver 245p, and first symbol demapper 247a, and a p-th symbol demapper. The value "r" can be determined by the number of streams transmitting PLP service data generated from the frame parser 243.

[0267] Therefore, if the number of services is transmitted to the number of the RF, the frame parser consists of the frequency interleavers.

<td>conversely, the number p</td><td>time</td><td>items</td><td colspan="2">Interweaving</td>

<td>inversely, and the number p</td><td>items</td><td colspan="2">mapping</td><td>vice versa</td>

<td>symbols.</td><td></td><td></td><td></td><td></td>

<td>[0268] Together with</td><td>first</td><td>channel</td><td>RF</td><td>first</td>

<td colspan="3">frequency interleaver</td><td>241</td><td>performs</td>

<td>reverse interleaving</td><td>date</td><td>input</td><td>in</td><td>the field</td>

frequency, and sends the result of reverse de-interleaving.

[0269] The frame parser 243 parses the TFS signal frame transmitted to the different RF channels including the desired service. The frame parser 243 parses the TFS signal frame to receive the specified service. PLS service data of the first track.

[0270] The first time de-interleaver 245a performs de-interleaving of the first-path PLP service data in the time domain. The symbol of demapper 247a the first symbol specifies the service of the PLP of the first track.

[0271] Provided that the symbol is a symbol of the symbol of the symbol of demappers, the symbol of demappers, the symbol of demapper symbol data using different diagrams.

[0272] FIG.

view of demappers 247a and 247p. The symbol demapper receives the streams corresponding to the PLPs from the time interleavers 245a and 245p correspondingly to the symbol demappers.

[0273] Each symbol of demapper 247a may include a block splitter 2471 and error correction 247p, and symbol splitter 2473, and first order inverse 2475 a, and second order inverter 2475b, and a bit stream element.

[0274] Distribution block splitter 2471 separating the mapping illustrator flux of 2478 can correspondingly received

2471 of the PLP block of the time interleavers 245a and 245p in the error correction block units. The error correction block splitter 2471 can split the service stream into a normal mode LDPC block unit. In this case, the service stream may be divided into a block of binary code (block of 1620 bits) having a length of 64800 bits).

[0275] The symbol splitter 2473 may split the symbol stream in the error error.

[0276] For example, the first order demapper 2475 and transforms the symbols according to a higher order bit mapping method. The second order of demapper 2475b converts the symbols to the lower order symbol mapping method into bits.

[0277] The bit stream merger 2478 may receive the converted bits and output one bit stream.

[0278] FIG. 42 is a view showing the other symbol of demapper 247a and 247p. The embodiment of FIG. 41 except that it has the first power unit calibration 2474a and a second power calibration unit 2474b.

[0279] The first order of the power calibration unit 2474a receives symbols separated by the symbol splitter 2473, calibrates the power of the received symbols. The symbol of mapping methods may have the power of calibrated. The first order power calibration unit 2474a converts the power of the constellation symbol. The first order demapper 2475 a may mirrors the power of calibration, it is bits.

[0280] Similarly, the second order power calibration unit 2474b symbols are separated by the symbol splitter 2473, modified to calibrate the power of the received symbols, and follow the modified symbols.

[0281] FIG. 43 is a view showing another symbol of demappers 247a and 247p. Each of the inverse 247a and

53 / 55P29208PL00

247p symbols may include a symbol splitter 2473, an element combining the embodiment 2478, an example of a second order into bits. On the first order mapparding 2474a, the second order demapper 2474a, the first order mux 2475a, the second order mux 2475b, the first order bit interleaver 2476a, the second order bit interleaver 2476b and the bit stream dividers. In this embodiment of the decoding and demodulation unit of FIG. 33 includes a first decoder 253, a first de-interleaver 255, and a second decoder 257.

[0282] The symbol splitter 2473 may split the symbol stream of the PLP according to a method corresponding to the symbol mapping method.

[0283] The first order demapper 2474a and the reverse-mapper 2474b convert the split symbol stream of the example, the first order demapper 2474 a performs higher order symbol demapping QAM and the second order inverse demapper 2474b performs down symbol demapping of the lower order symbols QAM. For example, the first order demapper 2474 a may perform the 256QAM symbol demapper and the second order demapper 2474b may perform the 64QAM symbol inverse mapping.

[0284] The first order mux 2475 a and the second order mux 2475b multiplex the symbol-mapped bits. The multiplexing methods may correspond to the demultiplexing methods described with reference to FIG. from 15 to 18. Accordingly, the demultiplexed sub streams can be converted to one bit stream.

[0285] The first order bit deinterleaver 2476a deinterleaves the bit streams multiplexed by the first order mux 2475 a

Element

The second order bit interleaver 2476b deinterleaves the multiplexer bits multiplexed by the first order mux 2475 a. The inverse deinterleaving method corresponds to the bit interleaving method. A bit interleaving method is shown in FIG. 12.

[0286] The bit stream merger 2478 may combine bit-streams de-interleaved by the bit interleavers 2476a and 2476b to one bit stream.

[0287] The first decoder 253 of the decoding and the code decoder.

[0288] FIG. 44 is a view showing the other symbol of demapper 247a and 247p. The embodiment of FIG. 43 except that it has the first power unit calibration 2474a and a second power calibration unit 2474b. The first order power calibration unit 2474a and the second order power calibration unit 2474b modify the calibrated symbol of the symbol demappers 2475 a and 2475 b.

[0289] FIG. 45 is a view of the multiplexing of the demultiplexed sub stream. In this embodiment, the reverse mappers 2474a and 2474b select the bits of cells that contain the bits.

words

Multiplexers 2475a and cells in accordance with the selected multiplexer

2475b multiplex the selection signal

The demoticers 2475a2 and 2475b2 to the nth muxs 2475a3 and 2475b3. The demultiplexed cell words are sent to the first multiplexers.

[0290] The first muxs 2475a2 and 2475b2 to the nth muxs 2475a3

2475b3 change the order of bits in

The input signal of the cell words to the mux selection signal. The mux selection signal may be changed in accordance with the error correction code coding or the symbol mapping method. In order to generate a stream and bit streams, it must change in accordance with the mux selection signal.

[0291] The first demultiplexers 2475a1 and 2475b1 output the symbol-demapped bit streams to the first multiplexers 2475a2 and 2475b2 to the nth muxs 2475a3 and 2475b3 according to the mux selection signal. The first sub-multiplexers 2475a1 and 2475b1 can receive the multiplexer 2475a2 and 2475b2 sub-multiplexer through n and 2475a3 and 2475b3 and send one stream to the mux selection signal.

[0292] The bits are provided to the bit interleavers 2476a and 2476b, and the de-interleaving elements 2476a and 2476b alternate the input bits inversely and output the bit-interleaved bits.

[0293] FIG. 46 is a block diagram illustrating a decoding demodulator. The decoding demodulator may comprise individual function blocks. In this embodiment, the decoding demodulator of FIG. 16 may include a first de-interleaver 251, a first decoder 253, a second de-interleaver 255, and a second decoder 257. The second de-interleaver 255 may be selectively included in the decoding demodulator.

[0294] The first de-interleaver 251 acts as an inner de-interleaver, and is able to perform de-interleaving of the p-th PLP stream generated from the frame parser.

[0295] The first decoder 253 acts as an inner decoder, can perform error.

[0296] The second de-interleaver 255 acts as an external interleaver, and can perform de-interleaving of the error-correction-coded data. [0297] The second decoder 257 acts as an outer decoder. The data de-interleaved by the first deceiver 253 are again subjected to error correction, so that the second decoder 257 sends the error-corrected data. The second decoder 257 decodes the error using the error.

[0298] The first de-interleaver 251 and the second de-interleaver 255 are able to convert the PLP stream into a random error. The first decoder 253 and the second decoder 257 can correct the errors.

[0299] The decoding demodulator shows the operation of a single PLP stream. If there are a number of p streams, the number of p decoding is required, or the decoding can repeatedly decode the input data times.

[0300] FIG. 47 is a block diagram illustrating an output. The output processor may include a number of parsers (251a, ..., 261p) of the baseband (BB), linking element 263a, first service, linking element 263b of the second service, first demultiplexer 265a, and second demultiplexer 265b.

[0301] Parsers (261a, ..., 261p) of BB frame BB remove BB frame headers from PLP, PLP paths, and output the deleted result. This embodiment shows at least two streams. The first stream is an MPEG-2 TS stream, and the second stream is a GS stream.

[0302] The first service combiner 263a calculates the sum of the data in the payload of a single service stream. The first demultiplexer 255a may demultiplex the service stream, and send the demultiplexed result.

[0303] In this way, the second service combiner 263b calculates the payload of the other one. The second demultiplexer 255b may demultiplex the GS format service stream, and output the demultiplexed service stream.

[0304]

FIG.

is a block diagram illustrating a multiplexed transmitting apparatus. The transmitter 400 encoders, and a transmitter 400. The transmitter 400 encodes or modulates a signal.

[0305] The service inventor 310 Receive different service streams, different service streams to be addressed to individual RF channels, send the multiplexed service streams. The creator of the service

400 transmits the PLP through various RF channels. By using this scheduling information, the service creator 310 modulates various frames

The services that are to be transmitted to other RF channels by the transmitter 400, and transmit the modulated service frames. [0306] The frequency splitter is a part of the streams, and it can be transmitted to each other.

[0307] The transmitter 400 streams to be transmitted to individual frequency bands. For example, in connection with a particular service, the first mapper 410 maps the input service. The first interleaver 420 interleaves the mapped symbols to prevent a burst error.

[0308] The first symbol embedding member may be a pilot signal (eg, a remote control signal) in the modulated signal.

[0309] The first modulator 440 modulates data interleaved by the signal modulation scheme. For example, the first modulator 440 can modulate signals using the OFDM scheme.

[0310] The first pilot symbol, inserter 450, inserts the first remote control signal, and is able to transmit the signal frame

TFS.

[0311] Service stream data transmitted to the second RF channel is transmitted to the TFS signal frame via several blocks 415, 425, 435, 445, and 455 of the FIG. 18.

[0312] The number of signal processing transmitted may be equal to the number of RF channels contained in the TFS signal frame.

[0313] The first mapper 410 and the second mapper may respectively include the demultiplexers 1313a and 1313b, and allow to change the MSB and LSB locations in the wordmarked cell word.

[0314] FIG. 49 is a block diagram illustrating an apparatus for receiving a signal. The signal reception apparatus 510, a synchronizing unit 520, a mode detector 530, an equalizer 540, a parameter detector 550, a de-interleaver 560, a demapper 570, and a service decoder 580.

[0315] The reception unit is able to receive signals from the RF. If the signal frame includes a different RF channels, the receiving unit. 500 performs hopping of the various.

[0316] The synchronization unit 510 obtains synchronization of the signal, and sends a synchronized reception signal. The demodulator 520 is able to demodulate the signal with the obtained synchronization. Mode detector 530 can obtain an FFT mode (eg, 2k, 4k, 8k FFT operational length) of the second pilot signal using the first pilot signal of the signal frame.

[0317] The demodulator 520 demodulates the FFT signal of the second pilot signal. Equalizer 540 performs a channel estimation of the signal signal, and sends a signal of the channel estimate obtained. The de-interleaver 560 interleaves the reception signal with channel alignment. The demapper 570 maps the inversely interleaved symbol using a symbol mapping scheme corresponding to

A symbol for mapping a transmission signal symbol (eg, QAM).

[0318] The parameter detector 550. obtains information about a physical parameter (eg, Layer-1 (L1) information) included in the second pilot signal from the signal equalizer 540, and transmits the acquired physical parameter the synchronization unit 510. The receiving unit 500 is able to change.

[0319] The detector detector 550, and the encoded service data. [0320] The mapping dematernator 570 may comprise multiplexers 2475a and 2475b and bits for the MSB and LSB locations error correction coding and the symbol mapping method.

[0321] Hereinafter, a method for modulating the first pilot signal of a modular first pilot signal will be described.

[0322] The temporarily interleaved PLP symbols are transmitted by regions. The temporally interleaved PLP symbols may be divided into multiple RF bands exist. Accordingly, if the PLP is transmitted or received, and diversification gain can be obtained. The error correction mode and the symbol of the mapping method may be changed in the service.

[0323] A first pilot signal and a remote control signal.

[0324] As described above, the first pilot signal in the frame, the signal from the above-described structure. The first pilot signal may be transmitted through the first pilot signal. The FFT mode of the data symbol.

[0325] FIG. 50 is a view of the first pilot signal. The A remote control signal. B denotes the same cyclic prefix as the first part of part. The first part may be reproduced from the first half of part

[0326] B and C may be reproduced the duplicated portions. The relationship between B or C and A is as follows.

[Equation 1]

B = onepart (A) · e¹C = anotherpart (A) · e^{J 2ΠΗ} [0327] In the above equation, SH is the frequency shift unit. Accordingly; the frequency and frequency of the changes B and C.

[0328] If the first remote signal is configured by the cyclic prefix (B) and the cyclic suffix (C), the probability that the data symbol is erroneously detected in the header is low and the probability of the preamble is erroneously detected is reduced, although the symbol symbols are configurable in the same FFT mode.

[0329] Continuous wave (CW) interference is included in the analog signal. In addition, if the FFT size is used for the message header, the message header can be corrected even more portion of the header symbol. Since both the cyclic prefix (B) and the cyclic suffix (C) are used in the header, the fractional offset of the correlation process.

[0330] FIG. 51 is a view showing an embodiment of the preamble signal shown in FIG. 50 and estimating the time shift and frequency offset. This embodiment may be included in the frame detector 221 or the frame synchronization unit 222.

[0331] This embodiment may comprise a first delay unit 601, a complex conjugate calculation unit 603, a first multiplier 605, a second multiplier 607, a first filter 611, a second delay unit 615, a third multiplier 609, and a second filter 613 , and the fourth mechanism multiplier 617, the peak search unit 619, and the phase measurement unit 621.

[0332] The first delay unit 601 may delay the received signal. For example, the first delay unit 601 may delay the signal of the first pilot signal.

[0333] The complex conjugate calculation unit 603 may calculate the complex conjugate of the delayed first pilot signal and the calculated signal.

[0334] The first multiplier 605 may multiply the signal output from the complex conjugate calculation unit.

[0335] Since the first pilot has signaled portions B and C obtained by shifting the frequency of the signal. In the first remote signal, part B is a part that is frequency-shifted up or frequency-shifted down from part A, and C is a part that is frequency-shifted upward or frequency-shifted down from part A.

[0336] For example, if the output of the first complex multiplier 605 is used for the portion of the first multiplier (ie the complex conjugate of part A).

[0337] The second multiplier 607 may be multiply the output signal of the first multiplier 605 by the frequency shift amount (denoted by ejnf);_SHt) applied to Part B and send the multiplied signal.

[0338] The first filter 611 performs a metron of the cyclic suffix (B) or the length of the cyclic suffix ( C). In this embodiment, the first

The filter 611, is the result of the average filter, 611, the correlation of the sum and still life. B ohhhhhhhhhhhhhhhhhhhhhhhhhhhjhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

[0339] The third multiplier 609 may be the multiplier of the frequency shift (denoted by ejnf)._SHt) applied to Part C and sends the multiplied signal.

[0340] The second filter 613 performs on the third digit of the cyclic suffix (B) or the length of the cyclic suffix ( C). In this embodiment, the second filter 613 can calculate the C of the second filter 613, the correlation of the parts in and that is average is calculated, becomes zero. The Since Since 60 C 60 60 60 60 60 A. 60 A. A. A. A..

[0341] The TB length of the parts, 611 and the second filter 613 is expressed as follows.

[Equation 2]

TB = k / fSH

[0343] where, k is an integer. In other words, the fSH frequency shift unit in B and C can be determined by k / TB.

[0344] The second delay unit 615. For example, the second delay unit 615 delays the signal filtered by the first filter.

[0345] The fourth multiplier 617 multiplexes the signal delayed by the second delay 613 and output the multiplied signal.

[0346] The peak search unit 621. The peak search unit has a 621. time shift.

[0347] The phase measurement unit 621 may output the changing phase. The phase value can be used to determine the fractional carrier frequency offset.

[0348] Meanwhile, the oscillator for generating the frequency 609 and the third multiplier 609 may generate any phase error.

[0349] Even in this case, the fourth multiplier 617 can eliminate the phase error of the oscillator. The results of the first filter 611 and the second filter 611 can be expressed by the following equation.

[Equation 3]

53/55 yMFI = || «1⁽ⁿ)² · ^{e jnΔ + θ}yMAF2 = | \^and2 ⁽ⁿ)² · ^{e jnf-θ} yprod = | l^andand^(N)|² · | l^and2^{(n) 2} · ^e'^{2n2A f} [0350] where, yMAF1 and yMAF2 represent the first filter and the second filter 613 respectively, and yProd denotes the output of the fourth multiplier 617. In addition, a1 and a2 Θ respectively mean frequency shift and oscillator phase error respectively.

[0351] Accordingly, yMAF1 and yMAF2 may have phase out 6 of the oscillator. error of the receiving signal device.

[0352] The estimated frequency offset can be expressed by the following equation.

[Equation 4]

<img file="PL2239906T3_D0001.tif" />

[0353] where, the estimated frequency offset Af is

0 &lt;= Af &lt;0.5.

[0354] FIG. 52 is a view showing the first pilot signal. In the first pilot signal, the frequency of the second shift is a cyclic suffix (C). The length of the useful part A, with the lengths of B and C being different.

[0355] FIG. 53 is a view of the first remote control signal shown in

53 / 55P29208PL00

FIG. 52 and measuring the time shift and frequency offset using the detected result. In this embodiment, for the convenience of the description, B and C represents cyclic prefix.

[0356] This embodiment includes a first delay unit 601, a complex conjugate calculation unit 603, a first multiplier 605, a second multiplier 607, a first filter 611, a second delay unit 615, a third multiplier 609, and a second filter 613, a fourth multiplier 617, and peak search unit 619, and a phase measurement unit 621. That is, it is an embodiment of FIG. 51, but the features of the components may be different. B and C are generated. B means the part frequency-shifted down from part A, and C means the part of the frequency-shifted up from part A.

[0357] The first delay unit 601 may delay the received signal. For example, the first delay unit 601 may the signal of the first pilot signal.

[0358] The complex conjugate calculation unit 603 may calculate the complex conjugate of the delayed first pilot signal and the calculated signal. [0359] The first multiplier 605 may multiply the signal output from a complex conjugate calculation unit.

[0360] The second multiplier 607 may by the frequency shift amount (denoted by ejnf);_SHt) applied to part B and sends the multiplied signal.

[0361] The first filter 611 performs a metron of the cyclic prefix (B). In this embodiment, the first filter 611, the correlation of the A and C contained in the The B and A still constant. A.ρ Bτηση αρ B A. με της A.ρ A.σεις από της A.ρ A.σεις

[0362] The third multiplier 609 may be the multiplex shift amount (denoted by ejnf);_SHt) applied to Part C and send the multiplied signal.

[0363] The second filter 613 performs a metron. In this embodiment, the second filter 613, the correlation of the second filter 613, the correlation average and that is insignificant and zero. The Since Since 60 C 60 60 60 60 60 A. 60 A. A. A. A..

[0364] The second delay unit 615 may delay the signal output from the first filter 611. For example, the second unit

Delay 615 delays the signal filtered by the first filter 611 by the length of the B + 1 / 2A part and sends a delayed signal.

[0365] The fourth multiplier 617 multiplexes the signal delayed by the second delay 613 and the output of the multiplied signal.

[0366] The peak search unit 619. The peak search unit 617. The value of the 621. The value of the plant is 621. Peak value and location can be used to estimate the time shift.

[0367] The phase metering unit 621 may the peak of the peak 619 sends the measured phase. The phase frequency can be used.

[0368] As described above, the oscillator for generating a frequency shift for the second multiplier 607 and the third multiplier 609 may generate any phase error. However, even the fourth multiplier 617 can eliminate the phase error of the oscillator.

[0369] The results obtained from the first filter 611 can be expressed by the following equation.

[Equation 5] j 2 πΔ _f + θ • e ^f j 2 πΔ _f_{• e}^f yMAFI = || «1^(N)\^{2 y}MAF2 = ||^fl2 ⁽ⁿ) j 2π · 2Δ f yprod = 1^{a (n)}\) · | AND^and2 ^(N)\) ·^e [0370] where, yMAF1 and yMAF2 represent the first filter 613, respectively, and yProd denotes the output of the fourth multiplier 617. In addition, a1 and a2

53, respectively, Mean levels of correlation results, and.

[0371] Accordingly, yMAF1 and yMAF2 may have phase five of the oscillator. error of the receiving signal device.

[0372] The estimated frequency offset can be expressed by the following equation.

[Equation 6]

<img file="PL2239906T3_D0002.tif" />

[0373] where, the estimated frequency offset At is

0 &lt;= f &lt;1.

[0374] That is, phase aliasing may be generated in the range of 0.5 &lt;= Af &lt;1 in the frequency offset in [Equation 4], but phase aliasing is not generated in the frequency offset estimated in [Equation 6]. Accordingly, the frequency offset can be more accurately measured. The structure of the first pilot signal may be used in the data symbol. If a structure is used, the displacement estimation can be improved.

[0375] FIG. 54 is a view of the shift and frequency offset using the detected result.

[0376] This embodiment includes a first delay unit 601, a third delay unit 602, and the first unit 603 for computing a complex conjugate, a second unit 603

Compound unit 604, the first multiplier 605, the first filter 606, the second filter 611, the second delay unit 615, the third multiplier 609, the second filter 613, the fourth multiplier 617, the unit 619 peak search, and a phase measurement unit 621.

[0377] In this embodiment, the first delay unit 601 may delay the received signal. For example, the f irst delay unit 601 may delay the signal of the cyclic suffix.

[0378] The third delay unit 602 may delay the signal delayed by the first delay unit 601. For example, the third delay unit 602 further delays of the cyclic suffix.

[0379] The first complexity calculation unit 603 may calculate the complex delayed by the third delay unit 602 and output the calculated signal. The second complex conjugate calculation unit 604 may calculate the complex delayed by the first delay unit 601 and output the calculated signal.

[0380] The first multiplier 605 may multiply the signal output from the first complex conjugate calculation unit. The fifth multiplier 606 may multiply the coupled complex number.

[0381] The second multiplier 607 may the multiplicity shift amount (denoted by ejnf);_SHt) applied to Part B and send the multiplied signal.

[0382] The first filter 611 performs a signal of the first pilot signal.

[0383] The third multiplier 609 may by the frequency shift amount (denoted by -ejnf)._SHt) applied to Part C and sends the multiplied signal.

[0384] The second filter 613 performs a second pilot multiplier 609.

[0385] The second delay unit 615. For example, the second delay unit 615 delays the signal filtered by the first filter suffer a delayed signal.

[0386] The fourth multiplier 617 multiplexes the signal delayed by the second delay 613 and output the multiplied signal. The fourth multiplier 617 can eliminate the phase error of the oscillator.

[0387] The operations of the peak search unit 621 and the phase measurement unit 621 are equal to those of the above-described embodiment. The peak search unit 619. Peak value and location can be used to estimate the time shift.

[0388] FIG. 55 is a view showing a method for transmitting a signal.

[0389] The service stream is converted to a PLP (S110). The PLP can be transformed into a service stream. The modulated service stream may be transmitted through a physical channel as a PLP. For example, the process of modifying a service stream to a PLP can be performed in the following steps from S110a to S110d.

[0390] GSE packet transferring service is error-correction-coded (S110a). The error correction coding scheme can be changed according to the service streams.

[0391] The LDPC error correction encoding scheme may be used as an error. The bits that are error-correction-coded according to the specific error correction coding block error correction coding mode. If the error is correct, the coding scheme is LDPC, the normal mode (64800 bits) and the short mode (16200 bits) can be used.

[0392] The service stream with coded error correction is interleaved (S110b). The interleaving can be performed in the block of error. The number of rows and the number of columns in the

The interleaving can be performed in the subject of correction error coding.

error correction. block unit

[0393] The interleaved bits of the service stream are mapped to symbols (S110c). The symbol mapping method may be changed according to the service streams or in the service stream. For example, and higher order symbol mapping method and a lower order symbol mapping method may be used as the symbol mapping method. When the symbols are mapped, the interleaved bits of the service stream may be demultiplexed according to the symbol of the mapping method, and the symbols may be mapped with the bits in the demultiplexed sub-streams. Then, the sequence of bits in the cell word mapped to symbols can be changed.

[0394] The mapped symbols are interleaved (S110d). The mapped symbols can be interleaved in the unit of blocks. The time interleavers 132a and 132b may interleave the symbols in the unit of error. That is, the service stream is interleaved in a horizontal symbol.

[0395] The PLP transformed as described above. The allocation of the PLP can be described as follows.

[0396] The interleaved symbols of the remote control signal are separated at the most frequently the beginning of the signal frame. The interleaved symbols of the service stream to provide the service. The PLP configuration symbols can be separated and allocated to the signal frame. The PLP can be allocated to at least

One signal frame at least one frequency band. If a plurality of frequency bands are provided, the PLP configuration symbols may be located in the slots displaced between the frequency bands. The bits included in the service stream.

[0397] The signal frame is converted into a real time domain of the OFDM scheme (S160).

[0398] The cyclic prefix is ​​the first pilot remote control signal of the first time remote control signal (S170). ). The If header header header header If header If If If If If If If If. The first pilot may be a part of the usable part, and the cyclic part of the second part of the usable part. The first part of the bridge is part of the most important part.

[0399] The signal frame including the first frame signal is transmitted over the RF channel (S180).

[0400] As a useful portion of the first remote control signal includes a frequency-shifted cyclic prefix, and a cyclic suffix, the signal frame can be easily identified. The time shift and frequency offset can be estimated.

[0401] FIG. 56 is a view of receiving a signal.

from a specific signal (S210) of the band

Frame [0402] The signal is received. The frequency of the signal signal. The signal may be received from a particular frequency band useful part is identified. demodulated using the OFDM scheme using the first pilot signal (S220). The remote control signal will be described in detail later.

[0404] The identified signal frame is analyzed (S230). The signal frame may at least one frequency band. In the signal frame, the first PLP containing the symbol error-coded blocks. The PLD including the error. The coded blocks of another service stream. If the signal frame includes a plurality of frequency bands, the PLP error correction encoded blocks may be allocated to OFDM symbols that are temporally shifted in a plurality of frequency bands.

[0405] The service may be obtained from the PLP of the signal signal frame (step S240) in S240a to S240c.

[0406] The symbols to which the service stream is mapped are interleaved in the image signal frame (S240a). Reverse de-interleaving can be performed on

The symbol level to which the service stream maps. For example, the time de-interleaving elements 245a and 245b may be de-interleaved with error-correction-coded blocks with symbols of which service is mapped.

[0407] Next, the inversely interleaved symbols are mapped in the end of the service stream is obtained (S240b). When the symbols are mapped in the end, the plurality of substreams received by the symbol mapping can be sent, the sent stream can be multiplexed, and the error can be sent. The multiplexing scheme may be changed in accordance with the symbol mapping method and the error correction coding efficiency. The symbol mapping method may be changed in the service of streams.

[0408] The service stream is inversely interleaved and the inversely interleaved service stream is error-correction-coded (240c).

[0409] According to a device for transmitting and receiving a signal, it is possible to detect and regenerate a transmitted signal. In addition, it is possible to improve the transmission / reception of the transmission / receiving system signal.

[0410] FIG. 57 is a flowchart illustrating the implementation of the demodulation procedure.

[0411] The first pilot signal shall take the cyclic part of the food. Time shift and frequency shift

53, may be calculated using the first remote signal as follows.

[0412] The received signal is delayed (S311). For example, delay pilot delay pilot pilot pilot pilot pilot pilot pilot pilot pilot pilot pilot. Alternatively, the portion of the delay may take the length of the cyclic suffix.

[0413] The complex number of the delayed signal is calculated (S313).

[0414] The composite number of the received signal and the delayed signal are multiplied (S315). The delayed signal multiplied by the complex conjugate may be a signal of the above-described length. If the delay signal is a length of a cyclic prefix or a cyclic suffix, the complex conjugate of the delayed signal may be calculated.

[0415] The signal multiplied by the complex conjugate is inversely shifted according to the frequency shift of the cyclic prefix (S317). That is, the signal multiplied by the complex Conversation is shifted by the change in the value of the cyclic prefix signal. That is, a signal that is frequency-shifted up is frequency-shifted down (or a signal that is frequency-shifted down is frequency-shifted up).

[0416] Next, the meaning is signaled with the cyclic prefix (S319). The first pilot signal on the occasions. The Since Since Since Since Since Since Since, the Since Since Since Since Since.

The average moving value may be sent along with the received signal.

[0417] The signal of which the average is calculated is delayed (S321). Of delay according according according A A A A A A A A A A A A A A A A A A A Embodiment.

[0418] The signal multiplied in step S315 is inversely shifted according to the frequency shift of the cyclic suffix (S323). The signal multiplied by the complex Conversation is shifted by the change in the value of the cyclic suffix signal. That is, the signal that is frequency-shifted up is frequency-shifted down (or the signal that is frequency-shifted down is frequency-shifted up).

[0419] The average pilot signal of the cyclic suffix (S325 is calculated by the frequency of the cyclic suffix.

with offset The signal delayed in the step S321 is multiplied (S327).

[0421]

The peak value of the peak is measured by the peak value of the peak signal (S329)

S331

The searched peak can be used to estimate the time shift. The measured phase can be used to estimate the frequency offset.

The data symbol is low and the message is [0422] In the flowchart, the length of the cyclic is the same, the length of the cyclic prefix, and the inverse frequency offset value can be changed.

[0423] According to the apparatus for transmitting and receiving the signal of the invention, the PLP configuration data symbol and the message header configura- tion symbols are modulated in the same FFT mode, the probability that the error-free header is reduced. If the continuous wave (CW) interference occurs, such as analogue TV signal, the probability of the message header being erroneously detected by the noise.

[0424] According to the FFT, the application of the FFT is the same as the FFT size applied to the invention. header, the message header is a different symbol for the header of the A part of the header. in the message header, a fractional carrier can be estimated.

[0425] The presented pilot signal structure may not be used for the signal frame including the PLP, and the remote control signal is used for any signal frame.

useful cyclic [0426] It will be understood that the idea of ​​the invention can not be understood. Therefore, intended

It is evident that the attitudes and their equivalences.

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