Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

[0001] The present invention relates to a method of transmitting and receiving a signal and an apparatus for transmitting and receiving a signal, and in particular, a method of transmitting and receiving a signal and devices for transmitting and receiving a signal that are capable of improving transmission efficiency.

[0002] As digital broadcasting technology evolved, users have received a high definition (HD) moving image. Along with the continuous development of compression algorithms and high performance of the equipment, a better environment will be provided to users in the future. A digital television system (DTV) can receive a digital broadcast signal and provide many additional services to users as well as a video signal and an audio signal.

Publication Mark J. Karol, Zygmunt J. Haas and Clark B. Woodworth "Performance Advantages Of Time-Frequency-Sliced ​​Systems" describes a system with cut-out time-frequency band allowing multiple users with different speed requirements to access a communication resource.

[0003] With the development of digital broadcasting technology, requirements for services such as video and audio signal are increasing and the amount of data required by the user or the number of broadcasting channels is gradually increasing.

[0004] Thus, the present invention is directed to a method of transmitting and receiving a signal and an apparatus for transmitting and receiving a signal which substantially removes one or more problems caused by the limitations and disadvantages of the prior art solutions.

[0005] The object of the present invention is to provide a method of transmitting and receiving a signal and an apparatus for transmitting and receiving a signal as shown in

53 of the attached claims 1 to 4, which are capable of improving data transmission efficiency.

[0006] Another object of the present invention is to provide a method for transmitting and receiving a signal and an apparatus for transmitting and receiving a signal that are capable of improving the error correction capability of the service configuration bits.

[0007] Additional advantages, objects and features of the invention will be set forth in the following part of the description and in the part which will become apparent to one of ordinary skill in the art having read the text below or may result from the application of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structure detailed in the description and claims presented herein as well as in the accompanying drawings.

[0008] The accompanying drawings, which are attached for the purpose of an additional understanding of the invention and which are incorporated into the present application and form part thereof, show an example (examples) of the embodiment of the invention and together with the description serve to explain the principle of the invention. In the drawings:

[0009] FIG. 1 is a view showing a signal frame for transmitting a service;

[0010] FIG. 2 is a view showing the structure of a first pilot signal P1 of a signal frame;

[0011] FIG. 3 is a view showing a signaling window;

[0012] FIG. 4 is a view showing an embodiment of a device for transmitting a signal;

[0013] FIG. 5 is a view showing an example of an input processor 110;

[0014] FIG. 6 is a view showing an embodiment of a coding and modulation unit;

[0015] FIG. 7 is a view showing an embodiment of a frame builder;

53 / 55P29302EN00 [0016] FIG. 8 is a view showing a first example of a ratio of symbols when the mappers 131a and 131b perform hybrid symbol mapping;

[0017] FIG. 9 is a view showing a second example of a ratio of symbols when the mappers 131a and 131b perform hybrid symbol mapping;

[0018] FIG. 10 is a view showing the number of symbols and the number of bits per cell word according to a symbol mapping scheme in the normal LDPC mode;

[0019] FIG. 11 is a view showing another example of the number of symbols according to a symbol mapping scheme in the normal LDPC mode;

[0020] FIG. 12 is a view showing another example of the number of symbols according to a symbol mapping scheme in the normal LDPC mode;

[0021] FIG. 13 is a view showing the number of symbols according to a symbol mapping scheme in the shortened LDPC mode;

[0022] FIG. 14 is a view showing an example of the number of symbols according to the symbol mapping scheme in the short LDPC mode;

[0023] FIG. 15 is a view showing another example of the number of symbols according to the symbol mapping scheme in the short LDPC mode;

[0024] FIG. 16 is a view showing an embodiment of each of the symbol mappers 131a and 131b

<td colspan="2">submitted</td><td colspan="5">in FIG. 7;</td>

<td>[0025] FIG</td><td> . 17</td><td>presents</td><td>view</td><td>illustrating</td><td>different</td><td>example</td>

<td>execution</td><td colspan="2">each item</td><td>131</td><td>and 131b</td><td colspan="2">mappers</td>

<td>symbols;</td><td></td><td></td><td></td><td></td><td></td><td></td>

<td>[0026] FIG</td><td> . 18</td><td>presents</td><td>view</td><td>illustrating</td><td>different</td><td>example</td>

making the symbol mapper;

53 / 55P29302EN00 [0027] FIG. 19 is a view showing another embodiment of each of the symbol mappers 131a and 131b;

[0028] FIG. 20 is a view showing the concept of bit interleaving by bit interleavers 1312a and 1312b;

[0029] Fig. 21 is a view showing a first example of the number of rows and columns in the memories of the bit interleavers 1312a and 1312b according to the types of the symbol mappers 1315a and 1315b;

[0030] Fig. 22 is a view showing a second example of the number of rows and columns in the memories of the bit interleavers 1312a and 1312b according to the types of the symbol mappers 1315a and 1315b;

[0031] FIG. 23 is a view showing the idea of ​​another embodiment of bit interleaving; [0032] FIG. 24 is a view showing another embodiment of bit interleaving;

[0033] FIG. 25 is a view showing another embodiment of bit interleaving;

[0034] FIG. 26 is a view showing the concept of demultiplexing the input bits of demultiplexers 1313a and 1313b;

[0035] FIG. 27 is a view showing an embodiment of demultiplexing an input stream by a demultiplexer;

[0036] FIG. 28 is a view showing an example of a demultiplexing type according to a symbol mapping method; [0037] FIG. 29 is a view showing an embodiment of demultiplexing an input bit stream according to the type of demultiplexing;

[0038] FIG. 30 is a view showing a type of demultiplexing that is determined according to the code rate for the error correction coding and symbol mapping method;

53 / 55P29302PL00

<td> [0039]</td><td>FIG.</td><td> 31</td><td>presents</td><td>view</td><td>illustrating</td><td>example</td>

<td colspan="3">expressive way</td><td colspan="2">demultiplexing for</td><td colspan="2">by the equation;</td>

<td> [0040]</td><td>FIG.</td><td> 32</td><td>presents</td><td>view</td><td>illustrating</td><td>example</td>

<td colspan="2">mapping</td><td colspan="5">symbol by the element mapping the symbols;</td>

<td> [0041]</td><td>FIG.</td><td> 33</td><td>presents</td><td>view</td><td>illustrating</td><td>example</td>

<td colspan="2">multipath</td><td colspan="2">signal encoder;</td><td></td><td></td><td></td>

<td> [0042]</td><td>FIG.</td><td> 34</td><td>presents</td><td>view</td><td>illustrating</td><td>example</td>

modulator execution;

<td>[0043] FIG. 35 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td>implementation of the analog processor</td><td> 160;</td><td></td><td></td>

<td>[0044] FIG. 36 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td colspan="2">making the receiving device</td><td colspan="2">signal capable of</td>

<td>receiving a signal frame;</td><td></td><td></td><td></td>

<td>[0045] FIG. 37 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td>making a signal receiver;</td><td></td><td></td><td></td>

<td>[0046] FIG. 38 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td>demodulator implementation;</td><td></td><td></td><td></td>

<td>[0047] FIG. 39 presents</td><td>view</td><td colspan="2">illustrating multipath</td>

<td>signal decoder;</td><td></td><td></td><td></td>

<td>[0048] FIG. 40 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td>making a frame parser;</td><td></td><td></td><td></td>

<td>[0049] FIG. 41 presents</td><td>view</td><td>illustrate</td><td>example</td>

<td>implementation of each element</td><td>247a</td><td>and 247p</td><td>vice versa</td>

mapping symbols;

[0050] FIG. 42 is a view showing another embodiment of each of the symbol demappers 247a and 247p;

[0051] FIG. 43 is a view showing another embodiment of each of the symbol demappers 247a and 247p;

[0052] FIG. 44 is a view showing another embodiment of each of the symbol demappers 247a and 247p;

53 / 55P29302EN00 [0053] FIG. 45 is a view showing an embodiment of multiplexing a demultiplexed sub stream; [0054] FIG. 46 is a view showing {above} an example of a decoding and demodulation unit;

[0055] FIG. 47 is a view showing an embodiment of an output processor;

[0056] FIG. 48 is a view showing another embodiment of a signal transmitting device for transmitting a signal frame;

[0057] FIG. 49 is a view showing another embodiment of a signal receiving device for receiving a signal frame;

[0058] FIG. 50 is a view showing an embodiment of the structure of a first pilot signal;

[0059] FIG. 51 is a view showing an embodiment of detecting the signal message header shown in FIG. 50 and time shift and frequency shift estimates;

[0060] FIG. 52 is a view showing another embodiment of the structure of the first pilot signal;

[0061] FIG. 53 is a view showing an embodiment of detecting the first pilot signal shown in FIG. 52 and measuring time shift and frequency shift;

[0062] FIG. 54 is a view showing an embodiment of detecting a first pilot signal and measuring a time offset and a frequency offset using a detected result;

[0063] FIG. 55 is a view showing an embodiment of a method of transmitting a signal;

[0064] FIG. 56 is a view showing an embodiment of a method of receiving a signal; and

53 / 55P29302EN00 [0065] FIG. 57 is a flowchart illustrating an embodiment of identifying the first pilot signal and estimating the offset in the demodulation process.

[0066] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference signs will be used in the drawings to designate the same or similar parts.

[0067] In the present specification, the term "service" indicates either the broadcast content that can be transmitted / received by the signal transmission / reception device or the delivery of specific content.

[0068] Before a device for transmitting and receiving a signal in accordance with an embodiment of the present invention is described, a signal frame will be described which is transmitted and received by a device for transmitting and receiving a signal according to an embodiment of the present invention.

[0069] FIG. 1 shows a signal frame for transmitting a service according to an embodiment of the present invention. [0070] The signal frame shown in FIG. 1 depicts an example signal frame for transmitting a broadcast service comprising audio / video (A / V) streams. In this case, a single service is multiplexed in time and frequency channels, and the multiplexed service is transmitted. The above signal transmission scheme is called the time-frequency division scheme (TFS). Compared with the case in which a single service is transmitted to only one radio frequency (RF) band, the signal transmitting device according to an embodiment of the present invention transmits the signal service over at least one RF band (several RF bands possible), so that he get a statistical increase in multiplexing capable of transmitting more numbers

53 / 55P29302EN00 services. The signal transmitting / receiving device transmits / receives a single service over several RF channels so that it can frequency. [0071] The first one to obtain an increase in the diversity of the third service to (Services 1-3) are transmitted to four RF bands (RF1 ~ RF4). However, this number of RF bands and this number of services are provided for illustrative purposes only, so that a different number may be used if necessary. Two reference signals (i.e., first pilot signal (P1) and second pilot signal (P2)) are located at the beginning of the signal frame. For example, in the case of the RF1 band, the first pilot signal (P1) and the second pilot signal (P2) are located at the beginning of the signal frame. The RF1 band contains three slots associated with Service 1, two slots associated with Service 2, and a single slot associated with Service 3. Slots associated with other services may also be placed in other slots (Slots 4 ~ 17) located behind a single slot associated with Service 3.

[0072] The RF2 band includes the first pilot signal (P1), the second pilot signal (P2), and other slots 13-17. In addition, the RF2 band includes three slots associated with Service 1, two slots associated with Service 2, and a single slot associated with Service 3.

[0073] Services 1 ~ 3 are multiplexed, and are then transmitted to the RF3 and RF4 bands according to a time-frequency division (TFS) scheme. The modulation scheme for signal transmission may be based on an orthogonal frequency division multiplexing (OFDM) scheme.

[0074] In the signal frame, individual services are shifted to RF bands (in this case there are multiple RF bands in the signal frame) and the time axis.

[0075] If signal frames equal to the above signal frame are successively arranged in time, the super-frame may be composed of different signal frames. The predicted extension frame may also be positioned among different signal frames. If the predicted extension frame is positioned among different signal frames, the super-frame may end in the predicted extension frame.

[0076] FIG. 2 shows the first pilot signal (P1) contained in the signal frame of FIG. 1 in accordance with an embodiment of the present invention.

[0077] The first pilot signal P1 and the second pilot signal P2 are located at the beginning of the signal frame. The first pilot signal P1 is modulated using the 2K FFT mode, and can be transmitted simultaneously including ¼ of the protection interval. In FIG. 2, the 7.61Mhz band of the first pilot signal P1 contains the band 6.82992Mhz. The first pilot signal uses 256 carriers from among 1705 active carriers. A single active carrier is used on average for every 6 carriers. Data carrier intervals may be irregularly arranged in the order of 3, 6, and 9. In FIG. 2, the solid line indicates the location of the used carrier, the thin dashed line indicates the location of the unused carrier, indicates the middle location

In the first pilot signal, the used carrier may be mapped to symbols by phase shift binary keying (BPSK), and the bit sequence (PRBS) may be modulated. The size of the pilot signal may be an unused carrier point line

FFT be a pseudo-random used to another indicated by various PRBS.

[0078] The signal receiving device detects the signal structure time-frequency division of the detected structure. The pilot device and recognizes (TFS) using the receiving signal acquires the FFT size of the second signal

53 / 55P29302EN00 pilot, compensates for the coarse frequency shift of the reception signal, and acquires time synchronization.

[0079] In the first pilot signal, the signal transmission type and transmission parameter can be set.

[0080] The second pilot signal P2 may be transmitted with an FFT size and a protection interval equal to that of the data symbols. In the second pilot signal, a single carrier is used as the pilot carrier in three carrier compartments. The signal receiving device compensates for the slight frequency synchronization shift using the second pilot signal, and performs a slight time synchronization. The second pilot signal transmits the first layer (L1) information among the Open Systems Interconnection OSI layers. For example, the second pilot signal may include a physical parameter and frame construction information. The second pilot signal transmits the parameter value through which the receiver can access the stream of the Physical Layer (PLP) service.

[0081] L1 (Layer 1) information contained in the second pilot signal P2 is as follows.

[0082] The Layer-1 (L1) information includes a length indicator indicating the length of the data containing the L1 information, so that it can easily use the signaling channels of Layers 1 and 2 (L1 and L2). The Layer-1 (L1) information includes a frequency indicator, guard interval length, the maximum number of FEC (Forward Error Correction) blocks for each frame in connection with individual physical channels, and the number of actual FEC blocks to be included in the FEC block buffer associated with the current / previous frame on each physical channel. In this case, the frequency indicator indicates the frequency information corresponding to the RF channel.

[0083] The Layer-1 (L1) information may include different information in association with individual slots. For example, the Layer-1 (L1) information includes the number of frames associated with the service, the start address of the slot having the OFDM carrier accuracy contained in the OFDM symbol, the slot length, slots corresponding to the OFDM carrier, the number of bits filled in the last OFDM carrier, service modulation information, information on the speed of service mode, and information on the Multi-Input-Multi-Output MIMO scheme.

[0084] The Layer-1 (L1) information may include a cell ID, a service flag such as a notification service message (e.g., threat status message), the number of current frames, and the number of additional bits for future use. In this case, the cell ID indicates the broadcast area transmitted by the broadcast transmitter.

[0085] The second pilot signal P2 is adapted to perform channel estimation for decoding the symbol contained in the P2 signal. The second pilot signal P2 may be used as an initial value to estimate the channel for the next data symbol. The second pilot signal P2 may also transmit Layer-2 (L2) information. For example, the second pilot signal is able to describe the information associated with the transmission service in the Layer-2 (L2) information. The signal transmitting device decodes the second pilot signal so that it can acquire the service information contained in the time division frequency (TFS) frame and can efficiently perform channel scanning. Meanwhile, this Layer-2 (L2) information may be included in a specific PLP of the TFS frame. According to another case, L2 information may be included in a specific PLP, and service description information may also be transmitted in a specific PLP. [0086] For example, the second pilot signal may include two OFDM symbols of the 8k FFT mode. Basically, a second pilot signal

53 / 55P29302EN00 can be any single OFDM symbol from 32K FFT mode, a single OFDM symbol from 16k FFT mode, two OFDM symbols from 8k FFT mode, four OFDM symbols from 4k FFT mode, and eight OFDM symbols from 2k FFT mode.

[0087] In other words, a single OFDM symbol having a large FFT size or several OFDM symbols, each of which is a small FFT size, can be included in the second pilot signal P2, so that a bandwidth that can be transmitted to the pilot signal can be maintained .

[0088] If the information to be transmitted to the second pilot signal exceeds the capacity of the OFDM symbol of the second pilot signal, OFDM symbols after the second pilot signal may be further used. The L1 (Layer1) and L2 (Layer2) information contained in the second pilot signal is error-correction-coded and then interleaved so that data recovery is performed despite the occurrence of impulse noise.

[0089] As previously described, L2 information may also be included in a specific PLP carrying information describing the service.

[0090] FIG. 3 shows a signaling window in accordance with an embodiment of the present invention. The time-frequency division frame (TFS) presents the idea of ​​shifting signaling information. The Layer-1 (L1) information contained in the second pilot signal includes frame construction information and physical layer information required by the signal receiving device decoding the data symbol. Thus, if information about preceding data symbols placed after the second pilot signal is included in the second pilot signal, and the resultant second pilot signal is transmitted, and the signal receiving device may be unable to immediately decode the above preceding data symbols due to the decoding time of the second pilot signal .

[0091] Thus, as shown in FIG. 3, L1 information contained in the second pilot signal (P2) includes information about a single time frequency partitioning (TFS) frame size, and includes information contained in the signaling window at a location outside the second pilot signal by shifting the signaling window. [0092] In the meantime, to perform channel estimation of the data symbol forming the service, the data symbol may include a scatter pilot and a continual pilot.

[0093] Hereinafter, a signal transmission / reception system capable of transmitting / receiving signal frames shown in FIG. 1-3. Individual services can be transmitted and received via individual RF channels. The path to broadcast each of the services or stream transmitted over this path is called the PLP. The PLP can be split among time-divided slots in several RF channels or in a single RF band. This signal frame may carry the time-divided PLP to at least one RF channel. In other words, a single PLP can be transferred through at least one RF channel with time-divided regions. In the following, signal transmission / reception systems transmitting / receiving a signal frame over at least one RF band will be described.

[0094] FIG. 4 is a block diagram illustrating an apparatus for transmitting a signal according to one embodiment of the present invention. Referring to FIG. 4, the signal transmitting device includes an input processor 110, coding and modulation unit 120, frame builder 130, MIMO / MISO encoder 140, multiple modulators (150a, ...,

150r) of the MIMO / MISO 140 encoder, and many analog processors (160a, ..., 160r).

[0095] The input processor 110 receives streams containing individual services, generates a P number of bandwidth frames

A basic (P is a natural number) which contain coding and modulation information corresponding to the transmission paths of individual services, and outputs the P number of baseband frames.

[0096] The coding and modulation unit 120 receives baseband frames from the input processor 110, performs the channel coding and interleaving on each of the baseband frames, and outputs the channel coding and interleaving result.

[0097] The frame builder 130 creates frames that transmit baseband frames contained in the P number of PLPs to the R number of RF channels (where R is a natural number), separates shaped frames, and sends separated frames to paths corresponding to the R number of RF channels. Individual services can be multiplexed in a single RF channel at a time. Signal frames generated from the frame builder 140 may include a time-frequency division (TFS) structure in which the time and frequency domain multiplexed service.

[0098] The MIMO / MISO encoder 140 encodes signals to be transmitted to the R number of RF channels, and outputs the encoded signals to paths corresponding to A number of antennas (where A is a natural number). The MIMO / MISO encoder 140 sends an encoded signal in which the signal to be transmitted to a single RF channel is encoded into the A number of antennas, so that the signal is transmitted / received to / from the MIMO structure (Multiple Inputs Multiple Outputs) - (Multi -Input-Multi-Output) or MISO (Multi-Input-Single-Output).

[0099] Modulators (150a, ..., 150r) modulate frequency-domain signals introduced through the path corresponding to each RF channel to time-domain signals. Modulators (150a, ..., 150r) modulate the input signals according to an orthogonal frequency division multiplexing (OFDM) scheme, and outputs the modulated signals.

[0100] Analog processors (160a, ..., 160r) convert input signals to RF signals so that RF signals can be sent to RF channels.

[0101] The signal transmitting apparatus according to this embodiment may include a predetermined number of modulators (150a, ..._ 150r) corresponding to the number of RF channels and a predetermined number of analog processors (160a, ..., 160r) corresponding to the number of RF channels. However, when using the MIMO scheme, the number of analog processors must be equal to the product of R (i.e., the number of RF channels) and A (i.e., the number of antennas).

[0102] FIG. 5 is a block diagram illustrating an input processor 110 in accordance with an embodiment of the present invention. Referring to FIG. 5, the input processor 110 includes a first stream multiplexer 111a, a first service splitter 113a, and a plurality of first constructors (115a, ..., 115m) of baseband (BB) frames. The input processor 110 includes a second stream multiplexer 111b, a second service splitter 113b, and a plurality of second constructors (115n, ..., 115p) of baseband (BB) frames.

[0103] For example, the first stream multiplexer 111a receives individual MPEG-2 transport streams (TS), multiplexes the received MPEG-2 TS streams, and outputs the multiplexed MPEG-2 TS streams. The first service splitter 113a receives the multiplexed streams, splits the input streams of the individual services, and outputs the split streams. As described above, provided that the service transmitted over the physical channel path is called PLP, the first service splitter 113a splits the service to be transmitted to each PLP, and sends the split service.

[0104] The first constructors (115a, ..., 115m) of BB frames create data contained in the service to be transmitted to each PLP in the form of a specific frame, and send the data

53 / 55P29302EN00 encapsulation multiplexer with streams.

formatted to a specific frame. The first constructors (115a, ..., 115m) of BB frames form a frame containing a header and a data field containing the given services. The header of each frame may contain mode information based on the modulation and coding of the service data, and a counter value based on the modulator clock cycle frequency to synchronize the input streams.

[0105] The second stream multiplexer 111b receives individual streams, multiplexes input streams, and outputs the multiplexed streams. For example, the second stream multiplexer 111b may multiplex Internet Protocol (IP) streams instead of MPEG-2 TS streams. These streams can be encapsulated using a generic stream encapsulation scheme (GSE - generic stream. The streams multiplexed by the second stream 111b can be any

Thus, the streams described above that differ in TS are called generic (GS streams) streams from MPEG-2 streams.

[0106] The second service splitter 113b receives the multiplexed generic streams, splits the received generic streams according to individual services (i.e., PLP types), and outputs the split GS streams.

[0107] Second constructors (115n,.

they create service data that have individual PLPs in the form of a specific frame used as a signal processing unit, and send the resultant service data. Frame format created by

115p) BB band frames to be transmitted to second constructors (115n, ... if necessary, such constructors (115a, necessity, can be implemented. In another

115p) BB frames can be, same as the format of the first .., 115m) BB frames. If you suggest also another example of the embodiment, created by the second constructors (115n, frame format, 115p) frames

The BB band may be different from the format of the first constructors (115a, ..., 115m) of BB frames. The TS MPEG-2 header also contains the Package Synchronization Word, which is not included in the GS stream resulting in the occurrence of different headers.

[0108]

FIG.

is a block diagram illustrating a coding and modulation unit according to the present invention. The coding and modulation unit includes a first interleaver 123, a second encoder 125, and a second interleaver 127.

[0109] The first encoder 121 acts as an outer coder of the input baseband frame, and is able to perform the error correction encoding. The first encoder 121 performs the error correction encoding of the input baseband frame using the Bose-ChaudhuriHocquenghem (BCH) scheme. The first interleaver 123 performs interleaving of the encoded data, such that it prevents a burst error from being generated in the transmission signal. The first interleaver 123 may not be included in the above-mentioned embodiment.

[0110] The second encoder 125 acts as an inner coder of either the output data of the first encoder 121 or the output data of the first interleaver 123, and is able to perform the error correction encoding. A low density parity (LDPC) bit scheme may be used as the error correction coding scheme. The second interleaver 127 mixes the error-correction-coded data generated by the second encoder 125, and outputs the mixed data. The first interleaver 123 and the second interleaver 127 are able to interleave data in bit units.

[0111] The coding and modulation unit 120 relates to a single PLP stream. The PLP stream is error-correction-coded and modulated by the coding unit i

Modulating 120, and then transmitted to the frame builder 130.

[0112] FIG. 7 is a block diagram illustrating a frame builder according to an embodiment of the present invention. Referring to FIG. 7, the frame builder 130 receives streams of individual paths from the coding and modulation unit 120, and arranges the received streams in a single signal frame. For example, the frame builder may include a first mapper 131a and a first time interleaver 132a in a first path, and may include a second mapper 131b and a second time interleaver 132b in the second path. The number of input paths is equal to the number of PLPs for the service transmission or the number of streams transmitted by each mapping pipe 131a may input from

PLP.

[0113] The first mapper 131a performs mapping of data contained in the input stream according to the first symbol mapping scheme. For example, the first element to perform mapping using a QAM scheme (e.g., 16 QAM, 64 QAM, and 256 QAM). [0114] If the first mapper 131a performs mapping of the symbol, the input data may be mapped to individual types of symbols according to individual symbol mapping schemes. For example, the first mapper 131a classifies the input into the baseband frame unit and the baseband frame subunit. Individual classified data can be hybrid mapped to symbols using at least two QAM schemes (e.g. 16 QAM and 64 QAM). Thus, data contained in a single service may be mapped to symbols based on different symbol mapping schemes in individual intervals.

[0115] The first time interleaver 132a receives a symbol sequence mapped by the first mapper 131a, and is able to perform time domain interleaving. The first mapper 131a maps data that is contained in the error-corrected frame unit received from the coding and modulation unit 120 into symbols. The first time interleaver 132a receives the symbol sequence mapped by the first mapper 131a, and interleaves the received symbol sequence in units of the error-corrected frame.

[0116] In this way, the p-th mapper 131p or the p-th time interleaver 132p receives service data to be transmitted to the p-th PLP, maps the service data to symbols according to the p-th symbol mapping scheme. The mapped symbols can be interleaved in the time domain. Note that this symbol mapping scheme and this interleaving scheme are equal to those of the first time interleaver 132a and the first mapper 131a.

[0117] The symbol mapping scheme of the first mapper 131a may be equal to or different from that of the p-th mapper 131p. The first mapper 131a and the p-th mapper 131p are able to map input to individual symbols using the same or different hybrid symbol mapping schemes.

[0118] Data of time interleavers located in individual paths (i.e., service data interleaved by the first time interleaver 132a and service data to be transmitted to the R number of RF channels using the p-th time interleaver 132p) is interleaved, so that the physical channel allows this data to be interleaved on individual RF channels.

53 / 55P29302EN00 RF channels.

received frame above [0119] In association with streams received in as many paths as the number of PLPs, the TFS frame builder 133 creates the TFS signal frame such as the previously mentioned signal frame, such that the service is time-shifted according to the TFS frame builder 133 splits the data service of any of the paths, and sends the service data separated into the R number data of the RF bands according to the signal planning scheme.

[0120] The TFS frame builder 133 receives the first pilot signal and the second pilot signal from the signaling information unit (denoted by the Ref / PL signal) 135, arranges the first and second pilot signals in the signal, and inserts the signaling signal (L1 and L2) of said layer in the second pilot signal. In this case, the first and second pilot signals are used as the beginning signals of the signal frame contained in each RF channel among the TFS signal frames received from the signaling information unit (Ref / PL signal) 135. As shown in FIG. 2, the first pilot signal may include a transmission type and basic transmission parameters, and the second pilot signal may include a physical parameter and frame creation information. Also, the second pilot signal includes the L1 signaling signal (Layer 1) and the L2 signaling signal (Layer 2).

[0121] The R number of frequency interleavers (137a, ..., 137r) interleave service data, to be transmitted to the respective RF channels of the TFS signal frame, in a frequency domain. Frequency interleavers (137a, ..., 137r) can interleave service data at the level of data cells contained in an OFDM symbol.

[0122] In congestion, the service data to be transmitted to each RF channel in the TFS signal frame is processed with selective frequency decays, so that it cannot be lost in a specific frequency domain.

53 through 55 [FIG. 8 is a view showing a first example of a ratio of symbols when the mappers 131a and 131b perform hybrid symbol mapping. This Figure shows the number of bits transmitted by one subcarrier (cell) if the error correction coding is performed by the coding and modulation unit in normal mode (the length of the error correction coded code is 64,800 bits) of the LDPC error correction coding mode.

[0124] For example, if the mappers 131a and 131b perform symbol mapping using 256QAM, 64800 bits are mapped to 8100 symbols. If the mappers 131a and 131b perform hybrid symbol mapping (Hyb 128-QAM) using 256QAM and 64QAM with a 3: 2 ratio, the number of mapped symbols the number of mapped symbols The number of transmitted bits per subcarrier (cell) is 7.0588.

[0125] If a 64QAM symbol mapping method is used, the input data may be mapped to 10800 symbols and six bits per cell may be transmitted. If the data is mapped to symbols by a hybrid symbol mapping method 64QAM and 16QAM (64QAM: 16QAM = 3: 2, Hyb32-QAM), five bits can be transmitted by one subcarrier (cell).

[0126] If data is mapped to symbols by the 16QAM method, the data is mapped to 16200 symbols, each of which is used to transmit four bits.

256QAM is 4860 and 64QAM is 4320.

[0127] Similarly, if data is mapped to symbols by a hybrid symbol mapping method 16QAM and QPSK (16QAM: QPSK = 2: 3, Hyb8-QAM), three bits may be transmitted by one subcarrier (cell).

[0128] If data is mapped to symbols by a QPSK method, the data may be mapped to 32400 symbols, with

53 / 55P29302EN00 each of which is used to transmit two bits.

[0129] FIG. 9 shows methods of mapping error correction data symbols using an LDPC short mode error correction coding method (error correction coded code length is 16200 bits) that are equal to the symbol mapping methods of FIG. 8, and the number of bits per subcarrier according to the symbol mapping methods.

[0130] The number of bits transmitted by the subcarrier is equal to the numbers of the normal mode (64800 bits) according to symbol mapping methods such as 256QAM, Hyb 128-QAM, 64-QAM, Hyb 2-QAM, 16QAM, Hyb8-QAM and QPSK, but integers the numbers of symbols transmitted are different from the numbers from normal mode. For example, 16200 bits are transmitted by 2025 symbols in 256QAM, 16200 bits are transmitted by 1215 symbols according to 256QAM and 1080 symbols according to 64QAM (total 2295 symbols) in Hyb 128-QAM.

[0131] Accordingly, the data rate per subcarrier (cell) for each PLP can be adjusted according to the hybrid symbol mapping method or the single symbol mapping method.

[0132] FIG. 10 is a view showing the number of symbols and the number of bits per cell word according to the symbol mapping method in normal LDPC mode. If the TFS signal frame contains at least one RF channel, the symbols configuring a particular PLP can be uniformly allocated to the RF channels. Locations of PLP symbols allocated to RF channels can be more efficiently addressed. Accordingly, when the signal receiving device selects the RF channels, the bits used to address the specific PLP can be reduced.

[0133] In this drawing, the symbol mapping method represented by 256-QAM indicates a method of mapping bits configuring a single block subjected to error correction coding to symbols with a factor

256QAM: 64QAM = 8: 1. According to this symbol mapping method, the number of bits in a single error-correction-coded block by the 256-QAM method is 57600, the number of bits in a single error-correction-coded block by the 256-QAM method is 1200, the number of all symbols in the block is 8400 and the number of bits per cell word is 7.714285714.

[0134] The symbol mapping method represented by Hyb 128-QAM indicates a method of mapping bits configuring a single error-correction-coded block to symbols with a ratio of 256QAM: 64QAM = 8: 7. According to the Hyb 128-QAM symbol mapping method, the number of all symbols in a single error-correction coding block is 9600, and the number of bits per cell word is 6.75.

[0135] According to the symbol mapping method represented by 64 QAM, the number of all symbols in a single error-correction coding block is 10800 and the number of bits per cell word is 6.

[0136] The symbol mapping method represented by Hyb 32-QAM indicates a method of mapping bits configuring a single error-correction-coded block to symbols with a ratio of 64QAM: 32QAM = 5: 4. According to the Hyb 32-QAM symbol mapping method, the number of all symbols in the error-correction-coded block is 13200 and the number of bits per cell word is 4.9090909. [0137] The symbol mapping method represented by 16 QAM indicates a method of mapping bits configuring a single error-correction-coded block to symbols with a ratio of 16QAM: QPSK = 1: 8. According to the 16 QAM symbol mapping method, the number of all symbols in one

53 / 55P29302EN00 error correction coded block is 15600, the number of bits per cell word is 4.153846154.

[0138] The symbol mapping method represented by Hyb 8-QAM indicates a method of mapping bits configuring a single error-correction-coded block to symbols with a ratio of 16QAM: QPSK = 2: 1. According to the Hyb 8QAM symbol mapping method, the number of all symbols in one error-correction-coded block is 21600, and the number of bits per cell word is 3.

[0139] According to the symbol mapping method provided by QPSK, the number of all symbols in one error-correction-coded block is 32400 and the number of bits per cell word is 2.

[0140] When PLP configuration symbols are allocated to RF channels, the frequency domain diversity increase can be maximized when the numbers of symbols allocated to the respective RF channels are equal. If a maximum of six RF channels are considered, the smallest common multiple of 1 to 6 is 60 and the largest common divisor of the number of symbols mapped to one error-correction-coded block is 1200. Accordingly, if an integral multiple of 1200/60 = 20 symbols is allocated to each of the RF channels, the symbols can be uniformly allocated to all RF channels. At this time, if 20 symbols are considered as one group and the group is addressed, the addressing overhead of log2 (20) «4.32 bits can be reduced compared to the case where the symbols are addressed one by one.

[0141] FIG. 11 is a view showing another example of the number of symbols according to the symbol mapping method in normal LDPC mode. In the example from the drawing, the 256-QAM method using the 256QAM and 64QAM symbols is used as the symbol mapping method (256QAM: 64QAM = 4: 1),

53 / 55P29302EN00 Hyb 128-QAM method using 256QAM and 64QAM symbols (256QAM: _64QAM = 8: 7), 64QAM method, Hyb 32-QAM method using 64QAM and 8QAM symbols (64QAM: 8QAM = 3: 2), method 16 QAM using the symbols 16QAM and QPSK (16QAM: QPSK = 1: 14), the Hyb 8-QAM method using 16QAM: QPSK = 2: 1 and the QPSK method. The largest common divisor (GCD) of the numbers of all symbols of the error-correction-coded block (normal mode) according to the symbol mapping methods is 720. Accordingly, if an integer multiple of 12 (= 720/60) symbols is allocated to each of the RF channels, the symbols may be uniformly allocated to all RF channels. At this time, if 12 symbols are considered as one group and this group is addressed, the addressing overhead of log2 (12) = 3.58 bits can be reduced compared to the case where the symbols are addressed one by one. The signal receiving device may collect the allocated PLP symbols using the addressing scheme and receive the PLP service stream.

[0142] FIG. 12 is a view showing another example of the number of symbols according to the symbol mapping method in normal LDPC mode. In the example from the drawing, the 256QAM scheme, Hyb 128-QAM scheme, 64QAM scheme, Hyb 32-QAM scheme, 16 QAM scheme, Hyb 8-QAM scheme and QPSK scheme were used as a symbol mapping method. The 256QAM symbol mapping method uses the 256QAM and 64QAM symbols (256QAM: 64QAM = 44: 1) and the Hyb 128-QAM symbol mapping method uses the 256QAM and 64QAM symbols (256QAM: 64QAM = 28: 17). The Hyb 32-QAM method uses 64QAM and 8QAM symbols (64QAM: 8QAM = 3: 2), the 16QAM symbol mapping method uses 16QAM and QPSK symbols (16QAM: QPSK = 1: 14), and the Hyb 8-QAM symbol mapping method uses 16QAM symbols. and QPSK (16QAM: QPSK = 2: 1). GCD numbers of all symbols of the error-correction-coded block (normal mode)

According to the symbol mapping methods is 240. Accordingly, if an integral multiple of the symbols 240/60 = 4 is allocated to each of the RF channels, the symbols can be uniformly allocated to all RF channels. At this time, if four symbols are considered as one group and the group is addressed, the addressing overhead of log2 (4) 2 bits can be reduced compared to the case where the symbols are addressed one by one. Accordingly, even when the number of RF channels is any number from 1 to 6 in the signal frame, PLP symbols can be uniformly allocated to the RF channels.

[0143] FIG. 13 is a view showing the number of symbols according to the symbol mapping method in LDPC short mode. As described above, if symbol mapping is performed according to this example, PLP symbols can be uniformly allocated to RF channels and the PLP symbol address overhead can be reduced. The symbol mapping methods shown in this drawing are equal to those shown in FIG. 10. However, because the number of bits of the LDPC short mode differs from the number of bits of the normal mode, the GCD numbers of all symbols of the error-coded block (short mode) according to the symbol mapping methods is 300, different from FIG. 10. Accordingly, if an integer multiple of the RF channels, symbols 300/60 = 5 is allocated to each, these symbols can be uniformly allocated channels

RF.

At the same time, if five for all symbols are considered as one group, this group is addressed, there may be symbols for this, including addressing overhead of log2 (5) bits reduced compared to the case where addressed one by one. According to an embodiment, the addressing bits are preserved by log2 (5) bits when the split PLP symbols are addressed.

53 / 55P29302EN00 [0144] FIG. 14 is a view showing an example of the number of symbols according to the symbol mapping method in the LDPC short mode. The symbol mapping methods of this drawing are equal to those shown in FIG. 11. In this example, the GCD number of all symbols of the error-correction-coded block (short mode) according to the symbol mapping methods is 180, which can be used to allocate PLP symbols of one RF channel and address the allocated symbols. In this embodiment, the addressing bits are saved by log2 (3) bits.

[0145] FIG. 15 is a view showing another example of the number of symbols according to the symbol mapping method in the LDPC short mode. These symbol mapping methods of the drawing are equal to those shown in FIG. 12. In this example, the GCD of the numbers of all symbols of the error-correction-coded block (short mode) according to the symbol mapping methods is 60. In this embodiment, the addressing bits are stored with log2 (1) bits (i.e., the addressing bit is not stored).

[0146] FIG. 16 is a view showing an example of each of the symbol mappers 131a and 131b shown in FIG. 7. Each of the symbol mappers 131a and 131b includes a first order mapper 1315a, a second order mapper 131b, a symbol merger 1317 and an error correction block merger 1318.

[0147] The bit stream parser 1311 receives the PLP service stream from the coding and modulation unit and splits the received service stream.

[0148] The first order symbol mapper 1315a maps the bits of the service stream split by a higher order symbol mapping method to symbols. The second order symbol mapper 1315b maps the bits of the service stream divided by a lower order symbol mapping method to symbols. For example, in the above

For example, the first order symbol mapper 1315a may map the bit stream to symbols according to 256QAM and the second order symbol mapper 1315b may map the bit stream to symbols according to 64QAM. [0149] The symbol merger 1317 combines the symbols output from the symbol mappers 1315a and 1315b to one symbol stream and outputs the symbol stream. The symbol merger 1317 may output the symbol stream contained in one PLP.

[0150] The error correction block merger 1318 may output one symbol stream merged by the symbol merger 1317 in the error correction coded block unit. The error correction block merger 1318 may output the symbol block such that the error correction coded code blocks are uniformly allocated to at least one RF band of the TFS signal frame. The error correction block merger 1318 may output the symbol block such that the length of the symbol block of the normal mode error correction coded block is equal to the length of the symbol block of the short mode error correction coded block. For example, four symbol blocks of a short mode error correction coded block may be combined into one symbol block.

[0151] The error correction block merger 1318 may split the symbol stream according to a common multiple of the number of RF bands such that the signal frame builder uniformly arranges the symbols to the RF bands. If the maximum number of RF bands in the signal frame is 6, the error correction block connecting element 1318 sends a symbol block so that the total number of symbols can be divided by 60 which is a common multiple of 1, 2, 3, 4, 5 and 6.

[0152] The symbols contained in the output symbol block can be arranged to be uniformly allocated to six RF bands. Accordingly, despite the fact that the error correction mode according to the coding efficiency and mapping method

The symbols are combined, the symbols configuring the PLP are uniformly allocated to the RF bands.

[0153] FIG. 17 is a view showing a different embodiment of each of the symbols mapper 131a and 131b. The embodiment of this drawing is similar to the embodiment of FIG. 16 except that it additionally includes a first order power calibration unit 1316a and a second order power calibration unit 1316b.

[0154] The first order power calibration unit 1316a calibrates the power of the symbols mapped by the first order symbol mapper 1315a according to the size of the constellation and outputs the calibrated symbols. The second order power calibration unit 1316b calibrates the power of the symbols mapped by the second order mapper 1315b according to the size of the constellation and the symbols calibrated. Accordingly, although symbol mapping varies in one PLP or varies among multiple PLPs, if the symbol power is set by the symbol mapping method according to the size of the constellation, the signal reception performance of the receiver can be improved.

[0155] The symbol merger 1317 combines the symbols calibrated by the power calibration units 1316a and 1316b and outputs one symbol stream.

the symbols send the method [0156] FIG. 18 is a view showing another embodiment of the symbol mapper. In the embodiment of this Figure, the symbol mapper includes the second encoder 125 and the second interleaver 127 included in the coding and modulation unit. That is, if this embodiment is used, the coding and modulation unit may include only the first encoder 121, the first interleaver 123 and the second encoder 125.

[0157] An embodiment of the symbol mapper includes the bit stream parser 1311, the interleaver

53 / 55P29302PL00

1312a first order bits, second order bit interleaver 1312b, first order demultiplexer 1313a, second order demultiplexer 1313b, first order symbol mapper 1315a, second order symbol mapper 1315b, and symbol linker 1317b.

[0158] When the second encoder 125 performs LDPC error correction coding, the length of the error correction coded block (e.g., length 64800 bits and length 16200 bits) may vary according to LDPC mode. If the bits contained in the error-correction-coded block are mapped to symbols, the error correction capabilities of the bits contained in the symbol cell word of the symbol may change according to the locations of the bits. For example, the cell word that is a symbol may be determined according to its error correction coding efficiency and symbol mapping method (whether the symbol mapping method is a higher order symbol mapping method or a lower order symbol mapping method). If the error correction code is LDPC, the bit error correction options vary depending on the location of the bits in the error-correction-coded block. For example, the reliability of the bits coded according to the characteristics of the H matrix used in the irregular LDPC error correction coding method may vary according to the locations of the bits. Accordingly, the order of bits configuring the cell word mapped to the symbol changes so that the possibility of bit error correction is adjusted, which is prone to error correction in the error-correction-coded block, and the error resistance at the bit level can be adjusted.

[0159] First, the second encoder 125, for example, performs the error correction coding with respect to the stream included in one PLP by the LDPC error correction coding method.

[0160] The bit stream parser 1311 receives the service stream according to the PLP and splits the received service stream.

[0161] The bit interleaver interleaves the bits contained in

1312a first order bits of the first bit stream of the split service streams. Similarly, the second order bit interleaver 1312b interleaves the bits contained in the second bit stream of the split service streams.

[0162] The first order bit interleaver 1312a and the interleaver correspond to the second

1312b the second order bits may interleaver 127 used as an inner interleaver. Hereinafter, the method of interleaving the first order bit interleaver 1312a and the second order bit interleaver 1312b will be described.

[0163] The first order demultiplexer 1313 and the second order demultiplexer 1313b demultiplex the bits of the bit streams interleaved by the first order bit interleaver 1312a and the second order bit interleaver 1312b.

Demultiplexers 1313a

1313b divide the input bit stream into the bit substreams that will be mapped to the real axis and the bit substreams. the symbols map the imaginary axis of the constellation and sends the mappers 1315a and 1315b bit streams demultiplexed by the demultiplexers 1313a and 1313b to the corresponding symbols.

[0164] The bit interleavers 1312a and 1312b and demultiplexers 1313a and 1313b can combine the characteristics of the LDPC codeword and the reliability characteristics of the symbol mapping constellation according to the constellation. A detailed embodiment of the first order demultiplexer 1313a and 1313b will be described hereinafter.

[0165] The first order symbol mapper 1315a performs first order symbol mapping, for example, higher order symbol mapping and the mapper

1315b the second order symbols perform symbol mapping

Second order symbols, e.g., lower order symbol mapping. The first order symbol mapper 1315a maps the sub bit streams output from the first order demultiplexer 1313 to the symbols, and the second order symbol mapper 1315b maps the sub bit streams output from the second order demultiplexer 1313b to the symbols.

[0166] The symbol merger 1317 combines the symbols mapped by the first order symbol mapper 1315a and the second order symbol mapper 1315b to one symbol stream and outputs the symbol stream.

[0167] As described above, in LDPC, the error correction capabilities of the bits may be changed depending on the location of the bits in the error-correction-coded block. Accordingly, if the bit interleaver and the demultiplexer are controlled in accordance with the characteristics of the LDPC encoder 125 such that the order of the bits configuring the cell word changes, then the bit correction error capability can be maximized.

[0168] FIG. 19 is a view showing a different embodiment of each of the symbol mappers 131a and 131b. The embodiment of this drawing is similar to the embodiment of FIG. 18 except that the first order power calibration unit 1316a and the second order power calibration unit 1316b are further included.

[0169] The first order power calibration unit 1316a calibrates the power of the symbols mapped by the first order symbol mapper 1315a according to the size of the constellation and outputs the calibrated symbols. The second order power calibration unit 1316b calibrates the power of the symbols mapped by the second order symbol mapper 1315b depending on the size of the constellation and sends the calibrated symbols. Accordingly, although the symbol mapping scheme is changed in one PLP or

53 / 55P29302EN00 is changed among the plurality of PLPs, if the symbol power is set according to the size of the constellation, the receiver signal reception performance can be improved.

[0170] The symbol merger 1317 combines the symbols calibrated by the power calibration units 1316a and 1316b and outputs one symbol stream.

[0171] FIG. 20 is a view showing the concept of bit interleaving by the bit interleavers 1312a and 1312b of FIG. 18 and 19.

[0172] For example, the input bits are stored and read from memory in the form of a matrix having a predetermined number of rows and columns. When the input bits are stored, first, the bits are stored in the first column in the row direction, and if the first column is full, the bits are stored in another column in the row direction. When the stored bits are read, the bits are read in the column direction and, if all bits stored in the first row are read, the bits in another row are read in the column direction. In other words, when bits are stored, the bits are stored in rows so that the columns are filled serially. And when the stored bits are read, the stored bits are read in columns from the first row to the last row serially. In this figure, MSB means the most significant bit and LSB means the least significant bit.

[0173] To map the LDPC error-correction-coded bits to symbols of the same length of the error-correction block unit at different coding rates, the bit interleavers 1312a and 1312b can change the number of rows and columns of the memory according to the types of the symbol mappers 1315a and 1315b.

[0174] Fig. 21 is a view showing an example of the number of rows and columns of the memory of interleavers 1312a i

53 / 55P29302PL00

1312b bits according to the types of symbol mappers 1315a and 1315b, if the LDPC mode is the normal mode.

[0175] For example, if the symbol mapper 1315a maps the bits to 256QAM symbols, the first order interleaver 1312a interleaves the bits by a memory having 8100 column rows.

If the symbols are mapped by 64QAM, the first order interleaver 1312a interleaves the bits by a memory having 10800 rows and 6 columns. If the symbols are mapped by 16QAM, the first order interleaver 1312a interleaves the bits by a memory having 16200 rows and 4 columns.

[0176] For example, if the symbol mappers 1315a and 1315b map the bits to the Hyb128-QAM symbols, the first order interleaver 1312a and 1315b interleave the bits using memory having 4860 rows and 8 columns, the second order interleaver 1312b interleaves the bits using memory having 4320 rows and 6 columns.

[0177] Similarly, if symbol mappers 1315a map symbols with Hyb 32-QAM, first order interleaving 1312a interleaves bits using memory having 6480 rows and 6 columns, second order interleaver 1312b interleaves bits using memory having 6480 rows and 4 columns.

[0178] Fig. 22 is a view showing an example of the number of rows and columns of memories of the bit interleavers 1312a and 1312b according to the types of the symbol mappers 1315a and 1315b, if the LDPC mode is the short mode.

[0179] For example, if the symbol mapper 1315a maps the bits to 256QAM symbols, the first order interleaver 1312a interleaves the bits by a memory having 2025 rows and 8 columns. If the symbol mappers 1315a and 1315b map the symbols using Hyb128QAM, the first order interleaver 1312a interleaves the bits using a memory having 1215 rows and 8 columns,

And the second order interleaver 1312b interleaves the bits using a memory having 1080 rows and 6 columns.

[0180] If the bit interleaving is performed with respect to the error-correction-coded block, the locations of the bits in the error-correction-coded block may be changed.

[0181] FIG. 23 is a diagram showing the idea of ​​another embodiment of interleaving a bit interleaver. In the embodiment shown in this drawing, when the bits are stored in memory, the bits are written in column direction. When the written bits are read, the bits from the cyclically shifted locations are read in a row direction. In each row, the bits written in each row are shifted cyclically. If the bits are written or read by a circular shifting method relative to the row or column of the memory, this is called twisted bit interleaving. This embodiment relates to a twisted bit interleaving method using a bit reading method after the bits are shifted one column in a row direction. Instead of moving the saved bits in memory, the bit reading point in memory or the bit writing point in memory may be moved.

[0182] In this embodiment, N denotes the length of the error correction coded block and C denotes the length of the column. When bits are written, bits are written in the first column (represented by shading) in the order 1, 2, 3, 4, ..., and C and bits are written in the second column in the order C + 1, C + 2, C +3, ....

[0183] Written bits are twisted in a row-by-column direction.

[0184] If the written bits are read, the twisted bits are read in the row direction. For example, in this embodiment, the bits are read in the first row

In the order 1, C + 1, the bits are read in the second row in the order X1, 2, C + 2, ... (X1 is the bit in the first column of the second row). Bits are read row by row and the cyclically shifted bits are read. Of course, instead of moving the stored bits in memory, the reading point of the bits stored in memory may be moved.

[0185] FIG. 24 is a view showing another embodiment of bit interleaving. In this embodiment, N denotes the length of the error correction coded block and C denotes the length of the column. When bits are written, bits are written in the first column in the order 1, 2, 3, 4, ..., C-1, and C and bits are written in the second column in the order

C + 1, C + 2, C + 3, ....

[0186] The recorded bits are double-twisted in a row direction two columns by two columns. If the written bits are read, the bits shifted cyclically by two columns are read in the column direction in each row. This method can be called a double-twisted bit interleaving method.

[0187] FIG. 25 is a view showing another embodiment of bit interleaving. In this embodiment, N denotes the length of the error correction coded block and C denotes the length of the column. Bits are written in the first column in the order 1, 2, 3, 4, ..., C-1, and C and bits are written in the second column in the order C + 1, C + 2, C + 3, ... .

[0188] When the written bits are read, in the first region of the rows, the bits can be read by the twisted bit interleaving method.

[0189] In the second region of the rows, the bits can be read by the double-stranded interleaving method.

[0190] In the third region of rows, the bits can be read by the twisted bit interleaving method.

[0191] If the bits are interleaved by at least one method, a twisted method of interleaving

In a bit and double-stranded interleaving method, the bits in the error-correction-coded block may be mixed more randomly.

[0192] FIG. 26 is a view showing the idea of ​​multiplexing the input bits of demultiplexers 1313a and

1313b.

[0193] The bit interleavers 1312a and 1312b interleave the input bits x0, x1, ..., and xn-1 and output the interleaved bits. The interleaving method has already been described above.

[0194] Demultiplexers 1313a and 1313b demultiplex the interleaved bit streams. The demultiplexing method may vary according to the error correction coding efficiency of the error correction coding method and symbol mapping method of the symbol mapper. If the symbol method of the symbol mapper is QPSK, the input bits, for example, are interleaved into two sub streams and the symbol mapper maps the two sub streams to the symbols so that they correspond to the real axis and the imaginary axis of the constellation. For example, the first bit y0 of the demultiplexed first sub stream corresponds to the real axis and the first bit y1 of the demultiplexed second sub stream corresponds to the imaginary axis.

[0195] If the symbol method of the symbol mapper is 16QAM, the input bits, for example, are demultiplexed to four sub frames. The symbol mapper selects the bits contained in the four sub streams and maps the selected bits to the symbols so that they correspond to the real axis and the imaginary axis of the constellation.

[0196] For example, the bits y0 and y2 of the demultiplexed first and third sub streams correspond to the real axis and the bits y1 and y3 of the demultiplexed second and fourth sub streams correspond to the imaginary axis.

[0197] Similarly, if the symbol method of the symbol mapper is 64QAM, the input bits may be

53 / 55P29302EN00 demultiplexed to six bit streams. The symbol mapper maps six substreams to the symbols so that they correspond to the real axis and the imaginary axis of the constellation. For example, the demultiplexed first, third and fifth bit streams y0, y2 and y4 correspond to the real axis, and the demultiplexed second, fourth and sixth bit streams y1, y3 and y6 correspond to the imaginary axis.

[0198] Similarly, if the symbol method of the symbol mapper is 256QAM, the input bits may be demultiplexed to eight bit streams. The symbol mapper maps eight substreams to the symbols so that they correspond to the real axis and the imaginary axis of the constellation. For example, first, the demultiplexed first, third, fifth and seventh sub streams y0, y2, y4 and y6 correspond to the real axis, and the demultiplexed second, fourth, sixth and eighth sub streams bits y1, y3, y6 and y7 correspond to the imaginary axis.

[0199] If the symbol mapper maps the symbols, the sub streams demultiplexed by the demultiplexer may be mapped to bit streams of the real axis and the imaginary axis of the constellation.

[0200] The bit interleaving method described above, the demultiplexing method and the symbol mapping method are exemplary and the various methods can be used as a method of selecting bits in sub streams so that the sub streams demultiplexed by the demultiplexer can correspond to the real axis and the imaginary axis of the constellation.

[0201] The word cells mapped to the symbols may vary according to any one of the error-corrected bit streams according to the code rate, the method of interleaving the bit streams, the demultiplexing method and the symbol mapping method. The MSB cell word is larger than the LSB cell word in decoding error correction reliability. Although the bit reliability of the specific block location

Coded error correction coding is low, the bit reliability can be improved by the symbol demapping process if the cell word bit is located in the MSB or adjacent to the MSB.

[0202]

Accordingly, although the bit reliability can be efficiently mapping process and and can be adjusted encoded according to the characteristics of the H matrix used in the LDPC irregular coding method, the error correction varies transmitted / received by the symbol mapping of the system performance inverse symbol.

[0203] FIG. 27 is a view showing an embodiment of demultiplexing an input stream by a demultiplexer.

[0204] If the symbol mapping method is QPSK, two bits are mapped to one symbol and the two bits of one symbol unit are demultiplexed in order of the bit indexes (indexes 0 and 1 of b).

[0205] If the symbol mapping method is 16QAM, 4 bits are mapped to one symbol and the four bits of one symbol unit are demultiplexed according to the calculation results of modulo-4 bit indexes (indexes 0, 1, 2 and 3 with b).

[0206] If the symbol mapping method is 64QAM, 6 bits are mapped to one symbol and six bits of one symbol unit are demultiplexed according to the calculation results of modulo-6 bit indexes (indexes 0, 1, 2, 3, 4 and 5 with b).

[0207] If the symbol mapping method is 256QAM, 8 bits are mapped to one symbol and eight bits of one symbol unit are demultiplexed according to the calculation results of modulo-8 bit indexes (indexes 0, 1, 2, 3, 4, 5, 6 and 7 zb).

[0208] The demultiplexing order of the sub streams is exemplary and may be modified.

53 / 55P29302EN00 [0209] FIG. 28 is a view showing an example of the demultiplexing type according to the symbol mapping method. The symbol mapping method includes QPSK, 16QAM, 64QAM and 256QAM, and the demultiplexing type includes types one to six.

[0210] The first type is an example in which the input bits successively correspond to even-numbered indexes (0, 2, 4, 8, ...) (or the real axis of the constellation) and successively correspond to the odd-numbered indexes (1, 3, 5, 7, ...) (or the imaginary axis of the constellation). Hence, demultiplexing of the first type bits can be represented by the demultiplexing identifier 10 (binary number 1010; location 1 is the location of the MSB corresponding to the real axis and the imaginary axis of the constellation).

[0211] The second type is an example in which demultiplexing is performed in reverse order of the first type, i.e., LSB input bits successively correspond to indexes with even numbers (6, 4, 2, 0) (or real axis of the constellation) and index with odd numbers ( 1, 3, 5, 7, ...) (or the imaginary axis of the constellation). Hence, demultiplexing of the second type bits may be represented by the demultiplexing identifier (binary number 0101).

[0212] The third type is an example in which the input bits are arranged such that the bits of both ends of the codeword become the MSB. The input bits are rearranged to fill the code word at both ends of the code word. Hence, demultiplexing of the third type bits can be represented by the demultiplexing identifier 9 (binary number 1001).

[0213] The fourth type is an example in which the input bits are arranged such that the center bit of the codeword becomes MSB. The input bit is first placed in the middle location of the codeword and the remaining bits are then rearranged towards both ends of the codeword

53 / 55P29302EN00 in the order of the input bits. From this d, the demultiplexing of the fourth type bits may be represented by the demultiplexing identifier 6 (binary number equal to [0215] As described vary according to

0110).

[0214] The fifth type is an example in which bits are demultiplexed such that the last bit of the codeword becomes MSB and its first bit becomes LSB, and the sixth type is an example in which the bits are rearranged so that the first bit of the codeword takes on MSB values, and its last bit becomes LSB values. Hence, demultiplexing of the fifth type bits can be represented by demultiplexing identifier 3 (binary number 0011), and demultiplexing of the sixth type bits can be represented by demultiplexing identifier 12 (binary number 1100).

above, the demultiplexing type may with the symbol mapping method or code rate of the error correction coding method. That is, another type of demultiplexing can be used if the symbol mapping method or coding efficiency changes.

[0216] FIG. 29 is a view showing an embodiment of demultiplexing an input bit stream according to the type of demultiplexing. This embodiment may include bit interleavers 1312a and 1312b, demultiplexers 1313a and 1313b, and mappers 1315a and 1315b.

[0217] The bit interleavers 1312a and 1312b interleave the PLP service streams with the coded error correction. For example, bit interleavers 1312a and 1312b may perform bit interleaving in error-correction-coding units according to the error-correction-coding mode. The bit interleaving method has already been described above.

[0218] Demultiplexers 1313a and 1313b may include first type demultiplexers 1313a1 and 1313b1,

..., and

Demultiplexers 1313a2 and 1313b2 of the n-th type. In this case, n is an integer. Methods for demultiplexing bits with n types of demultiplexers are in accordance with the types shown in FIG. 17. For example, demultiplexers of the first type may correspond to demultiplexing of bits (1100) of the first type and demultiplexers of the second type (not shown) may correspond to demultiplexing of bits (0011) Demultiplexer 1313b of the n-th type input bit stream according to the bits of the n-th type (e.g. identifier and sends the demultiplexed stream and 1313b3 receive a second type selection signal. demultiplexed with 1100 bit demultiplexing. The demultiplexer type 1313a3 selectors suitable for the input bits and output the demultiplexed bit stream according to any one of the first to nth types and the demultiplexer selection signal. The demultiplexer selection signal may change according to the error correction coding efficiency and constellation symbol mapping method. Accordingly, the demultiplexing type may be determined according to the coding efficiency of the symbol mapping method, e.g., according to the symbols mapped to the constellation or / and the error correction coding efficiency according to the demultiplexer selection signal will be described hereinafter.

[0219] The mappers 1315a and 1315b may map the demultiplexed sub bit streams to the symbols according to the error correction or / and the constellation. Detailed signal selection symbols.

[0220] FIG. 30 demultiplexing, the demultiplexer shows which is and output a mapped view showing the type determined according to the symbol mapping.

coding efficiency with error correction method

[0221] In the 4QAM symbol mapping method, even when the coding efficiency cr of the LDPC error correction coding method is any of, 1/4, 1/3, 2/5, 1/2, 3/5, 2/3 , 3/4, 4/5, 5/6, 8/9 and 9/10, the bit stream may be demultiplexed according to all types of demultiplexing (denoted by all).

16QAM symbol mapping, if the LDPC error correction coding method is 1/4, 1/3, 2/5 and 1/2, the symbols can be mapped without performing bit interleaving and bit demultiplexing (denoted by No-Int and NoDemux ). If the error correction coding efficiency is 3/5, the bit may be demultiplexed according to any of 10 and 12 demultiplexing. If the error correction is 2/3, 3/4, 4/5, [0222] In the method, the coding efficiency of identifiers 9, the coding efficiency

5/6, 8/9 and 9/10, demultiplexed demultiplexing. [0223] In the method, the input bit stream may be according to the identifier 6

64QAM symbol mapping, if the LDPC error correction coding efficiency is 1/4, 1/3, 2/5 and 1/2, the symbols can be mapped without performing bit interleaving and bit demultiplexing. If the coding efficiency is 3/5, the bits may be demultiplexed according to any of the demultiplexing identifiers 9 and 10. If the coding efficiency is 5/6, 8/9 and 9/10, the bits may be according to identifier 6

2/3, 3/4, 4/5, demultiplexed demultiplexing 6 [0224] In the method

256QAM symbol mapping, if the LDPC error correction coding efficiency is 1/4, 1/3, 2/5 and 1/2, the symbols can be mapped without performing bit interleaving and demultiplexing the bits. If the code rate is 3/5, the bits can be demultiplexed according to identifier 9

Demultiplexing. If the coding efficiency is 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10, the bits may be demultiplexed according to the demultiplexing identifier 6.

[0225] As described above, the bit demultiplexing type may vary according to the code rate used for the error correction coding and the symbol mapping method. Accordingly, the error correction capability of the bit located at a particular location of the error-correction-coded block can be adjusted by mapping the demultiplexed sub streams to the symbols. Accordingly, it is possible to optimize resistance in the bit level.

[0226] FIG. 31 is a view showing an example of expressing the demultiplexing method by an equation. For example, if the symbol mapping method is QPSK, the input bits (xi xN / 2 + and correspond to the demultiplexed bits y0 and y1. If the symbol mapping method is 16QAM, the input bits^x2n +^x3 N +, and^xand^xn_{and +}

- + 1 - + and - + i

V 4 4 4 J correspond to the demultiplexed bits y0, 4 4 4 y1, y2 and y3.

[0227] If the symbol mapping method is 64QAM, input bits ^X4N. &gt;^X5N. &gt;^X2N. &gt;^X3N.&gt; ^Xand, ^X^

V 6 6 6 6 6 J demultiplexed bits y0, y1, y2, y3, y4 the symbol mapping method is 256QAM, correspond and y5. If the input bits

--l · and - Η i

V 8 8 correspond to demultiplexed ones. . . · + And --l · i

8 8 8 8 J bits y0, y1, y2, y3, y4, y5, y6 and y7.

[0228] In this case, N denotes the number of bits mapped to the symbols with respect to the input of the bit interleaver.

[0229] FIG. 32 is a view showing an example of mapping a symbol by a symbol mapper. For example, in the QPSK symbol mapping method, symbols to

The constellation values ​​correspond to the value of bit y0 of the demultiplexed first sub stream and the value of bit y1 of the demultiplexed second sub stream.

[0230] In 16QAM, the real axis of the symbols in the constellation corresponds to the demultiplexed bits of the first and third sub streams (bits separated from the MSB locations by 0 and 2) and its imaginary axis corresponds to the demultiplexed bits of the second and fourth sub streams (bits separated from the MSB locations by 1 and 3 ).

[0231] In 64QAM, the real axis of the symbols on the constellation corresponds to the demultiplexed bits of the first, third and fifth sub streams (bits separated from the MSB locations by 0, 2 and 4) and its imaginary axis corresponds to the demultiplexed bits of the second, fourth and sixth sub streams (bits separated from locations of MSBs by 1, 3 and 5).

[0232] Accordingly, the bits configuring the symbol may be mapped to the cell word in the demultiplexing order. If the cell word bits are demultiplexed, the MSB and LSB cell words change and the bit resistance can be adjusted, although the reliability of the LDPC error-coded bits change according to the locations.

[0233] FIG. 33 is a block diagram illustrating a MIMO / MISO encoder in accordance with an embodiment of the present invention. The MIMO / MISO encoder encodes the input data using the MIMO / MISO encoding scheme, and sends the encoded data to individual paths. If a terminal device receiving a signal receives a signal transmitted to different paths from one or more paths, it is able to obtain a gain (also called a diversification gain, data field gain, or multiplexing gain).

[0234] The MIMO / MISO encoder 140 encodes service data of each path generated from the frame builder 130, and sends encoded

53 / 55P29302EN00 data to the number A of paths corresponding to the number of output antennas.

[0235] FIG. 34 is a block diagram illustrating a modulator according to an embodiment of the present invention. The modulator includes a first power controller (PAPR Reduce1) 151, a time domain transform unit (IFFT) 153, a second power controller (PAPR Reduce2) 157, and a protective compartment positioning element 159.

[0236] The first power controller 151 reduces the PAPR (average to peak power ratio) of data transmitted to the R number of signal paths in the frequency domain.

[0237] Time domain transform unit (IFFT) transforms received signals in the frequency domain to signals in the time domain. For example, signals in the field converted to signals in an IFFT algorithm. Thus, frequency-domain data may be modulated according to an OFDM scheme.

[0238] The second power controller (PAPR Reduce2) 157 reduces PAPR (Peak-to-Average Power Ratio) of channel data transmitted to the R number of signal paths in the time domain. In this case, a tone reservation scheme and active constellation extension (ACE) can be used to extend the constellation of the symbol.

the frequencies may be in the time domain according to [0239] The protection interval inserter 159 inserts the protection interval into the OFDM symbol output, and outputs the placed result. As described above, the aforementioned embodiment may be performed in each signal of the number R of paths.

[0240] FIG. 35 is a block diagram illustrating an analog processor 160 according to an embodiment of the present invention. The analog processor 160 contains a converter

And sending illustrative example digital-analog (DAC) 161, up-conversion unit 163, and analog filter 165. [0241] DAC 161 converts the input data to an analog signal, and outputs the analog signal. The up frequency conversion unit 163 converts the frequency domain of the analog signal to the RF area. The analog filter 165 filters the signal in the RF area, the filtered RF signal.

[0242] FIG. 36 is a block diagram of an apparatus for receiving a signal in accordance with an embodiment of the present invention. The signal receiving apparatus includes a first signal receiver 210a, a nth signal receiver 210n, a first demodulator 220a, a nth demodulator 220n, a MIMO / MISO 230 decoder, a frame parser 240, and a decoding demodulator 250, and an output processor 260.

[0243] In the case where the reception signal according to the structure of the TFS signal frame, individual services are multiplexed into R channels and then are time-shifted, such that a time-shifted result is transmitted.

[0244] The receiver may include at least one signal receiver for receiving a service transmitted over at least one RF channel. The TFS signal frame transmitted to the number R (where R is a natural number) of RF channels can be transmitted to multi-track / multi-track via A number of antennas. A Antenna has been used for R RF channels, so that the total number of antennas is R x A.

[0245] The first signal receiver 210a is able to select service data transmitted over at least one path among all service data transmitted over different RF channels. For example, the first signal receiver 210a may receive a transmission signal processed by the scheme

MIMO / MISO through various paths.

[0246] The first signal receiver 210a and the nth signal receiver 210n may receive different service data units

53 / 55P29302EN00 transmitted via the number of n RF channels among the various RF channels as a single PLP. Namely, this embodiment shows a signal receiving device capable of simultaneously receiving R number data of RF channels. Thus, if this embodiment receives a single RF channel, only the first receiver 210a is needed.

[0247] The first demodulator 220a and the nth demodulator 220n demodulate signals received at the first and nth signal receiver 210a and 210n according to an OFDM scheme, and output the demodulated signals.

[0248] The MIMO / MISO decoder 230 decodes service data received through different transmission paths according to the MIMO / MISO decoding scheme, and sends the encoded service data to a single transmission path. If the R number of services transmitted through different transmission paths is received, the MIMO / MISO decoder 230 may send a single PLP service data contained in each of the R services corresponding to the number of R channels. If the P number of services is transmitted via the R number of RF channels, and the signals of individual RF channels are received by the A number of antennas, the receiver decodes the P number of services using the total number (R x A) of the receiving antennas.

[0249] The frame parser 240 parses the TFS signal frame including individual services, and outputs the parsed service data.

[0250] The decoding demodulator 250 performs error correction decoding on service data contained in the parsed frame, maps the decoded symbol data to bit data, and outputs the demapping processing result.

[0251] The output processor 260 decodes a stream containing the demapped bit data, and outputs the decoded stream.

[0252] In the above-mentioned description, each frame parser 240, and decoding demodulator 250, and output processor 260 receives different service data units as much as the number of PLPs, and performs signal processing on received service data.

[0253] FIG. 37 is a block diagram illustrating a signal receiver according to an embodiment of the present invention. The signal receiver may include a tuner 211, a down signal frequency converter 213, and an analog-to-digital converter (ADC) 215.

[0254] Tuner 211 performs hopping of certain RF channels capable of transmitting user-selected services on all RF channels when the PLP is contained in different RF channels, and outputs the hop result. Tuner 211 performs hopping of the RF channels contained in the TFS signal frame according to the input center frequencies of the RF band, and at the same time tunes the appropriate frequency signals so that it outputs tuned signals. If the signal is transmitted to the A number of multiple paths, tuner 211 performs tuning to the corresponding RF channel, and receives the receiving signals through the A number of antennas.

[0255] The down signal frequency converter 213 performs the frequency conversion of the signals down the frequency signal of the RF band tuned by the tuner 211, and outputs the result of the frequency conversion of the signals down. ADC 215 converts an analog signal to a digital signal.

[0256] FIG. 38 is a block diagram illustrating a demodulator according to an embodiment of the present invention. The demodulator includes a frame detector 221, a frame synchronizing unit 222, a compartment removing element 223 (transforming unit 224 in the FFT domain), a channel estimator 225, a channel equalizer 226, and a signaling information extractor

227.

safety, frequency

[0267] If the demodulator obtains service data transmitted to a single PLP stream, the next signal demodulation will be performed. A detailed description will be provided later.

[0258] The frame detector 221 identifies a delivery system of a reception signal. For example, the frame detector 221 determines whether the reception signal is a DVB-TS signal or not. And, the frame detector 221 may also determine whether the reception signal is a TFS signal frame or not. The frame synchronizing unit 222 obtains synchronization in the time and frequency domain of the TFS signal frame.

[0259] The guard interval controller 223 removes the guard interval located between the OFDM symbols from the time domain. A frequency domain converter (FFT) 224 converts a reception signal to a frequency domain signal using an FFT algorithm such that it obtains frequency domain symbol data.

[0260] The channel estimator 225 performs channel estimation of a reception channel using a pilot symbol contained in symbol data of the frequency domain. The channel equalizer 226 performs channel equalization of reception data using channel information estimated by the channel estimator 225.

[0261] The signaling information extractor 227 may obtain the signaling information of the physical layer established in the first and second pilot signals contained in channel-equalizing reception data.

[0262] FIG. 39 is a block diagram illustrating a MIMO / MISO decoder in accordance with an embodiment of the present invention. The signal receiver and demodulator are designed to process the signal received in a single path. If the signal receiver and demodulator receive PLP service data providing a single service through different paths of different antennas, and demodulate PLP service data, a decoder

53 / 55P29302PL00

230 MIMO / MIMO sends a signal received in different paths as service data transmitted to a single PLP. Thus, the MIMO / MISO decoder 230 may obtain a diversification gain and a multiplexing gain from service data received in the respective PLP.

[0263] The MIMO / MISO decoder 230 receives a multi-path transmission signal from various antennas, and is able to decode a signal using a MIMO scheme capable of recovering each reception signal as a single signal. Otherwise, the MIMO / MISO 230 decoder is able to recover a signal using the MIMO scheme, which receives the multi-path transmission signal from a single antenna and recovers the received multi-path transmission signal.

[0264] If the signal is transmitted via the R number of RF channels (where R is a natural number), the MIMO / MISO decoder 230 can decode signals received via the A number of antennas of individual RF channels. If the A value is "1", the signals can be decoded using the MISO scheme. If the A value is greater than "1", the signals can be decoded using the MIMO scheme.

[0265] FIG. 40 is a block diagram illustrating a frame parser according to an embodiment of the present invention. The frame parser includes the first 241a frequency deinterleaver, the 24th frequency 241r deinterleaver, the 243 frame parser, the 245a first time deinterleaver, the 245p first time deinterleaver, the 247a first symbol demapper, and the th symbol demapper. The value "r" may be determined by the number of RF channels, and the value "p" may be determined by the number of streams transmitting PLP service data generated from frame parser 243.

[0266] Thus, if the p number of services is transmitted to the p number of PLP streams through the R number of RF channels, a frame parser

53 / 55P29302EN00 contains the number r of frequency interleavers

<td>vice versa, the number of p</td><td>time</td><td>items</td><td colspan="2">interweaving</td>

<td>vice versa, and the number of p</td><td>items</td><td colspan="2">mappers</td><td>vice versa</td>

<td>symbols.</td><td></td><td></td><td></td><td></td>

<td>[0267] Together with</td><td>first</td><td>channel</td><td>RF</td><td>first</td>

<td colspan="3">frequency interleaver</td><td>241</td><td>performs</td>

<td>reverse interleaving</td><td>data</td><td>input</td><td>in</td><td>the field</td>

frequency, and outputs the deinterleaving result.

[0268] The frame parser 243 parses the TFS signal frame transmitted to various RF channels using TFS signal frame planning information, and parses PLP service data contained in the slot of a specific RF channel containing the desired service. The frame parser 243 parses the TFS signal frame for receiving specific service data provided to different RF channels according to the structure of the TFS signal frame, and outputs the first path PLP service data.

[0269] The first time de-interleaver 245a performs data interleaving the PLP service of the first time domain path. The first symbol demapper 247a specifies the service data mapped to the symbol to be bit data, so that it can send the PLP conscience associated with the first path PLP service data.

[0270] Provided that the symbol data is converted to bit data, and each symbol data includes symbols based on a hybrid symbol mapping scheme, the number of p symbol demappers, each of which includes the first symbol demapper, may specify symbol data. , which are to be bit data using various schemes that map symbols in different symbol input data ranges.

[0271] FIG. 41 is a view showing an embodiment of each of the symbol demappers 247a and 247p. The symbol demapper receives streams corresponding to PLPs from the time interleavers 245a and 245p respectively corresponding to the symbol demappers.

[0272] Each symbol demapper 247a may include a block splitter 2471 and error correction 247p, symbol splitter 2473, first order inverse 2475a, second order inverse 2475b, and bit stream element.

[0273] A correction block splitter 2471 to split the mapping stream mapping connecting 2478 errors may appropriately received

2471 a PLP block of one of the time interleavers 245a and 245p in error correction block units. An error correction block splitter 2471 may split the service stream in a LDPC block unit of normal mode. In this case, the service stream can be split in a state in which four blocks according to the short mode (block having a length of 16200 bits) are treated as an error correction block of one of the blocks according to the normal mode (block with a length of 64800 bits) .

[0274] The symbol splitter 2473 may split the symbol stream in the split error correction block according to the symbol mapping method of the symbol stream.

[0275] For example, the first order demapper 2475a converts the symbols according to the higher order symbol mapping method to the bits. The second order demapper 2475b converts the symbols according to the method of mapping the lower order symbols to bits.

[0276] The bit stream merger 2478 may receive the converted bits and output one bit stream.

[0277] FIG. 42 is a view showing a different embodiment of each of the symbol demappers 247a and 247p. The embodiment of this drawing is similar to the embodiment of FIG. 41 except that it additionally includes a first order power calibration unit 2474a and a second order power calibration unit 2474b.

[0278] The first order power calibration unit 2474a receives the symbols split by the symbol splitter 2473, calibrates the power of the received symbols according to the symbol mapping schemes, sends the calibrated symbols. The power of the received symbols can have a power calibrated according to the size of the constellation based on the symbol mapping methods. The first order power calibration unit 2474a converts the power calibrated according to the power of the initial constellation symbol. The first order demapper 2475a may demap the symbols whose power is calibrated by the first order power calibration unit into bits.

[0279] Similarly, the second order power calibration unit 2474b receives the symbols split by the symbol splitter 2473, the modified calibrated power of the received symbols to the initial power according to the size of the constellation, and sends the modified symbols.

[0280] FIG. 43 is a view showing a different embodiment of each of the symbol demappers 247a and 247p. Each symbol demapper 247a and 247p may include a symbol splitter 2473, first order demapper 2474a, second order demapper 2474a, first order multiplexer 2475a, second order multiplexer 2475b, first bit deinterleaver 2476a, first order bit deinterleaver 2476a 2476b second order and bit stream. In this embodiment, the decoding unit and the connecting element 2478, an example

Demodulating from FIG. 33 includes a first decoder 253, a first de-interleaver 255 and a second decoder 257.

[0281] The symbol splitter 2473 may split the PLP symbol stream according to the method corresponding to the symbol mapping method.

[0282] The first order demapper 2474a and the second order demapper 2474b convert the split symbol stream into bits. For example, the first order demapper 2474a performs the higher order QAM symbol demapping and the second order demapper 2474b performs the lower order QAM symbol mapping. For example, the first order demapper 2474a may perform the 256QAM symbol demapping and the second order demapper 2474b may perform the 64QAM symbol demapping.

[0283] The first order multiplexer 2475a and the second order multiplexer 2475b multiplex the bits mapped to the symbols. The multiplexing methods may correspond to the demultiplexing methods described with reference to FIG. 15 to 18. Accordingly, the demultiplexed sub streams can be converted to one bit stream.

[0284] The first order bit deinterleaver 2476a deinterleaves the bit streams multiplexed by the first order mux 2475a. The second order bit deinterleaver 2476b deinterleaves the bits multiplexed by the first order multiplexer 2475a. The deinterleaving method corresponds to the bit interleaving method. The bit interleaving method is shown in FIG. 12.

[0285] The bit stream merger 2478 may merge the bit streams deinterleaved by the bit interleavers 2476a and 2476b to one bit stream.

[0286] The first decoder 253 of the decoding and demodulation unit may error correction decode the output bit stream according to the normal mode or the short mode and the code rate according to the modes.

[0287] FIG. 44 is a view showing a different embodiment of each of the symbol demappers 247a and 247p. The embodiment of this drawing is similar to the embodiment of FIG. 43 except that it additionally includes a first order power calibration unit 2474a and a second order power calibration unit 2474b. The first order power calibration unit 2474a and the second order power calibration unit 2474b modify the calibrated symbol powers according to the symbol mapping methods and send the modified symbols to the symbol demappers 2475a and 2475b.

[0288] FIG. 45 is a view showing an embodiment of multiplexing a demultiplexed sub stream. In this embodiment, the demappers 2474a and 2474b select the words of cells containing bits.

words

2475a multiplexers and cells according to selected multiplexer

2475b multiplex with a selection signal

Demultiplexed cell words are sent to one of the first 2475a2 and 2475b2 multiplexers to the nth 2475a3 and 2475b3 multiplexers.

[0289] First 2475a2 and 2475b2 multiplexers for the nth 2475a3 multiplexers

2475b3 change the order of the bits in the cell word input signal according to the multiplexer selection signal. The multiplexer selection signal may be changed according to the error correction coding efficiency or symbol mapping method. In one stream and bit streams of the multiplexers, the order of selecting sub streams can be changed according to the selection signal of the multiplexer.

to generate delivered to

[0290] The first demultiplexers 2475a1 and 2475b1 send bit streams of inversely mapped symbols to the one of the first from the first multiplexers 2475a2 and 2475b2 to the nth multiplexers 2475a3 and 2475b3 according to the multiplexer selection signal. The first sub-multiplexers 2475a1 and 2475b1 may receive sub-streams multiplexed by the multiplexers from the first 2475a2 and 2475b2 to n's 2475a3 and 2475b3 and send one stream according to the multiplexer selection signal.

[0291] The cell words including the changed bits are provided to the bit interleavers 2476a and 2476b, and the bit deinterleavers 2476a and 2476b deinterleave the input bits and output the deinterleaved bits.

[0292] FIG. 46 is a block diagram illustrating a decoding demodulator in accordance with an embodiment of the present invention. The decoding demodulator may comprise individual function blocks corresponding to a coding and modulation unit. In this embodiment, the decoding demodulator of FIG. 16 may include a first de-interleaver 251, a first decoder 253, a second de-interleaver 255, and a second decoder 257. The second de-interleaver 255 can be selectively included in the decoding demodulator.

[0293] The first de-interleaver 251 acts as an inner de-interleaver, and is able to perform de-interleaving of the p-th PLP stream generated from the frame parser.

[0294] The first decoder 253 acts as an inner decoder, can perform error correction of de-interleaved data, and can use an error correction decoding algorithm based on the LDPC scheme.

[0295] The second de-interleaver 255 acts as an outer interleaver, and can perform de-interleaving of the error-correction-coded data.

[0296] The second decoder 257 acts as an outer decoder. Data de-interleaved by the second de-interleaver 255 or error-corrected by the first decoder 253 is again error-corrected, such that the second decoder 257 sends the data again subject to error -correction. The second decoder 257 decodes data using an error correction decoding algorithm based on the BCH scheme, such that it sends decoded data.

[0297] The first de-interleaver 251 and the second de-interleaver 255 are able to convert the burst error generated in data contained in the PLP stream into a random error. The first decoder 253 and the second decoder 257 may correct data errors.

[0298] The decoding demodulator represents the operation process associated with the single PLP stream. If there are a number of p streams, the number of p decoding demodulators is needed, or the decoding demodulator can repeatedly decode input data p times.

[0299] FIG. 47 is a block diagram illustrating an output processor according to an embodiment of the present invention. The output processor may include the number of p parsers (251a, ..., 261p) of the baseband frame (BB), the first service connecting 263a, the second service connecting 263b, the first demultiplexer 265a, and the second demultiplexer 265b.

[0300] The parsers (261a, ..., 261p) of the BB band remove the BB band headers from the first to fpPP streams according to the received PLP paths, and output the deleted result. This embodiment illustrates that the service data is transmitted to at least two streams. The first stream is MPEG-2 TS stream and the second stream is GS stream.

[0301] The first service merger 263a calculates the sum of service data contained in payload of at least one frame

BB, so that it sends the sum of service data as a single service stream. The first demultiplexer 255a may demultiplex the service stream, and send the demultiplexed result.

[0302] In this way, the second service merger 263b calculates the sum of service data contained in payload of at least one BB frame, such that it can output another service stream. Second demultiplexer GS-format service stream, service stream.

[0303] FIG. 48 presents

255b may demultiplex and send and the demultiplexed block diagram illustrating multiplexed the transmitted signal transmitting apparatus according to an embodiment of another embodiment of the embodiment of the present invention. The signal transmitting apparatus comprises a service creator 310, a frequency splitter 320, and a transmitter 400. The transmitter 400 encodes or modulates a signal comprising a service stream to be transmitted to each RF band.

[0304] The service creator 310 receives different service streams, different service streams, which are to be multiplexed to individual service streams. planning information, yes, using information sends RF channels, and

The creator of the service 310 sends that it controls the transmitter 400 from scheduling when the transmitter 400 transmits the PLP via various RF channels. With this scheduling information, the service creator 310 modulates the different service frames to be transmitted to different RF channels by the transmitter 400, and transmits the modulated service frames.

[0305] The frequency splitter 320 receives a service stream to be transmitted to each RF band, and splits each service stream into different sub-streams, such that individual RF frequency bands can be allocated to the sub-streams.

[0306] The transmitter 400 processes service streams to be transmitted to individual frequency bands, and outputs the processed received streams. For example, in association with the broadcast mapping of a specific service stream to be to the first RF channel, the first element 410 maps the input stream service data to symbols. The first interleaver 420 interleaves the mapped symbols to prevent a burst error.

[0307] The first symbol inserter 430 can place a signal frame containing a pilot signal (e.g., a scattered pilot signal or a continuous pilot signal) in a modulated signal.

[0308] The first modulator 440 modulates the data interleaved by the signal modulation scheme. For example, the first modulator 440 may modulate signals using an OFDM scheme.

[0309] The first pilot symbol inserter 450 inserts the first pilot signal and the second pilot signal in the signal frame, and is able to transmit the signal frame

TFS.

[0310] Stream service data transmitted to the second RF channel is transmitted to the TFS signal frame via individual blocks 415, 425, 435, 445, and 455 of different paths shown in the transmitter of FIG. 18.

[0311] The number of signal processing paths transmitted from the transmitter 400 may be equal to the number of RF channels contained in the TFS signal frame.

[0312] The first mapper 410 and the second mapper may respectively include demultiplexers 1313a and 1313b, and allow changing the location of MSB and LSB in the cell word mapped to symbols.

[0313] FIG. 49 is a block diagram illustrating an apparatus for receiving a signal in accordance with another embodiment of the present invention. Signal receiving device

53 / 55P29302EN00 may include a receiving unit 510, synchronization unit 520, mode detector 530, equalizer 540, parameter detector 550, de-interleaver 560, demapper 570, and service decoder 580.

[0314] The receiving unit 500 is able to receive the signals of the first RF channel selected by the user from among the signal frame. If the signal frame contains different RF channels, the receiving unit 500 performs hopping of different RF channels, and at the same time can receive a signal containing the selected service frame.

[0315] The synchronization unit 510 obtains the synchronization of the reception signal, and sends the synchronized reception signal. Demodulator 520 is able to demodulate the signal with synchronization obtained. The mode detector 530 may obtain the FFT mode (e.g., 2k, 4k, 8k FFT operating length) of the second pilot signal using the first pilot signal of the signal frame.

[0316] Demodulator 520 demodulates the reception signal in the FFT mode of the second pilot signal. Equalizer 540 performs a channel estimation of the reception signal, and outputs a signal of the achieved channel estimate. The deinterleaver 560 deinterleaves the receive signal with channel equalization. The demapper 570 maps the deinterleaved symbol using a symbol demapping scheme corresponding to a transmission symbol mapping scheme (e.g., QAM).

[0317] The parameter detector 550 obtains the physical parameter information (e.g., Layer-1 (L1) Information) contained in the second pilot signal from the output of the equalizer 540, and transmits the acquired physical parameter information to the receiving unit 500 and the synchronizing unit 510. The receiving unit 500 is able

Change the RF channel to another channel using network information detected by the 550 parameter detector.

[0318] The parameter detector 550 sends the information associated with the service, the service decision selection block 580 decodes the service signal data according to the information associated with the service from the parameter detector 550, and sends the encoded service data. [0319] The demapping element 570 may include multiplexers 2475a and 2475b and outputs the bit stream obtained by restoring the order of the bits whose locations MSB and LSB change according to the error correction coding efficiency and the symbol mapping method.

[0320] Hereinafter, a method for modulating a first pilot signal of a signal frame having at least one RF band and a method and apparatus for receiving the modulated first pilot signal will be described.

[0321] The time-interleaved PLP symbols are transmitted by regions, which are temporally divided in the signal frame. The time-interleaved PLP symbols can be transmitted through regions that are divided in the frequency domain if multiple RF bands exist. Accordingly, if the PLP is transmitted or received, a diversification gain may be obtained. The error correction mode and symbol mapping method can be changed according to services corresponding to transport streams or can be changed in the service.

[0322] The first pilot signal and the second pilot signal are arranged at the start location of the signal frame having such characteristics as the header signal.

[0323] As described above, the first pilot signal included in the signal frame u may include an identifier for identifying the signal frame having the above-described structure. The first pilot signal may include information about the transmission structure indicating whether the signal frame is transmitted over multiple paths or not, and information about the FFT signal mode

53 / 55P29302EN00 following the first pilot signal. The receiver can detect the signal frame from the first pilot signal and receive information about the estimation of the total carrier frequency offset and information about the FFT mode of the data symbol.

[0324] FIG. 50 is a view showing an embodiment of the structure of the first pilot signal. Part A designated as A is a useful part of the first pilot signal. B denotes the same cyclic prefix as the first part of Part A in the time domain, and C denotes the same cyclic suffix as the second part of Part A in the time domain. The first part may be reproduced from the second half of part A and the second part may be reproduced from the first half of part A.

[0325] B and C may be obtained by duplicating the first part and the second part and frequency shifting the duplicated parts respectively. The relationship between B or C and A is as follows.

[Equation 1]

B = onepart (A) · e^{1 jnsiit}C = anotherpart (A) · e^{1 insit} [0326] In the above equation, SH is a frequency shift unit. Accordingly; the frequency shift values ​​of parts B and C can be inversely proportional to the length of parts B and C.

[0327] If the first pilot signal is configured by shifting the frequency of the cyclic prefix (B) and the cyclic suffix (C), the probability that the data symbol is erroneously detected in the header is low, and the probability that the header is mistakenly detected is reduced, despite that the data symbols configuring the PLP and the header configuration symbols are modulated in the same FFT mode.

[0328] If continuous wave (CW) interference is included like an analog TV signal, the probability that

The header was erroneously detected because the DC noise component generated in the correlation process is decreasing. In addition, if the FFT size used for data symbols configuring the PLP is larger than the FFT size used for the message header, the message header detection characteristics can be improved even on a delay propagating channel having a length equal to or greater than the useful portion A of the header symbol. Because both the cyclic prefix (B) and the cyclic suffix (C) are used in the header, the fractional carrier frequency offset can be estimated by the correlation process.

[0329] FIG. 51 is a view showing an embodiment of detecting the signal of the message header shown in FIG. 50 and time shift and frequency shift estimates. This embodiment may be included in the frame detector 221 or the frame synchronization unit 222.

[0330] This embodiment may include a first complex conjugate 601, a complex conjugate 603, first multiplier 605, second multiplier 607, first filter 611, second delay unit 615, third multiplier 609, second filter 613, fourth mechanism multiplier 617, peak search unit 619 and phase measurement unit 621.

[0331] The first delay unit 601 may delay the received signal. For example, the first delay unit 601 may delay the received signal by the length of the useful symbol portion (A) of the first pilot signal.

[0332] The complex conjugate calculation unit 603 may calculate the complex conjugate of the delayed first pilot signal and output the calculated signal.

[0333] The first multiplier 605 may multiply the signal output from the complex conjugate calculation unit 603 by the received signal and output the multiplied signal.

[0334] Since the first pilot signal includes the portions B and C obtained by shifting the useful frequency of the part A, the respective correlation values ​​are obtained by shifting the received signals by the respective frequency shift amounts. In the first pilot signal, part B is a part which is frequency shifted up or frequency shifted down from part A, and C is a part which is frequency shifted up or frequency shifted down from part A.

[0335] For example, if the output of the complex conjugate calculation unit 603 is used, the output of the first multiplier 605 may include a correlation result of part B (i.e. the complex conjugate of part B) and part A (i.e. the complex conjugate of part A).

[0336] The second multiplier 607 may multiply the signal from the output of the first multiplier 605 by the frequency shift amount (denoted by ejnf_SHt) applicable to Part B and send a multiplied signal. [0337] The first filter 611 calculates a moving average during a predetermined period with respect to the signal output from the second multiplier 607. The moving average portion may be the length of the cyclic prefix (B) or the length of the cyclic suffix (C). In this embodiment, the first filter 611 may calculate the average of the signal contained in the length of the part B. Then, as a result of the exit from the first filter 611, the correlation value of parts A and C contained in the part in which the average is calculated, basically becomes zero, and the correlation result of parts B and A remains constant. Since the signal of the part is the shift value multiplied by the frequencies by the second multiplier 607, it is equal to the signal received by duplicating the second half of part A.

[0338] The third multiplier 609 may multiply the signal output from the first multiplier 605 by

53 / 55P29302EN00 frequency shift amount (denoted by ejnf_SHt) applied to Part C and sends a multiplied signal.

[0339] The second filter 613 performs a moving average during a predetermined period with respect to the signal obtained from the third multiplier 609. The moving average portion may have the length of the cyclic prefix (B) or the length of the cyclic suffix (C). In this embodiment, the second filter 613 may calculate the average of the signal contained in the length of the part C. Then, as a result of sending from the second filter 613, the correlation value of parts A and B contained in the part in which the average is calculated, basically becomes zero, and the correlation result of parts C and A remains constant. Because the signal of part C is multiplied by the frequency shift value by the third multiplier 609, it is equal to the signal received by duplicating the first half of part A.

[0340] The length TB of the parts from which the moving average is calculated by the first filter 611 and the second filter 613 is expressed as follows.

[0341] [Equation 2]

TB = k / fSH [0342] where, k is an integer. In other words, the frequency shift fSH unit used in parts B and C can be determined by k / TB.

[0343] The second delay unit 615 may delay the signal output from the first filter 611. For example, the second delay unit 615 delays the signal filtered by the first filter 611 by the length of the part B and outputs the delayed signal.

[0344] The fourth multiplier 617 multiplies the signal delayed by the second delay unit 615 by the signal filtered by the second filter 613 and outputs the multiplied signal.

[0345] The peak search unit 619 searches for the location where the peak value is generated from the multiplied signal obtained from the fourth multiplier 617 and sends the searched location to the phase measurement unit 621. The peak value and location can be used to estimate the time offset.

[0346] The phase measurement unit 621 may measure the changed phase using the peak value and the location output from the peak search unit 619 and output the measured phase. The phase value can be used to estimate the fractional carrier frequency offset.

[0347] Meanwhile, an oscillator for generating the frequency used for performing the frequency shift by the second multiplier 607 and the third multiplier 609 may generate any phase error.

[0348] Even in this case, the fourth multiplier 617 may eliminate the oscillator phase error. The results exiting from the first filter 611 and the second filter 613 and the result exiting from the fourth multiplier 617 can be expressed by the following equation.

[Equation 3] yMAFI = || «1 ⁽ⁿΪ² · ^{e jnΔ + θ}yMAF2 = | \^and2 ⁽ⁿΪ² · ^{e jnf-θ} yprod = | l^andand^(N)|² · | l^and2^{(n) 2} · ^e'^{2n2A f} [0349] where, yMAF1 and yMAF2 respectively represent the outputs of the first filter 611 and the second filter 613, and yProd means the output of the fourth multiplier 617. In addition, a1 and a2 respectively correspond to correlation result levels and Af and oznaczają respectively represent frequency shift and oscillator phase error .

[0350] Accordingly, yMAF1 and yMAF2 may include oscillator phase errors having different characters, but the oscillator phase error is eliminated by a fourth multiplier 617.

53 / 55P29302PL00

Accordingly, the frequency offset Af can be estimated regardless of the oscillator phase error of the signal receiving device.

[0351] The axis clamped frequency offset may be expressed by the following equation.

[Equation 4] yprod [0352] where, the estimated frequency offset Af is 0 &lt;= Af &lt;0.5.

[0353] FIG. 52 is a view showing another embodiment of the structure of the first pilot signal. In the first pilot signal, the frequency shift of the first half of the useful portion A is the cyclic prefix (B) and the frequency shift of the second shift of the useful part A is the cyclic suffix (C). The lengths of the useful part A for generating parts B and C may be, for example, 1/2 the length of part A, while the lengths of B and C may be different.

[0354] FIG. 53 is a view showing the embodiment of detecting the first pilot signal shown in FIG. 52 and measuring the time offset and frequency offset using the detected result. In this embodiment, for convenience of description, B and C respectively denote the cyclic prefix and cyclic suffix obtained by a frequency shift of 1/2 of the length of part A.

[0355] This embodiment includes a first complex conjugate 601, a complex conjugate 603, first multiplier 605, second multiplier 607, first filter 611, second delay unit 615, third multiplier 609, second filter 613, fourth multiplier 617, a peak search unit 619, and a phase measurement unit 621. So, this embodiment is equivalent to the embodiment with

53 / 55P29302PL00

FIG. 51, but the features of the components can be changed according to the length of the part A by which the parts B and C are generated. B means the frequency shifted down from part A and C means the frequency shifted up from part A.

[0356] The first delay unit 601 may delay the received signal. For example, the first delay unit 601 may delay the received signal by 1/2 of the useful length of the symbol portion A of the first pilot signal.

[0357] The complex conjugate calculation unit 603 may calculate the complex conjugate of the delayed first pilot signal and output the calculated signal. [0358] The first multiplier 605 may multiply the signal output from the complex conjugate calculation unit 603 by the received signal and output the multiplied signal.

[0359] The second multiplier 607 may multiply the signal output from the first multiplier 605 by the frequency shift amount (denoted by ejnf_SHt) applied to Part B and sends a multiplied signal.

[0360] The first filter 611 calculates a moving average during a predetermined period with respect to the signal output from the second multiplier 607. The moving average portion may be the length of the cyclic prefix (B). In this embodiment, the first filter 611 may calculate the average of the signal contained in the length of the part B. Then, as a result of the exit from the first filter 611, the correlation value of the parts A and C contained in the part from which the average is calculated, basically becomes zero, and the correlation result of parts B and A remains constant. Since the signal of part B is multiplied by the frequency shift value by the second multiplier 607, it is equal to the signal received by duplicating the second half of part A.

[0361] The third multiplier 609 may multiply the signal output from the first multiplier 605 by the frequency shift amount (denoted by ejnf_SHt) applied to Part C and send a multiplied signal.

[0362] The second filter 613 calculates the moving average during a predetermined period with respect to the signal output from the third multiplier 609. The moving average portion may become the length of the cyclic suffix (C). In this embodiment, the second filter 613 may calculate the average of the signal contained in the length of the part C. Then, as a result of sending from the second filter 613, the correlation value A and B contained in the part from which the average is calculated, basically becomes zero, and the correlation result of the parts C and A remains constant. Because the signal of part C is multiplied by the frequency shift value by the third multiplier 609, it is equal to the signal received by duplicating the first half of part A.

[0363] The second delay unit 615 may delay the signal output from the first filter 611. For example, the second delay unit 615 delays the signal filtered by the first filter 611 by the length of the B + 1 / 2A portion and outputs the delayed signal.

[0364] The fourth multiplier 617 multiplies the signal delayed by the second delay unit 615 by the signal filtered by the second filter 613 and outputs the multiplied signal.

[0365] The peak search unit 619 searches for the location where the peak value is generated from the signal output multiplied from the fourth multiplier 617 and sends the searched location to the phase measurement unit 621. The peak value and location can be used to estimate the time offset.

[0366] The phase measurement unit 621 may measure the changed phase using the peak value and the output

Locator from the peak search unit 619 and output the measured phase. The phase value can be used to fractional estimation of the carrier frequency offset.

[0367] As described above, an oscillator for generating the frequency used for performing the frequency shift by the second multiplier 607 and the third multiplier 609 may generate any phase error. However, even in this embodiment, the fourth multiplier 617 may eliminate the oscillator phase error.

[0368] The results obtained from the first filter 611 and the second filter 613 and the result obtained from the fourth multiplier 617 can be expressed by the following equation.

[Equation 5]

II ί \ || 2 ί2ΠΔ _f + θ ymaf = h (W)^e yMAF2 = 1 \^and2 (^IN)² · ^{e ίΠ}'yprod = | l^andand ² · | l^and2 ² ·^{e ίππ}^^Δ [0369] where, yMAF1 and yMAF2 respectively represent the outputs of the first filter 611 and the second filter 613, and yProd means the output of the fourth multiplier 617. In addition, a1 and a2 respectively correspond to correlation result levels, and Af and Θ respectively represent frequency shift and phase error oscillator.

[0370] Accordingly, yMAF1 and yMAF2 may include oscillator phase errors having different characters, but the oscillator phase error is eliminated as a result of the fourth multiplier 617. Accordingly, the frequency offset Af can be estimated independently of the oscillator phase error of the signal receiving device .

[0371] The axis clamped frequency offset may be expressed by the following equation.

[Equation 6]

53 / 55P29302PL00

<img file="PL2157754T3_D0001.tif" />

[0372] where, the estimated frequency offset At is 0 &lt;= Δ f &lt;1.

[0373] That is, phase aliasing can be generated in the range 0.5 &lt;= Af &lt;1 in frequency shift estimated in [Equation 4], but phase aliasing is not generated in frequency shift estimated in [Equation 6]. Accordingly, the frequency offset can be more accurately measured. The structure of the first pilot signal may be used in the data symbol and the second frequency signal. If such a structure is used, the offset estimation characteristics such as CW interference can be improved and the receiving characteristics of the receiver can be improved.

[0374] FIG. 54 is a view showing an embodiment of detecting the first pilot signal and measuring the time shift and frequency shift using the detected result.

[0375] This embodiment includes a first delay unit 601, a third delay unit 602, a first complex conjugate calculation unit 603, a second complex conjugate calculation unit 604, a first multiplier 605, a fifth multiplier 606, a second multiplier 607, a first filter 611, second delay unit 615, third multiplier 609, second filter 613, fourth multiplier 617, peak search unit 619, and a 621 phase measuring unit.

[0376] In this embodiment, the first delay unit 601 may delay the received signal. For example, the first delay unit 601 may delay the received signal by the length of the cyclic suffix.

[0377] The third delay unit 602 may delay the signal delayed by the first delay unit 601. Na

For example, the third delay unit 602 further delays the signal by a difference between the length of the cyclic prefix and the length of the cyclic suffix.

[0378] The first complex conjugate calculation unit 603 may calculate the complex conjugate of the signal delayed by the third delay unit 602 and output the calculated signal. The second complex conjugate calculation unit 604 may calculate the complex conjugate of the signal delayed by the first delay unit 601 and output the calculated signal.

[0379] The first multiplier 605 may multiply the signal output from the first complex conjugate 603 calculating the received signal and output the multiplied signal. The fifth multiplier 606 may multiply the complex conjugate calculated by the second complex conjugate 604 by the received signal and output the multiplied signal.

[0380] The second multiplier 607 may multiply the signal output from the first multiplier 605 by the frequency shift amount (denoted by ejnf_SHt) applicable to Part B and send a multiplied signal. [0381] The first filter 611 calculates a moving average during a predetermined period with respect to the signal output from the second multiplier 607. The moving average portion may become the length of the used portion (A) of the first pilot signal.

[0382] The third multiplier 609 may multiply the signal output from the second multiplier 604 by the frequency shift amount (denoted by -ejnf_SHt) applied to Part C and sends a multiplied signal.

[0383] The second filter 613 performs a moving average during a predetermined period with respect to the signal output from the third multiplier 609. The moving average portion

53 / 55P29302EN00 can become a useful part A of the first pilot signal.

[0384] The second delay unit 615 may delay the signal output from the first filter 611. For example, the second delay unit 615 delays the signal filtered by the first filter 611 by the length of the useful portion (A) of the first pilot signal and outputs the delayed signal.

[0385] The fourth multiplier 617 multiplies the signal delayed by the second delay unit 615 by the signal filtered by the second filter 613 and outputs the multiplied signal. The fourth multiplier 617 may eliminate the oscillator phase error.

[0386] The operations of the peak search unit 619 and the phase measurement unit 621 are equal to those of the above-described embodiment. The peak search unit 619 searches for the location where the peak value is generated from the output of the signal multiplied with the fourth multiplier 617 and sends the searched location to the phase measurement unit 621. The peak value and location can be used to estimate the time offset.

[0387] FIG. 55 is a view showing an embodiment of a method of transmitting a signal.

[0388] The service stream is converted to a PLP (S110). The PLP can be generated by modulating a service stream such as a transport stream and a GSE packet, in which error correction coding and symbol mapping are performed on the service stream. The modulated service stream may be provided in at least one signal frame and may be transmitted through at least one physical channel as a PLP. For example, the process of modulating the service stream to the PLP can be carried out in the following steps S110a to S110d.

[0389] A service stream such as a transport stream and a GSE packet transfer service is error-correction-coded (S110a). The error correction coding scheme may be changed according to the service streams.

[0390] The LDPC error correction coding scheme may be used as the error correction coding scheme and the error correction coding may be performed at various code rates. Bits that are error-correction-coded according to the specific error-correction-coding efficiency may be included in the error-correction-coded block according to the error-correction-coding mode. If the error correction coding scheme is LDPC, normal mode (64800 bits) and short mode (16200 bits) can be used.

[0391] The service stream with the coded error correction is interleaved (S110b). Interleaving can be performed by varying the directions for writing and reading the bits contained in the coded block with error correction to and from memory. The number of rows and the number of columns of the memory can be changed according to the encoding mode from

Interleaving can be performed in subjected error correction coded.

[0392] The interleaved bits of the service stream are mapped to a Symbol mapping method may be with service streams or in a service stream. For example, a higher order symbol mapping method and a lower order symbol mapping method may be used as the symbol mapping method. When the symbols are mapped, the interleaved bits of the service stream may be demultiplexed according to the symbol mapping method or the error correction coding code, and the symbols may be mapped using the error correction bits. unit of block symbols (S110c). amended in accordance with the demultiplexed sub streams. Next,

The bit sequence of the cell word mapped to the symbols can be changed.

[0393] The mapped symbols are interleaved (S110d). The mapped symbols can be interleaved in a unit of error-correction-coded blocks. Time interleavers 132a and 132b may interleave the symbols in a unit of error-correction-coded blocks. That is, the service stream is interleaved again in the symbol level.

[0394] The transformed PLP is allocated in at least one signal frame, and the message header including the first pilot signal is located in the beginning of the signal frame (S150). PLP allocation can be described as follows.

[0395] The interleaved symbols of the service stream are separated, the separated symbols are allocated to a signal frame having at least one frequency band and comprising slots that are temporally separated in the frequency bands and the message header including the first pilot signal is located in the beginning of the signal frame.

The interleaved service stream symbols may configure the PLP with respect to the service stream to provide the service. PLP configuration symbols can be split and allocated to the signal frame. The PLP can be allocated to at least a signal having at least one band

If multiple frequency bands are placed, PLP configuration symbols may be placed in slots shifted between the frequency bands. The bits contained in the service stream may be placed in the signal frame in a unit of interleaved error-correction-coded blocks.

[0396] The signal frame is converted into a time domain according to an OFDM scheme (S160).

[0397] Cyclic prefix obtained by frequency shifting the first useful portion of the first one frequency frame

The pilot signal and the cyclic suffix obtained by the frequency shift of the second useful portion are placed in the first time domain pilot signal (S170). If the message header is not placed in the frequency domain, the message header including the first pilot signal and the second pilot signal may be placed in the time domain. The first time domain pilot signal may include the useful part, the cyclic prefix of the first useful part and the cyclic suffix of the second useful part. The first part may be the rearmost part or the most forward part of the useful part. The second part may be the frontmost part or the rearmost part of the useful part.

[0398] The signal frame including the first frame signal is transmitted via at least one RF channel (S180).

[0399] Since the useful portion of the first pilot signal includes the frequency-shifted cyclic prefix and cyclic suffix, the signal frame can be easily identified as the structure of the first pilot signal. The time shift or frequency shift can be estimated and compensated using the structure of the first pilot signal.

[0400] FIG. 56 is a view showing an embodiment of a method of receiving a signal.

from a specific signal (S210) band

Frame [0401] A signal is received the frequency of the carrying signal frames can be transmitted over at least one frequency band. The signal may be received from a specific frequency band [0402] From the received signal, a first pilot signal comprising a cyclic prefix obtained by switching the frequency of the first useful portion and a cyclic suffix obtained by switching the frequency is identified.

Of the second useful portion, and the signal frame including PLPs is demodulated by the OFDM scheme using the first pilot signal (S220). The demodulating process using the information set in the first pilot signal will be described in detail later.

[0403] The identified signal frame is parsed (S230). The signal frame may contain at least one frequency band. In the signal frame, the first PLP including the symbol error correction coded blocks to which the service stream is mapped may be allocated to OFDM symbols together with the second PLP containing the error correction coded blocks of the other service stream. If the signal frame contains multiple frequency bands, the PLP error correction coded blocks may be allocated to OFDM symbols that are temporarily shifted across multiple frequency bands.

[0404] The service may be obtained from the PLP of the analyzed signal frame (step S240), in which this process is described in steps S240a to S240c.

[0405] The symbols to which the service stream is mapped are de-interleaved with the parsed signal frame (S240a). De-interleaving can be performed at the symbol level to which the service stream is mapped. For example, time de-interleavers 245a and 245b may de-interleave the error-correction-coded blocks containing the symbols to which the service stream is mapped.

[0406] Then, the deinterleaved symbols are demapped so that a service stream (S240b) is obtained. When symbols are demapped, multiple sub streams obtained by symbol demapping can be sent, sent sub streams can be multiplexed, and the service stream of the correction-coded

53 / 55P29302EN00 errors can be sent. The multiplexing scheme may be changed according to the symbol mapping method and the error correction coding efficiency. The symbol demapping method may be changed in one service stream or according to service streams.

[0407] The service stream is deinterleaved and the deinterleaved service stream is error-correction-coded (240c).

[0408] According to an apparatus for transmitting and receiving a signal and a method of transmitting and receiving a signal according to an embodiment of the present invention, it is possible to easily detect and regenerate the transmitted signal. In addition, it is possible to improve the transmission / reception performance of the transmitting / receiving system.

[0409] FIG. 57 is a flowchart illustrating an embodiment of identifying the first pilot signal and estimating the demodulation procedure offset.

[0410] The first pilot signal includes the cyclic prefix obtained by shifting the frequency of the first portion of its useful portion and the cyclic suffix obtained by shifting the frequency of the second portion of its useful portion. The time offset and frequency offset can be calculated using the first pilot signal as follows.

[0411] The received signal is delayed (S311). For example, the delay portion may be the useful portion of the first pilot signal or 1/2 of the useful portion. Alternatively, the delay portion may be the length of the cyclic prefix or the length of the cyclic suffix.

[0412] The complex conjugate of the delayed signal is calculated (S313).

[0413] The complex conjugate of the received signal and the delayed signal are multiplied (S315). The delayed signal multiplied by the complex conjugate can be

53 / 55P29302EN00 signal having the above-described length. If the delay signal is of the length of a cyclic prefix or cyclic suffix, the complex conjugate of the delayed signal may be calculated.

[0414] The signal multiplied by the complex conjugate is inversely shifted according to the frequency shift of the cyclic prefix (S317). That is, the signal multiplied by the complex conjugate is shifted by the inverse shift value of the frequency shift value of the cyclic prefix signal. That is, a signal that is frequency shifted up is frequency shifted down (or a signal that is frequency shifted down is frequency shifted up).

[0415] Then, the average is calculated with respect to the signal which is inversely shifted according to the frequency shift of the cyclic prefix (S319). The part in which the average is calculated may have the length of the cyclic prefix or the length of the useful portion A of the first pilot signal depending on the embodiments. Since the average is calculated with respect to a signal having the same length along with the received signal, a moving average value can be sent along with the received signal.

[0416] The signal of which the average is calculated is delayed (S321). The delay portion may take the sum of the length of the cyclic prefix and the length of 1/2 the useful period, the length of the cyclic prefix, or the length of the useful portion A of the first pilot signal, according to an embodiment.

[0417] The signal multiplied in the step S315 is inversely shifted according to the frequency shift of the cyclic suffix (S323). The signal multiplied by the complex conjugate is shifted by the inverse shift value

53 / 55P29302EN00 frequency shift value of the cyclic suffix signal. That is, a signal that is frequency shifted up is frequency shifted down (or a signal that is frequency shifted down is frequency shifted up).

[0418] The average is calculated with respect to the signal which is inversely shifted according to the frequency of the cyclic suffix (S325 is calculated with respect to the length of the calculated cyclic useful portion of the first pilot signal in accordance with the embodiments.

with offset Moving average signal corresponding to suffix or length [0419] The signal delayed in the step S321 the signal whose average is calculated in the step S325 are multiplied (S327).

[0420]

The peak location of the multiplied result is searched (S329) and the phase of the signal is measured using the peak

S331

The searched peak value can be used to estimate the time offset and the measured phase can be used to estimate the frequency offset. [0421] In this flowchart, the length of the cyclic suffix, the length of the cyclic prefix and the inverse frequency shift value may be changed.

[0422] According to an apparatus for transmitting and receiving a signal and a method of transmitting and receiving a signal according to the invention, if the PLP configuration data symbol and the message header configuration symbols are modulated in the same FFT mode, the probability that the data symbol is detected by the probability message header the fact that the header is correctly detected is reduced. If continuous wave (CW) interference such as analog TV signal occurs, the probability that it is low and the message is reduced

The message header will be erroneously detected by the noise DC component generated during the correlation.

[0423] According to a device for transmitting and receiving a signal and a method of transmitting and receiving a signal according to the invention, if the size of the FFT used for the data symbol configuring the PLP is larger than the size of the FFT used for the message header, the performance of the message header detection even on the propagating channel can be improved a delay having a length equal to or greater than the length of the portion A of the header symbol. Because both the prefix (B) and the cyclic suffix (C) are used in the header of the message, the fractional carrier frequency offset can be estimated.

[0424] The illustrated pilot structure may not be used for a signal frame including PLP, and if the pilot signal is used for any signal frame, the described effect may be maintained.

useful cyclic [0425] It will be appreciated by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention that are within the scope of the appended claims and their equivalents.

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