Apparatus and methods for multi-channel metering

[0001] The application claims priority of US Provisional Application No. 60 / 737,580, filed November 15, 2005, US Provisional Application No. 60 / 739,375, filed November 23, 2005, and US Provisional Application No. 60 / 813,901, filed June 15, 2006 and is partial continuation of US Patent Application No. 11 / 431.849, filed May 9, 2006, which is separated from US Patent Application No. 11 / 030,417, filed January 6, 2005 (now US Patent No. 7,054,770), which is separated from US Patent Application No. 09 / 795,838, filed February 28, 2001 (currently US Patent No. 6,947,854).

[0002] US 5696501 relates to an electric measuring device and related method. The device has a common node and a number of electrical measuring devices connected to the node. Measuring devices measure power consumption and transmit a signal to the node. The node calculates the power consumed and stores the results in a register.

[0003] EP 1379012 relates to an automated and integrated measuring procedure for reading and transferring the obtained digital data to a remote computer system and the device intended therefor. The device measures power, gas and water consumption, processes the measured data and transmits the data to the position of the delivery company.

[0004] US 2005/0137813 relates to a system and method for directly monitoring and calculating energy consumption. The system has a measuring device connected to the power line and a transponder connected to the measuring device. The transponder receives and transmits data from and to the measuring device via a power line and receives and transmits data from and to a remote computer.

Background and summary [0005] According to the invention there is provided a device for multi-channel electricity measurement as described in claim 1.

[0006] One embodiment of the present invention includes a measuring device that is associated with meters from the Quadlogic ASIC family (see US Patent No. 6,947,854 and US Patent Application Publication No. 20,060,036,388). In particular, this embodiment (hereinafter referred to as the "Energy Guardian" for convenience) is a multi-channel meter that is preferably capable of performing many of the functions of the above-mentioned family of meters and furthermore provides the above-mentioned improvements, features and components.

[0007] Used in at least one embodiment, MiniCloset is a 24-channel measuring device that measures electricity consumption for up to 24 single-phase consumers, 12 two-phase consumers or 8 three-phase consumers. Preferably, one or more Load Control Modules (LCM) are connected to the MiniCloset, discussed below.

[0008] The Energy Guard preferably comprises a MiniCloset measuring head module and two LCMs mounted in a steel box. Relays that allow the consumer of electricity to remotely disconnect and reconnect are also mounted in the box, along with current transformers. See FIG. 1.

[0009] Once installed, the electricity supply line to the electricity consumer is output from the main electricity supplier, passed through an Energy Guard device and routed directly to the consumer's home. The construction and use of the Energy Guard will be clear to the skilled person after reviewing the following description and related figures. Source code is provided in the attached Annex.

[0011] The Energy Guard meters are preferably capable of providing:

(A) Remote disconnection / reconnection: The meter supports full duplex (bidirectional) communication via power line communication ("PLC") and can be equipped with remotely operated relays (60 amp, 100 amp or 200 amp) allowing remote disconnection and reconnecting electricity users.

(B) Theft Prevention: The system is designed with three specific features to prevent theft. First, the Energy Guard device is preferably installed on an electric pole above the medium voltage lines, making it difficult for consumers to access and manipulate. Secondly, since there are no additional signal cables in the system (ie all communication occurs along the power line), any serious communication cable damage is immediately detected. This means that if the communication cable is cut, the service is cut off, which is easily seen. The third anti-theft feature is that the meter can be used to measure transformer energy to confirm total measurements for individual customers. Discrepancies may indicate energy theft.

(C) Detection of adverse effects: The Energy Guard preferably provides two modes of optical detection of adverse effects. Each unit contains light that reflects off a small mirror type sticker. The absence of this reflected light indicates that the box has been opened. This detection will automatically disconnect all customers being measured using the Energy Guard unit. In addition, if the Energy Guard enclosure is opened and the surrounding light enters it, this will also automatically disconnect all customers being measured using the Energy Guard unit. These two modes of detection of side effects work continuously and change many times per second for maximum safety.

(D) Reverse voltage detection: In some cases, the supply company may disconnect the energy to an individual customer and the customer will be able to receive energy from an alternative source. If the plant restored the connection under these conditions, the measuring equipment and / or distribution system could be damaged. The Energy Guard is preferably capable of detecting such abnormal conditions. The Energy Guard can detect any voltage that returns to open disconnection with lines connected to the clients' property. If voltage is detected, the Energy Guard firmware will automatically prevent reconnection.

(E) Prepayments: Prepayments for energy can be made by phone, electronic transaction or in person. The quantity of kWh purchased is transmitted to the meter and stored in its memory. The meter will count down energy showing how much available energy is left to reach zero and disconnect. As long as the consumer continues to buy energy, the service will not be cut off and the supply company will have a daily activity report.

(F) Load containment: As an alternative to disconnection for non-payment or as part of a prepayment system, an Energy Guard meter may allow the supplier to remotely limit

EP 1 960 932 B1 to the supplied power at a set level, causing disconnection after exceeding the load. If the consumer exceeds this load and is disconnected, he can reset the button on the optional remote display unit to restore the load, as long as the connected load is less than the set limit. Alternatively, customers can call the electricity provider hotline to restore the service. This feature allows electricity suppliers to provide electricity for critical systems, for example even in the absence of payment by the customer.

(G) Limiting monthly consumption: Some consumers benefit from subsidized rates and are offered maximum monthly consumption. The Energy Guard firmware allows power to be cut off when a certain level of consumption is reached. However, this type of program is best implemented if advanced consumer notification is provided. This can be achieved either by means of a display at home, thanks to which a message or series of messages notifies consumers that their consumption level is approaching the expected monthly consumption. Alternatively (or in combination), you can design temporary service interruptions as the limit approaches, energy is disconnected for longer periods to notify residents. These planned service interruptions act as a warning to consumers about the impending limit so that they have time to change consumer habits.

(H) Meter approval: The integrated system module is preferably replaceable. This allows easy laboratory re-attestation of the meter accuracy in the event of a billing question by the customer.

(I) Working benefits for use: The Energy Guard has built-in numerous event logs and diagnostic functions, providing service technicians with extensive data for starting and solving problems related to electrical and communication systems. Parameters not related to invoicing include: amps, volts, temperature, harmonic content factor, instantaneous watts, wages and volt amps, V2 hrs, 12 hrs, power factor and phase angle.

[0012] These and other features will be clear to those skilled in the art after reviewing the attached descriptions, program code, and diagrams.

[0013] In one aspect, the invention includes a device for measuring electricity consumption, comprising: means for remote disconnection via power line communications; means for detecting theft of electricity; means for detecting adverse effects; and reverse voltage detection means.

[0014] According to another embodiment, the invention includes a multi-channel electricity measurement device comprising: (a) a measuring head capable of measuring electricity consumption for numerous electricity consumer lines; (b) a transponder communicating with the measuring head and capable of transmitting data received from the measuring head via power line communication to a remote computer and for transmitting data received via communication with power lines from a remote computer to the measuring head; and (c) a load control module communicating with the measuring head and capable of activating the connection and disconnection of each set of relays, each set of relays corresponding to one of the set of electricity consumer lines.

[0015] In various embodiments: (1) the device further includes an adverse reaction detector communicating with the measuring head; (2) the adverse reaction detector contains light and a reflecting surface and the measuring head is suitable for commissioning the load control module to disconnect all consumer lines if the adverse reaction detector provides notification that no reflection of light has been detected by the reflecting surface; (3) the device further includes a box containing a measuring head, a load control module and relays, and wherein the adverse effects detector comprises a surrounding light detector penetrating the box; (4) the device further includes a box containing a measuring head, a load control module and relays, and in which the box is installed on an electric pole; (5) the device further includes means for comparing the transformer energy with the total energy consumed by consumer lines; (6) the device further includes means for detecting reverse voltage flow in consumer lines; (7) the device further includes a computer readable memory communicating with the measuring head and a meter communicating with the measuring head, the meter corresponding to the consumer line and is capable of counting the amount of energy stored in the memory and the measuring head is capable of sending a disconnection signal to the load control module to disconnect the consumer line when the counter reaches zero; (8) the device further includes a computer readable memory communicating with the measuring head, the memory being capable of storing a load line for the consumer line, and the measuring head being capable of sending a disconnection signal to the load control module to disconnect the consumer line when the load limit is disconnected will be exceeded; (9) the device further includes a computer readable memory communicating with the measuring head, wherein the memory is capable of storing the consumption line for the consumer line and the measuring head is capable of sending a disconnection signal to the load control module to disconnect the consumer line when the consumption limit will be exceeded; (10) the transponder is capable of communicating with a remote computer via a medium voltage line; (11) the device further comprises a display unit communicating with the measuring head and capable of displaying data received from the measuring head; (12) the display unit is capable of displaying information regarding energy consumption by the consumer; (13) the display unit is capable of displaying warnings regarding energy consumption by the consumer or suspected energy theft; and (14) the display unit is used to transmit information input by the consumer to the measuring head.

Brief description of the drawings [0016]

FIG. 1 is a block / connection diagram showing a combination of preferred embodiments.

FIG. 2 is a block diagram showing the physical configuration of the preferred embodiments.

FIG. 3A-3B are diagrams of the preferred CPU board for the Scanned Transponder and MiniCloset device.

FIG. 4 is a diagram of the preferred power source for the Scanned Transponder.

FIG. 5 is a diagram of the preferred power source for the MiniCloset device.

FIG. 6 is a diagram of a preferred printed circuit board for returning current information from a transformer to a MiniCloset measuring head.

EP 1 960 932 B1

FIG. 7A-7C are diagrams of a preferred Load Control Module PCB.

FIG. 8A-8D are diagrams of a preferred power board that provides optical detection of side effects.

FIG. 9A-9C are diagrams of the preferred Energy Guard connection board.

FIG. 10 is a diagram of a control printed circuit board used to provide control of relays.

FIG. 11 is a schematic of the preferred Energy Guard base assembly.

FIG. 12 and 13 are diagrams of preferred phase busbars and their construction.

FIG. 14 is a diagram showing the construction and assembly of the zero strip frame.

FIG. 15 shows preferred transition strips; FIG. 16 shows the preferred placement of transition strips.

FIG. 17 and [18] show the preferred design of the receiving module.

FIG. 19 shows a preferred integrated current detection and relay module. FIG. 20 is an exploded view of the preferred integrated current detection module and relays.

FIG. 21 shows exploded views of preferred measurement modules.

FIG. 22 shows the measurement modules placed in the EG [Energy Guard] assembly

Energy Guard] and receiving module.

FIG. 23 is an exploded view of a preferred embodiment of the Energy Guard. FIG. 24 is an exploded view of the preferred EG assembly and base assembly.

FIG. 25 shows a preferred EG system.

FIG. 26 and 27 are preferred diagrams of the measurement module.

FIG. 28 shows the preferred diagrams for a back plate.

FIG. 29 shows preferred power board diagrams.

FIG. 30 shows preferred I / O expansion board diagrams.

FIG. 31 shows preferred CPU board diagrams.

FIG. 32 shows preferred diagrams for a control module.

FIG. 33 shows preferred diagrams of measuring and power circuits for a consumer display module; FIG. 34 depicts preferred CDM display board diagrams.

FIG. 35 is a block diagram of a preferred analog front-end measurement system. FIG. 36 and 37 show preferred DSP implementations.

FIG. 38 illustrates the beneficial features of frequency and response to a phase filter pulse.

FIG. 39 illustrates the introduction of PLC signals with an odd half of harmonics in o

H. FIG. 40 shows 12 possible ways to go beyond the phase of the FFT frame received by the meter with the FFT frame transposed by scanning.

FIG. 41 illustrates advantageous FIR filter specifications.

FIG. 42 shows voltage and current resulting from favorable FFT.

Detailed Description of Preferred Embodiments [0017] In one embodiment, the Energy Guard measurement device includes MiniCloset (i.e., a measurement device for measuring multiple consumer lines); Scanned Transponder; one or more relays capable of disconnecting the service from selected consumers; Load Control Module; and optical means for detecting adverse effects.

[0018] The MiniCloset and Scanned Transponder cited herein are very similar to those described in US Patent No. 6,947,854. This means that although they have been improved over time, their functions and structures relating to this description can be considered the same as those described in the above patent.

[0019] One aspect of the invention involves utilizing the existing multi-channel measurement function found in MiniCloset and adding remote connection and disconnection via a PLC. The provision of such additional functionality required the addition of new hardware and software. The equipment added includes the Load Control Module (LCM) and connection / disconnection relays. A set of auxiliary circuits has been added to route signal routes to and from the meter's main processor - the MiniCloset5 Measuring Head. Software add-ons include code modules that communicate with the added hardware as described in the following tables.

[0021] FIG. 1 is a block diagram of connections from a preferred embodiment. Medium voltage lines A, B, C, and N (zero) supply Distribution Transformer 110. Low voltage lines connect (via current transformers 120) Distribution Transformer 110 with the Energy Guard unit 140. The Energy Guard unit 140 monitors the current transformers 120 and supplies single-phase Consumer lines 1-24.

[0022] FIG. 2 is a block diagram of the preferred structure of the Energy Guard unit 140.

[0023] The scanned Transponder 210 is the preferred data collector for the unit 140, it can be located outside or inside the MiniCloset device and can also be the main data collector for more than one MiniCloset device. The scanned Transponder 210 preferably: (a) checks the data (each communication preferably begins with the verification of the identity of the clock and meter to ensure data integrity); (b) collects data (it periodically collects a block of data from each meter unit, each block containing previously accumulated meter readings, interval readings and event records); (c) stores data (preferably, the data is stored in non-volatile memory for a specified period of time (e.g. 40 days)); and (d) reports data (via PLC, telephone modem, RS-232 connection or other means).

[0024] The slide plate 280 includes a Minicloset measuring head and a load control module 240 that provides control signals for activating the relays. All electronics are preferably supplied from a 250 power source. Back plate assembly 270 contains a plurality (e.g. 24) Current Transformers and relays - grouped in this example as three sets of 8 CT [Current Transformers] and relays . Consumer cables are routed through CTs and connected to the circuit on consumer property 290. Remotely located Scanned Transponder 210 gains access to the Energy Guard measuring head and communicates bidirectionally using communication on the power line carrier.

[0025] The signal flow shown in FIG. 1 and 2 are preferably obtained by implementing various software code modules that work simultaneously to enable remote connection / disconnection capability in the Minicloset device. These program modules, presented in the Annex below, are:

<td>Code Module</td><td>Location</td><td>Function</td>

<td>Icm.def and pic.def</td><td>Control module load</td><td>Starting connection and disconnecting relays.</td>

<td>pulse.c and pulse.h</td><td>Measuring head</td><td>Establishing communication with LCM.</td>

<td>picend.def and</td><td>Measuring head</td><td>Providing control signals to LCM.</td>

EP 1 960 932 B1

<td>picvars.def</td><td></td><td></td>

<td>pulselink.def and pulseoutm.c</td><td>Measuring head</td><td>Provides LCM pulses to use for connecting and disconnecting relays.</td>

[0026] FIG. 3-10 are diagrams of preferred components as described below. Preferred connect / disconnect relays are the K850 series relays, but those skilled in the art will recognize that other relays can be used without departing from the scope of the invention.

<td>Figure</td><td>Scheme</td><td>Detail</td>

<td> 3</td><td>PCB 107D</td><td>Scanned Transponder CPU board and MiniCloset device</td>

<td> 4</td><td>PCB 135C</td><td>Power Source for the Scanned Transponder.</td>

<td> 5</td><td>PCB 144C</td><td>Power Source for the MiniCloset device.</td>

<td> 6</td><td>PCB 146C</td><td>This board returns information from the Current Transformer back to the head MiniCloset measuring device.</td>

<td> 7</td><td>PCB 160A</td><td>Board for Load Control Module.</td>

<td> 8</td><td>PCB 170</td><td>EG power board that adds optical detection of side effects.</td>

<td> 9</td><td>PCB 171</td><td>EG connection plate. Board with routing for signal routing.</td>

<td> 10</td><td>PCB 172</td><td>Control circuit board for controlling Relays.</td>

[0027] In another embodiment, the implementation of the Energy Guard uses the architecture similarity of traditional chopper panels to a multi-channel measurement environment. In the chopper panel, electricity is supplied to the panel and distributed to various consumer circuits via choppers that provide the ability to connect or disconnect consumer circuits.

[0028] In the MiniCloset / Energy Guard device, numerous current transformers measure current in consumer circuits and return this data back to the central processing unit, where the measurement quantities are calculated. However, MiniCloset / Energy Guard has some key differences to the chopper panel. For example, while the choppers are near the consumer's property, an Energy Guard is usually installed near the supply transformer. The advantages offered by this alternative embodiment will be apparent to those skilled in the art. For example, this embodiment offers improved dimensions and overall size compared to the above discussed embodiments. Space is always a limitation when adding hardware to existing electrical installations. This version of the Energy Guard ("EG") with favorable dimensions of 28 "X 22" X 11 "provides the main advantage in situations of space restrictions.

[0029] The following description includes preferred construction details, detailed schematics and software descriptions. As in the above discussed embodiments, this embodiment is used to provide remote disconnection / reconnection operations, prevent theft, detect misuse, reverse voltage detection, prepay and load reduction, and perform meter attestation.

EP 1 960 932 B1 [0030] Constructional details of the preferred EG [0031] In this embodiment, the basic components of EG are:

1. Energy Watch Basics Team

2. Energy Guard team

a. Phase Busbars and Zero Strips

b. Transition Strips

c. Receiving Module

3. Energy Guard Measuring Modules a. Measuring Modules

i. Integrated Current Detection Modules and Relays

4. Energy Guard Electronic Components

a. PCB 203 b. PCB 204

c. PCB 234

d. PCB 235

e. PCB 202

f. PCB 210

g. PCB 230

h. PCB 206

EG Base Assembly [0032] The EG base comprises a housing bottom with screws and retaining washers as a locking mechanism for the upper EG cover, which is connected on one side by means of sling hinges. See FIG. 11. The bottom of the enclosure provides routing for consumer cables.

EG - Phase Busbars assembly [0033] Three aluminum phase busbars are facing the center of the Energy Guard assembly and staggered. See FIG. 12 and 13. This ensures connection with consumer measuring modules by using transition strips. A stepped busbar arrangement is shown in FIG. 13. Busbars are marked in black.

Zero Strips [0034] EG preferably includes 4 zero strips that form the frame for the EG assembly, whereby a path for zero current is provided. This is shown in FIG. 14. The protrusion on the crossbar ensures neutral current from the transformer of the distribution company. Also, there are 2 neutral strips on the motherboard that transfer neutral current to the control module.

Transition Strips [0035] Transition strips complete the mechanical and electrical connection between consumer measuring modules and phase busbars. See FIG. 15. Transition bars for phase A and C are shown in FIG. 15A; transition strips for phase B are shown in FIG. 15B. FIG. 16 shows transition strips marked in black.

Receiving Module [0036] The receiving module is preferably made of plastic and mechanically adopts measuring modules that can be easily fitted into the EG unit. Each EG has 4 receiving modules, which are combined with each other and can contain either 12 two-phase measuring modules or 8 three-phase.

EP 1 960 932 B1

See FIG. 17. The receiving module also provides a mechanical path for the motherboard's zero strip that connects to the control module. See FIG. 18.

Consumer Measurement Modules [0037] Advantageous consumer measurement modules provide the measurements required to measure the consumption of a single-phase, two-phase or three-phase customer. A single module acts as a complete stand-alone meter that can be tested and evaluated as a separate measurement unit. Each module preferably includes an integrated current and relay detection module and electronic measuring components, and provides a connection between the consumer circuit and phase busbars. FIG. 19 shows a preferred integrated current detection and relay module. FIG. 20 is an exploded view of the preferred integrated current detection module and relays.

[0038] FIG. 21 shows exploded views of preferred measurement modules. FIG. 22 shows the measuring modules (marked in black) located in the EG frame assembly and the receiving module.

[0039] FIG. 23 is an exploded view of the Energy Guard, and FIG. 24 is an exploded view of the preferred EG Assembly and EG Basics Assembly.

Electronics [0040] The Control Module boxes preferably contain various PCBs that work simultaneously to collect measurement data from individual measurement modules and communicate on power lines to transmit this data to a host device, such as a Scanned Transponder ("ST").

[0041] FIG. 25 illustrates the preferred Energy Guard system for this embodiment. Each consumer line has a corresponding Measurement Module (PCB 203 and PCB 204, discussed below) (diagrams shown in FIGS. 26 and 27).

[0042] The back plate 2510 shown in FIG. 25 (PCB 234; see FIGURE 28 for a structure diagram) is a common bus that carries signals within the EG. There are two types of possible communication on the Back Board 2510 to enable data transfer from the 2520 Control Module to individual PCB 203 Measuring Modules. This can be achieved either by using the I2C 2-cable option or 1-cable serial option.

[0043] The Control Module 2520 includes a Power Board (PCB 210; see FIGURE 29 for a schematic), which is a power supply board that also has built-in PLC transceiver circuits. The Power Board supplies power to the CPU board and electronic circuit board components 203. The 2520 Control Module also includes an I / O Expansion Board (PCB 230; see FIG. thirty in terms of schematic), which is a board with several I / O extension options that allow communication from the Measurement Modules to the CPU board.

[0044] The Control Module 2520 also includes a CPU Board (PCB 202; see FIGURE 31 for a schematic) that has a built-in Digital Signal Processing (DSP) processor.

[0045] Finally, the Control Module 2520 includes a routing board (PCB 235; see FIGURE 32 for a schematic) with paths and a bushing without any electronic components embedded.

[0046] Each Consumer Display Module (CDM) 2530 is installed in the client's property and can communicate in two directions with the EG installed on the distribution transformer serving the given consumer. Two-way PLC allows

EP 1 960 932 B1 communication between the consumer and the supplier on low voltage lines and enables the supplier to send the consumer regular information, warnings, special information about interruptions in supply, etc. [0047] Each CDM 2530 contains the selected combination of measurement and power source together with PLC circuits on the same board (PCB 240; see FIGURE 33 for a schematic). Each CDM also preferably has a 9-digit display board (PCB 220; see FIGURE 34 for a schematic). This display communicates with EG and presents consumption information, warnings, notes and other messages from the supplier.

Equipment Implementation [0048] In one embodiment, the Energy Guard implements Fast Fourier Transform (FFT) on the PLC communication signal on both ST and meter, and performs detailed harmonic analysis for measurement purposes. This chapter discusses the implementation scheme

Measuring Modules, communication with Control Modules and PLC communication of the Control Module with remotely placed Scanned Transponder.

[0049] Control Module 2520 includes a power source and PLC circuits (PCB 210; see FIGS. 25 and 29); I / O extension (PCB 230; see FIG. 30) and a CPU board called Meter D (PCB 202; see FIG. 31). The power source supplies power to the D meter and I / O extension, and includes PLC transceiver circuits. PCB 235 provides route routing and throughput between different boards.

[0050] The Measuring Module can have two versions: 2-phase or 3-phase. The 2-phase version can be programmed by the software to act as a single 2-phase meter or two 1-phase meters. The 2-phase version includes a B2 meter (PCB 203 schematically shown in FIG. 26), while the 3-phase version includes a B3 meter (PCB 204 schematically shown in FIG. 27). Meter B acts as a slave device to the meter D in the 2520 Control Module. The D and B meters can communicate via the serial ASCII protocol. Different B meters are interconnected via BPB 2510 to 2520, which provides power, J Hz standard and serial communication for the D meter. A preferred DSP motor for the B meter is the Freescale 56F8014VFAE chip. The preferred microprocessor used to implement the CPU on the D meter is that of the ColdFire Integrated Microprocessor family, MCF5207. The use of a specific processor is determined by the requirements of RAM and Flash dictated by the meter version. A separate power source and LCD board complete the electronic part of the D meter as a product. In addition to performing the function of the main device relative to B meters, the D meter is also a 3-phase meter and it measures the total output power of the transformer on which the EG is installed. As part of the anti-theft feature, this total value is compared to the total consumption reported by various B meters.

tkWh, Total transformer output power [0051] The components of the signal streams are as follows:

B2: Two voltage channels, two current channels and no Power Line Carrier Channel (PLC).

B3: Three voltage channels, three current channels and no PLC Channel.

D: Three voltage channels, three current channels and one PLC channel.

[0052] Each stream has a related circuit for performing analog amplification and anti-aliasing.

[0053] Characteristic for the D meter is the preferred implementation of:

• Phase Locked Loop (PLL) for blocking sampling of signal streams for many incoming A / C lines (synchronous sampling per power line).

• Voltage Controlled Oscillator (VCO - Controlled Oscillator) at 90-100 MHz controlled by DSP processor via two PWM modules directly controlling the system clock, thanks to which DSP becomes consistent with PLL.

• a synchronous phase detector that responds only to the fundamental component of the incoming line frequency wave and not to its harmonics.

• Options for carrying out FSK and PSK modulation schemes.

[0054] Each measurement and communication channel preferably includes analog front-end circuits followed by signal processing. For analog circuits, a unique anti-aliasing filter with constant gain is assigned, which ensures tracking of the first order temperature, which eliminates the need to re-calibrate meters when temperature changes occur. This will be discussed below, followed by a description of the preferred implementation of signal processing.

Voltage and Current Analog Signal Chain [0055] An analog front-end system for voltage (current) channels includes voltage (current) sensing elements and an adjustable attenuator behind which the anti-aliasing filter is located. The attenuator reduces the level of the incoming signal in such a way that there is no restriction behind the anti-aliasing filter. The constant gain anti-aliasing filter returns the signal to its full value at the input to the Analog-to-Digital Converter (ADC). For measurement, the anti-aliasing filter cuts off frequencies above 5 kHz. The input data is then provided to the ADC, which is part of the DSP. See FIG. 35, which is a block diagram of the preferred analog front-end measurement system.

[0056] While a typical implementation would include a Programmable Gain Amplifier (PGA) followed by a low gain anti-aliasing filter, in the present embodiment the invention implements an adjustable attenuator followed by a high constant filter strengthened. In addition, the implementation of both anti-aliasing filters on a single chip is the same when using the same Quad Op Amps with 25 ppm resistors and NPO / COG capacitors. This unique implementation by pairing anti-aliasing filters ensures that the phase shifts occurring in both voltage and current channels are completely identical and therefore the accuracy of the power calculations (provided by the product V and I) is not impaired. This provides means for both V and I channels to track temperature changes to first order without recalibrating the meter.

[0057] However, by using PGA together with a low gain filter, the phase shift in the V and I signals cannot be monitored due to temperature. This is because the phase shift introduced by PGA is a gain function.

PLC Voltage, Current and Digital Signal Chain [0058] FIG. 36 is a block diagram of PCB 202; the functions of each block will be obvious to specialists. FIG. 36 shows the favorable implementation of DSP.

[0059] This embodiment preferably uses PLL to block sampling of signal streams for multiple incoming A / C line frequencies. In the above-discussed embodiment, sampling is asynchronous to the power line. In the D meter, there is a 90-100 MHz VCO, which is controlled by a DSP motor via two PWM modules. VCO directly

EP 1 960 932 B1 directs the system clock of the DSP chip (by deactivating the internal PLL) in such a way that DSP becomes an integral part of the PLL. Locking the DSP system clock relative to the power line makes it easy to match the sampling to the power line waveform. The phase detector should operate to respond only to the fundamental component of the incoming 60 Hz wave, not to its harmonics. FIG. 37 is a diagram of a favorable DSP implementation.

[0060] The DSP BIOS or voluntary context switching code provides three stacks, each for background, PLC communication and serial communication. The small micro [processor] communicates with DSP using the I2C controller. The circuit integrated with MSP430F2002 measures power sources, side effects port, battery temperature and voltage. The tasks of MSP430F2002 include:

i. maintaining RTC;

ii. battery voltage measurement;

iii. temperature measurement;

iv. + U power source measurement;

v. DSP reset in case of reduced energy supply;

vi. providing an additional alarm circuit; and vii. providing a 1-second reference for switching to DSP for a time reference for measuring a 1-second reference against a system clock with VCO.

D Meter PLC Communication Signal Chain [0061] A typical installation consists of many EG and ST communicating on power lines. Gauge

D communicates in both directions with the Scanned Transponder remotely located via a distribution transformer. To enable this, this embodiment uses the 10-25 kHz band for PLC communication. The PLC signal is sampled at approximately 240 kHz (212 * 60), synchronously with the voltage on the line, and then the Finite Impulse Response (FIR) filter is used for data decimation. The preferred FIR specifications are listed below:

10-25 kHz band

<td colspan="2">Number of Counts</td><td> 65</td>

<td>blanking attenuation</td><td>bandwidth</td><td>71,23dB</td>

<td>Upper frequency pass</td><td>bandwidth</td><td>25kHz</td>

<td>Lower frequency attenuation</td><td>bandwidth</td><td>35kHz</td>

<td>Sampled at</td><td></td><td> 60 * 4096</td>

<td>End of sampling</td><td></td><td> 30* 2048</td>

[0062] See FIG. 38 for favorable frequency response and pulse response for a phase filter.

[0063] After decimation up to 60 kHz (2¹¹ * 30), decimated data is subjected to 2048-point FFT. The data transfer rate is therefore determined as 30 baud depending on the choice of FIR filters. Each FFT produces two bits approximately every 66 msec. when using FIR in the 10-25 kHz band for communication via distribution transformers.

[0064] To circumvent the communication problem in the presence of noise on the line, the present embodiment preferably implements a unique technique for clear and reliable communication. This is achieved by introducing PLC signals at frequencies that cover the odd half of the harmonics of the frequency lines (60 Hz). This is discussed below for an embodiment using the typical noise spectrum occurring on AC lines in the 12 -12.2 kHz range.

[0065] FIG. 39 illustrates the introduction of PLC signals with an odd half of harmonics by 60 Hz. Since FFT is performed every 30 Hz and the harmonics are separated by 60 Hz, the data bits are in the range corresponding to 201.5th and 202.5th 60 Hz harmonic in 60 Hz. 39. The algorithm considers these two frequency ranges and compares the signal amplitude for determining 1 or 0 in both. This FSK scheme uses two frequencies and gives a data rate of 30 baud. Alternatively, QFSK, which uses 4 frequencies, can be implemented for 60 bauds.

[0066] When passing through transformers, both ST and D meters preferably perform FFT on the PLC and [generate] data signals every 30 Hz in the range of 10-25 kHZ. Because Phase Coupling Loops (PLL) implemented in both ST and meter D are blocked for lines, data frames are also synchronized with the line frequency (60 Hz). However, data frames may have phase shifts due to:

1. various transformer configurations that may occur on the path between the ST and the meter (delta-Wye, etc.); and

2. phase shift caused by the fact that STs are locked in a certain phase, while single- and multi-phase meters can be powered by other phases.

[0067] The signal-to-noise ratio (SNR) is maximum when the meter data frame and the ST data frames are almost perfectly matched. From the meter's point of view, this requires receiving a PLC signal from all possible STs that it can "hear", decoding the signal, searching for SNRs by comparing data frames and then sending a response to the ST, which gives maximum SNR. FIG. 40 shows 12 possible ways out of phase of the FFT frame received by the meter with the FFT ST frame. The dashed lines correspond to 30 degrees of rotation due to the delta transformer in the signal path between the ST and the meter.

[0068] Furthermore, since data frames are available every 30 Hz on a 60 Hz line, there are two possibilities corresponding to 2 possible phases obtained by dividing 60 Hz by 2. Thus there are 24 ways to incorrectly match meter data frames to ST data frames.

[0069] Each ST frame has an odd integer number of carrier frequency cycles. Because the preferred modulation scheme is Frequency Shift Keying (FSK), if there are n cycles to transmit bit 1, bit 0 is transmitted using n + 2 carrier frequency cycles. For the meter, it is crucial to recognize its own 2 cycles at 60 Hz so that it is able to decode its own data bits that are available every 1 / 30th of a second.

[0070] If the meter D decodes signals with incorrectly matched data frames, there is energy that decomposes into adjacent frequencies (separated odd half). If the signal level that falls into the "adjacent" frequency range is lower than the noise level, the signal may be decoded correctly. However, if the spread exceeds the noise level, the ability to distinguish between 1 and 0 decreases and as a result the overall SNR decreases, resulting in a decoding error . Summarizing:

EP 1 960 932 B1

a. If the frames are incorrectly matched, the data bits become unreadable and SNR decreases.

b. When the frequency changes and there are incorrectly matched data frames, there is a substantial amount of energy that scatters into adjacent FFT intervals, which results in colliding other STs in the system that communicate using frequencies in these specific intervals.

[0071] After determining the clock offset corresponding to the highest SNR, the meter locks until a significant change in the SNR ratio, which the meter registers, in which case the process is repeated. Implementation of Measurement in Meter D and B using FFT [0072] While versions of Meter B and Meter D perform a measurement, Meter D is also responsible for collecting measurement information from various B meters via PCB 234. Each data stream in the meters has a related circuit for performing analogue amplification and anti-aliasing. Each section of the analog front-end device has an adjustable attenuator controlled by a higher level code. The data stream is tested at 60 kHz (2¹⁰ * 60) and then the FIR filter is used to decimate the data stream up to ~ 15 kHz (2⁸ * 60). Preferred filter specifications are shown in the table below and in FIG. 41.

<td colspan="2">Number of Counts</td><td> 29</td>

<td>blanking attenuation</td><td>bandwidth</td><td>80,453dB</td>

<td>Upper frequency pass</td><td>bandwidth</td><td>3kHz</td>

<td>Lower frequency attenuation</td><td>bandwidth</td><td>12kHz</td>

[0073] Since only data up to 3 kHz are of interest, preferably a gain drop of 3-12 kHz during FIR decimation is used at a sampling rate of ~ 15kHZ. Frequencies from 0-3 kHz or 12-15 kHz are mapped to 0-3 kHZ. The real part of the FFT is carried out to obtain 2 data streams, which can be further divided into 4 data streams: Real and Imaginary Voltage and Real and Imaginary Current. This is achieved by adding and subtracting positive and negative mirror frequencies for the real and imaginary parts respectively. Since the aliased signal in the 12-15 kHz range falls below 80 dB, accuracy is achieved using the FIR filter discussed above. Alternatively, a 256-point composite FFT can be performed on each phase of a decimated data stream. This gives 2 pairs of data streams: the real part, which is voltage, and the imaginary part, which is current. This approach requires a complex 256-point FFT every 16.667 milliseconds. [0074] The results of any FFT are the voltage and current shown in FIG. 42, where the notation Vm, n denotes the mth harmonic component of the number of the nth cycle. For example, V11 and I11 correspond to the fundamental component of the first cycle and V21 and I21 correspond to the first harmonic component of the first cycle, etc., as shown in FIG 42, which shows FFT frames for voltage, indicating harmonics. [0075] The real and imaginary parts of the harmonic component of any k-th cycle are given as:

K. = ^Re&lt;7 "&gt;) + i); m = 1 ... M i * =^Re(O + i'W »,); * = i ....«

<img file="PL1960932T3_D0001.tif" />

[0076] The imaginary part of the voltage is a measure of the lack of synchronization between the PLL and the frequency of the lines. To calculate the measured values, the calculations are carried out in the time domain. In the time domain, the FFT function gives the flexibility to calculate measurement quantities only using the fundamental component or taking into account harmonic components. When using the complex form of the voltage obtained from FFT, the measured values ​​are calculated as:

<img file="PL1960932T3_D0002.tif" />

W = Re (P) = Re (^) * Re (/_rt ) + Im (U) * Im (F ",) <img file="PL1960932T3_D0003.tif" /> Var = Im (O = Re (U) * WK.) -Re ^) * Im (U)

PowerFactor ~ W / P [0077] However, in the above formulas, when harmonics are included (Vmk &amp; Imk; m = 1 ... M, k = 1 ... n), all measurement quantities include the results for harmonics. On the other hand, when only the basic component (Vlk &amp; Ilk) was used, all calculated quantities represent only the 60 Hz input. By way of example, we presented calculations as soon as the fundamental component was used to perform the calculations. Of all FFT data frames, only Vl and Il were used. The following values ​​were calculated for a given set of N frames and frequency of fline lines:

kWh = jż [Re (F ;,) * Re (/ ") + Im (7") * Im (/ ")] * Δζ, * 1 (Τ 'kVAr = tlWWJ-WW»)] **, * 10 -³

<img file="PL1960932T3_D0004.tif" />

<img file="PL1960932T3_D0005.tif" />

lute

<img file="PL1960932T3_D0006.tif" />

[0078] The power shift factor is shown as:

<img file="PL1960932T3_D0007.tif" />

where W and VA include only the basic components and VAl = VlRMS * IlRMS; where r, iMS.

V 0-1 &amp; Ϊ it-l for N cycles.

[0079] This flexibility allowing either to include or exclude harmonic components when calculating the measurement quantities translates into a significant improvement over the possibilities offered by the above described embodiment. Another feature offered by this embodiment is the calculation of the Harmonic Content Index (THD)

EP 1 960 932 B1

Harmonic Distortion). THD is a measure of harmonic distortion that occurs and is defined as the ratio of the sum of the powers of all harmonics to the power of the fundamental component. For the nth cycle, it was rated as:

<img file="PL1960932T3_D0008.tif" />

Vmm (Imm) means the mth harmonic component of the nth cycle obtained from FFT, where

<img file="PL1960932T3_D0009.tif" />

Consumer Display Module [0080] The consumer display module is installed in the consumer's property, communicates with the Energy Guard near the transformer and includes: PCB 240, power source and PLC circuitry (see FIG. 33); and PCB 220, LCD display (see FIG. 34). In one embodiment, the consumer display unit installed at the consumer's residence is a two-way PLC unit that communicates with EG. For example, not only the supplier can send messages, but also the consumer can request verification of consumption using EG installed on the pole. ANNEX [0081]

EP 1 960 932 B1

LCM.DEF; QLC LCM (Load Control Module) program for PIC 16C63A;

include 'C: \ pictools \ 16c63a.inc'; include 'C: \ pictools \ 16c63.inc';

; Configuration bits

FUSES _BODEN_OFF; Brown-out reset disabled

FUSES _CP_OFF; No codka protect

FUSES _PWRTE_OFF; Disable power-up timer

FUSES _WDT_ON; Watchdog Timer Enabled

FUSES _RC_OSC; Oscillator = RC

<td colspan="3">; Parameter Equates program</td>

<td>Software_type equ</td><td> 7</td><td>; Which PIC program is this? ; 7 = LCM program</td>

<td>Software_version equ</td><td> 2</td><td>; Version #</td>

<td>LCM_base_addr equ</td><td> 16</td><td>; Address of first LCM</td>

<td>Ramstart equ</td><td>020h</td><td>; Begioning of available RAM</td>

<td>RESET_VECTOR</td><td>equ</td><td>0; Location of reset vector</td>

<td>ROM_start equ</td><td>OOSh</td><td>; first avai labie program location</td>

<td>Num_start_bits equ</td><td> 12</td><td>; Number of start bits</td>

; Port definitions

<td>comm_port</td><td>equ</td><td colspan="2">PORT</td>

<td>data_out</td><td>equ</td><td> 3</td><td></td>

<td>data_in</td><td>equ</td><td> 4</td><td></td>

<td>clock_in</td><td>equ</td><td>S</td><td></td>

<td>ctl_portequ</td><td colspan="2">PORT</td><td></td>

<td>driver_enable</td><td>equ</td><td> 0</td><td>; output bit to tum on the drivers</td>

Driver_enable_mask equ 1 «driver_enable; Initialization values ​​for I / O ports

<td>init_TRISA</td><td>equ</td><td>001lOOOOb</td><td>; Data direction for port A</td>

<td>initJTRlSB</td><td>equ</td><td>oooh</td><td>; B port data direction - all ports output</td>

<td>init_TRISC</td><td>equ</td><td>oooh</td><td>; C port data direction - all out</td>

EP 1 960 932 B1 read__ TRISC equ Olfh; C port data direction for jumper read - 0-4 in

Init_comm_port_value equ 1 «data_out + Driver_enable_mask option reg val equ 100011 llb; Option register init value; bit 7 = 1: Port B pullups disabled; bit 6 = 0: Int on falling edge; bit 5 = 0: Timer 0 uses inst clock; · Bit 4 = 0: Timer 0 counts on rising edge; bit 3 = 1: Prescaler used by WDT; bit 2.0.0 = 11 kPrescaler divide by 128

ΝΟΤΕ - interrupts and timer 0 are not used by this program

<td>ms_preset equ 9</td><td> 700</td><td colspan="2">; Time set for millisecond delay</td>

<td>; RAM Iocations</td><td></td><td></td><td></td>

<td>ORG Ram_</td><td>start</td><td></td><td></td>

<td>Reg. Status</td><td>for</td><td> 4</td><td>; status register</td>

<td>ORG</td><td>Status_</td><td>reg</td><td></td>

<td>Status_MSB</td><td>for</td><td> 1</td><td></td>

<td>Clk_timeout_flag</td><td>equ</td><td> 7</td><td>; Timeout waiting for comm clock edge</td>

<td>bad_reset_flag</td><td>equ</td><td> 6</td><td>; Non-POR, non-WDT reset encountered</td>

<td>POR_flag</td><td>equ</td><td> 5</td><td>; Power-on reset detected</td>

<td>WDT_reset_flag</td><td></td><td>equ</td><td>4; WDT reset, not from sleep</td>

<td>Status_LSB</td><td>for</td><td> 1</td><td></td>

<td>CPU reset_flag</td><td>equ</td><td> 7</td><td></td>

<td colspan="2">Need_param_refresh_flag</td><td>equ</td><td> 6</td>

<td>Parity_err_flag</td><td>equ</td><td> 5</td><td></td>

<td>GIobal_cmd_timer</td><td>for</td><td> 1</td><td></td>

<td>Jumper_state</td><td>for</td><td> 1</td><td>; current State of input jumpers</td>

<td>Parameter_reg</td><td>for</td><td> 4</td><td>; Communication parameters</td>

<td></td><td>org</td><td colspan="2">Parameter_reg</td>

<td></td><td>for</td><td> 1</td><td> 9</td>

<td></td><td>for</td><td> 2</td><td> 9</td>

<td></td><td>for</td><td> 1</td><td> 9</td>

Fast communication variables

<td>Comm_state</td><td>for</td><td> 1</td><td>; Stored State of fast comm uart</td>

<td>Wstate</td><td>for</td><td> 1</td><td>; Stored State of fast comm word handler</td>

<td>Comm_bit_count</td><td></td><td>for</td><td>1; Bit counter for fast comm</td>

<td>Comm_buffer</td><td>for</td><td> 1</td><td>; fast comm word buffer</td>

EP 1 960 932 B1

<td>Work_addr</td><td>for</td><td> 1</td><td>; Address read from jumpers</td>

<td>temp</td><td>for</td><td> 1</td><td>; temporaiy register</td>

<td>Tpar</td><td>for</td><td> 1</td><td>; Transverse parity</td>

<td>word_count</td><td>for</td><td> 1</td><td>; Counter for sending and receiving 5-bit words</td>

<td>Command</td><td></td><td>for</td><td>1; Command received over comm link_r</td>

<td>Register_ID</td><td>for</td><td> 1</td><td>; Register specified in comm command</td>

<td>PIC_addr</td><td>for</td><td> 1</td><td>; Address of this PIC chip</td>

<td>Commbuf</td><td>for</td><td> 5</td><td>; Communication buffer</td>

<td>Inputjhold</td><td>for</td><td> 1</td><td>; Tribute to register for comm rcv value</td>

<td>Output_bit__reg</td><td>for</td><td> 4</td><td>; Tribute to register for output bit mask</td>

<td>Flags</td><td>for</td><td> 1</td><td>; Program control flags</td>

<td>Clk_wait_flag</td><td>equ</td><td> 7</td><td>; indicates which clock edge we are waiting for</td>

<td>Global_cmd_flag</td><td></td><td>equ</td><td>6; Processing global command</td>

<td>scratch</td><td>for</td><td> 1</td><td>; Work register</td>

<td>Timeout_ctr</td><td>for</td><td> 2</td><td>; Counter for pulse duration</td>

<td>millisecs</td><td>for</td><td> 1</td><td>; Counter for pulse duration milliseconds</td>

<td>Clk_timeout_ctr</td><td></td><td>for</td><td>2; counter for clock timeout</td>

<td>NPR_timer</td><td>for</td><td> 2</td><td>; counter for need parameter refresh</td>

ORG OaOh; Bank 1 RAM locations

IF $ -land0100h crror - RAM overflow ENDIF

ORG RESET_VECTOR jmp start; Jump to first program location

Start of program space

ORG ROMstart; Initialization

Start setb RPO; point to upper register bank jnb NOT_POR, got_POR; Power on reset, set flags clrb RPO; point to RAM bank 0 jnb NOT_TO, WDT_reset; Watchdog reset setb status_MSB.bad_reset_flag; Indicate unknown reset condition jmp Do_initialize

EP 1 960 932 B1

WDT_reset setb

J^mP got_POR clrb mov clr

Do_initialize mov: clr_loop clr inc jz mov and jnz add jmp

Init State

Status_MSB.WDT_reset_flag do_initialize

RPO; point to RAM bank 0

Status_MSB, # l «PORJlag; Set POR flag Status LSB

F SR, # Ram_start + 2

INDF

FSR lnit_state

W, FSR

In, # 7fH: clr_loop

FSR, # 20h: clr_loop. Point past status flags, Clear RAM location, Increment pointer; If zero, done 1 get pointer; look at 7 LSB's; Not end of segment, continue; Point to next segment; Not last segment, continue machina setb setb mov mov mov

Status_LSB.CPU_reset_flag Status_LSB.Need_param_refreshflag comm_port, # Init_comm_port_value Comm_state, # Edge_wait Comm_bit_count, # N um_start_bits; lndicate CPU reset; lndicate parameter reffesh needed; initialize comm port State; Initialize fast comm State clr clr jmp

PORTB

PORTO

Main_loop; start running main program; Comm Receive routines

Edge_wa.it mov setb dec jz jb jmp

See_edge_one jnb mov mov jmp

Rcv_stop mov mov jnb jmp

Rcv_bits clc! OPTION, # option_reg_val comm_port.data_out Comm_bit_count See_edge_one Input_hold.data_in, Set_edge_wait Comm ret; Initialize Watchdog timer; Set option reg; send a 1; decrement bit count; if zero, looking for a 1; Looking for 0, reset bit count if 1; done

Input_hold.data_in, Set_edge_wait; looking for 1, reset if 0 Wstate, # Rcv_addr; First word is address

Tpar, # 01fh; Init parity

Rcv next word

Comm_state, # Edge_wait

Comm_bit_count, # Num_start_bits; Preset State to wait for edge Input_hold.data_in, Parity_error; stop bit must be 1 Cmd_exec; Done, process received buffer; copy ...

EP 1 960 932 B1

<td>snb</td><td>Input_hold.data_in</td>

<td>SETC</td><td></td>

<td>rl</td><td>Comm_buffer</td>

<td>jmp</td><td>Rcv_word_handler</td>

... input bit ...

... to carry shift buffer

Check for complete word; Comm Transmit routines

<td colspan="2">Send_edge dec</td><td rowspan="2">Comm_bit_count :They comm_port.data._out Comm_ret comm_port.data_out Do_xmit_word</td>

<td>:They</td><td>j clrb jmp setb jmp</td>

<td colspan="2">Send bits</td><td></td>

<td></td><td>rl</td><td>Comm_buffer</td>

<td></td><td>jc</td><td>:they</td>

<td></td><td>clrb</td><td>comm_port.data_out</td>

<td></td><td>jmp</td><td>: check</td>

<td>:they</td><td></td><td></td>

<td></td><td>setb</td><td>comm_port.data_out</td>

<td>: check</td><td></td><td></td>

<td></td><td>jmp</td><td>Xmit_word_handler</td>

; decrement bit count; if zero, send a 1; send a 0; send a 1; put xmit bit into carry; send a '0'; send a '1'

Comm receiye word handler routines

Rcv_word_handler djnz Comm_bit_count, Comm_i and Comm_buffer, # 03fh clc mov \ V, »Comm_buffer cali parity_lookup xor W, Comm_buffer jnz Parity_error rr Comm_buffer and Comm_bu.ffer, # 01fh xor Tpar, CommLatter_sJate W strate; If word not complete, continue; only 6 bits; get 5 MSBs of received word; compare with received word; extract 5-bit value; calculate total parity; Execute word handler routine

Rcv addr

See_if_us

<td>clrb</td><td colspan="2">Flags.Global_cmd_flag; Clear global command flag</td>

<td>raov</td><td>W, Comm buffer</td><td>; Get received address</td>

<td>mov</td><td>PIC addr, W</td><td>; save it</td>

<td>xor</td><td>W # LFH</td><td>; is it global command</td>

<td>jnz</td><td>See_if_us</td><td>; No, check for address match</td>

<td>setb</td><td>Flags.Global_cmd_flag</td><td>; Set global command flag</td>

<td>jmp</td><td>Its_us</td><td>; process rest of command</td>

EP 1 960 932 B1

<img file="PL1960932T3_D0010.tif" />

Rcv__cmd rnov Command, Comm_buffer; save command jnb Command.4, Comm_get_fast; Fast read command, skip Reg ID

<td>mov jmp</td><td>Back. # Rcv reg ID Rcv_next_word</td><td>; point to next routine</td>

<td colspan="2">Comm get fast</td><td rowspan="2">; point to next routine</td>

<td>mov</td><td>Wstate, # Rcv_tpar</td>

<td>jmp</td><td>Rcv_next_word</td><td></td>

<td>Rcv reg ID mov</td><td>register_ID, Comm_buffer</td><td>; save register number</td>

<td>mov</td><td>In State, # Rcv_tpar</td><td>; point to next routine</td>

<td>JNB</td><td>Command.3, Rcv_next_word</td><td>; lf no value, done</td>

<td>mov</td><td>word_count, # 7</td><td>; Init word count</td>

<td>mov</td><td>Wstate, # Rcv_value</td><td>; point to next routine</td>

<td>J^mP</td><td>Rcv_next_word</td><td></td>

<td>Rcv value</td><td></td><td></td>

<td>rl</td><td>Commbuffer</td><td></td>

<td>rl</td><td>Commbuffer</td><td></td>

<td>rl</td><td>Commbuffer</td><td>; Shift rcvd bits to MSBs</td>

<td>mov</td><td>Comm__bit_count, # 5</td><td>; shift 5 bits</td>

<td>.shift loop</td><td></td><td></td>

<td>rl</td><td>Comm_buffer</td><td></td>

<td>rl</td><td>Comm_buf + 4</td><td></td>

<td>rl</td><td>Comm_buf + 3</td><td></td>

<td>rl</td><td>Comm_buf + 2</td><td></td>

<td>rl</td><td>Comm_buf + 1</td><td></td>

<td>rl</td><td>Comm_buf</td><td>; Shift a bit from Comm_buf to comm_buf</td>

<td>djnz</td><td>Comm_bit_count,: shift_loop</td><td></td>

<td>djnz</td><td>word_count, Rcv_next_word</td><td>; any mora words?</td>

<td>mov</td><td>Wstate, # Rcv_tpar</td><td>; point to next routine</td>

<td>jmp</td><td>Rcv_next_word</td><td></td>

<td>Rcv_tpar</td><td></td><td></td>

<td>mov</td><td>W Tpar</td><td>; Get result of parity calculations</td>

<td>jnz</td><td>Parity_error</td><td>; lf not 0, parity error</td>

<td>jmp</td><td>Set_rcv_stop</td><td>; set up to receive stop bit</td>

EP 1 960 932 B1; Comm transmit word handler routines

Xmit_word_handler djnz Comm_bit_count, Comm_ret; If word not complete, continue

Do_xmit_word

<td>mov</td><td>PCLATH, # $ &lt;</td><td></td>

<td>mov</td><td>W Wstate</td><td></td>

<td>jmp</td><td>IN</td><td>; Execute word handler routine</td>

Send_addr

<td>mov mov jmp</td><td>Wstate, # Send cmd&gt; W, PIC_addr Send_next_word</td><td>; point to next word routine; get address</td>

<td>Send_cmd</td><td></td><td></td>

<td>mov</td><td>Wstate, #Send_value&gt;</td><td>; point to send value</td>

<td>JNB</td><td>Command .4, V alue_is__next</td><td>; Is it fast read command?</td>

<td>mov</td><td>Back. # Send reg ID&gt;</td><td>; point to next word routine</td>

<td>Value_is_next</td><td></td><td></td>

<td>mov</td><td>W Command</td><td>; get command</td>

<td>jmp</td><td>Send_next_word</td><td></td>

<td>Send reg ID</td><td></td><td></td>

<td>mov</td><td>In State, # Send__value&gt;</td><td>; point to next word routine</td>

<td>. mov</td><td>W Register_lD</td><td>; get Register ID</td>

<td>jmp</td><td>Send_next_word</td><td></td>

<td>Send_value</td><td></td><td></td>

<td>mov</td><td>Wstate, # Next_value&gt;</td><td>; point to next word routine</td>

<td>mov</td><td>Word_count, # 7</td><td>; value is 7 words long</td>

Next_value mov Comm_bit_count, # 5: loop rl comm_buf + 4 rl comm_buf + 3 rl Comm_buf + 2 rl Comm_buf + 1 rl Comm_buf rl CommbufFcr djnz Comm_bit_count,: loop mov W, Comm_buffer djnz word_count, Send_par&gt;

mov W, Comm_buffer jmp Send_next_word

Send_Tpar mov Wstate, # Send_stop mov W.Tpar; Get 5-bit word; if not last word, all set; send parity next; point to next word routine; get transverse parity

EP 1 960 932 B1 jmp Sendnext_word Send_stop jmp Set_edge_wait; Go back to receive fashion; Process received buffer »

org lOOh

Gmd_exec

Process_cmd cjbe Command, # 7h, Fast_register_read; is it fast read?

cje Command, # 1 Oh, readregister; is it read register command?

cje Command, # 18h, write_register; is it write register?

cje Command, # 19h, reset_status__bits; is it reset status?

jmp Cmd_process_done

Fast_register_read

<td>mov</td><td>register_ID, command</td><td>; Register number is same as command codę</td>

<td>Read_register</td><td></td><td></td>

<td>mov</td><td>W # 27</td><td></td>

<td>mov</td><td>W-W register_TD</td><td>; Get index of register to read</td>

<td>JNC</td><td>Cmd_process_done</td><td>; if negative, not a valid register</td>

<td>mov</td><td>Temp, The</td><td>; save index</td>

<td>mov</td><td>PCLATH, # $ &lt;</td><td>; set up High-order PC bits</td>

<td>mov</td><td>In, Temp</td><td>; get index</td>

<td>jmp</td><td>In the PC +</td><td></td>

<td>jmp</td><td>cpy_output_reg</td><td></td>

<td>jmp</td><td>cpy reg 28</td><td></td>

<td>jmp</td><td>cpyreg 29</td><td></td>

<td>jmp</td><td>cpy reg 30</td><td></td>

<td>^cpy_reg_31</td><td></td><td>; Reg 31 = Status register</td>

<td>mov</td><td>Comm_buf, Status_reg</td><td></td>

<td>mov</td><td colspan="2">Comm_buf + 1, Status_reg + l</td>

<td>mov</td><td colspan="2">Comm_buf + 2, 2 + Status_reg</td>

<td>mov</td><td colspan="2">Comm_buf + 3, Status_reg + 3</td>

<td>jmp</td><td>Setup_reply</td><td></td>

<td>Cpy_reg_30</td><td></td><td>; Reg 30 = Serial number</td>

<td>inches</td><td>semo</td><td></td>

<td>mov</td><td>comm_buf + 3, W</td><td></td>

<td>inches</td><td>semo + 1</td><td></td>

<td>mov</td><td>comm_buf + 2, W</td><td></td>

<td>inches</td><td>semo + 2</td><td></td>

<td>mov</td><td>comm_buf + 1, W</td><td></td>

<td>inches</td><td>semo + 3</td><td></td>

<td>mov</td><td>comm_buf, The</td><td></td>

<td>jmp</td><td>Setup_reply</td><td></td>

<td>Cpy reg 29</td><td></td><td>; Reg 29 = Software type and version</td>

<td>mov</td><td colspan="2">Comm_buf, # Software_type</td>

<td>mov</td><td colspan="2">Comm buf + l, # Software version</td>

<td>mov</td><td>Comm_buf + 2, # 0</td><td></td>

<td>mov</td><td>Comm_buf + 3, # 0</td><td>; Send Software lype and version</td>

EP 1 960 932 B1 jmp Setup_reply

Cpy_reg_28; Reg 28 = Parameter reg mov Comm_buf, Parameter_reg mov Comm_buf + 1, Parameter_reg + 1 mov Comm_buf + 2, Parameter_reg + 2 mov Comm_buf + 3, Param eter_reg + 3 jmp Setup_reply

Cpy_output_reg; Reg 27 = Output State mov Comm_buf, Output_bit_reg mov Comm_buf + l, Output_bit_reg + l mov Comm_buf + 2, Output_bit_reg + 2 mov Comm_buf + 3, Output_bit_reg + 3 jmp Setup_reply

Writejregister mov bits: loop rl rl rl rl rl djnz cjne mov mov mov mov clrb jmp

Comm_bit_count, # 5; need to shift buffer by 5 comm_buf + 4 comm_buf + 3 comm_buf + 2 comm_buf + l commbuf

Comm_bit_count,: loop

Register_ID, # 28, See_write_output_reg

Parameter_reg, Comm_buf

Parameter_reg + 1, Comm_buf + 1

Parameter_regł-2 + 2 Comm__buf

Param eter_reg + 3, Comm_buf + 3

Status_LSB.Need_param_reffesh_flag

Cpy_reg_28; Not reg 28, see if output reg; Copy received data to reg; Reset need parameter refresh flag; send contents back in reply

See_write_output_reg

<td>CJNE</td><td>Register_ED, # 27, Cmdjprocess_done</td><td>; if not output reg, ignore</td>

<td>mov</td><td>Output_bit_reg, Comm_buf</td><td></td>

<td>mov</td><td>Output_bit_reg + 1, Comm_buf + 1</td><td></td>

<td>mov</td><td>Output_bit_reg + 2, 2 + Comm_buf</td><td></td>

<td>mov</td><td>Output_bit_reg + 3, Comm_buf + 3</td><td>; Copy received data to reg</td>

<td>inches</td><td>Update_outputs</td><td></td>

<td>jmp</td><td>Cpy_output_reg</td><td>; send contents back in reply</td>

Reset_status_bits mov Comm_bit_count, # 5 bits: loop rl comm_buf + 4 rl comm_buf + 3 rl comm_buft-2 rl comm_buf + l rl commbuf djnz Comm_bit_count,: loop mov W, / Comm_buf + 1 and Status_reg + 1, W

Z mov W / Comm_buf; need to shift buffer by 5; get byte; Clear bits; get MSB

EP 1 960 932 B1 and Status_reg, W; Clear bits mov Register_ID, # 31; indicate status reg in reply jmp Cpy reg 31

Setup_reply jb Flags.Global__cmd_flag, Set edge wait; If it was giobal, don't reply mov W, Status_LSB mov Comm_buf + 4, W and W, # 01fh or W, Status_MSB sz setb Comm_buf + 4.7

MSB mov Tpar, # lfh mov Comm_state, # Send_edge mov Wstate, # Send_addr mov Comm_bit_count, # Num_start jmp Comm_ret; Get LSB status; preset stored flags; Tum off 3 MSBs; Combine 5 LSbs with StatusJMSB; If any other flag bits set, indicate in; Initialize parity word; Go to send_edge State; Point to next routine bits; Init number of bits

Cmd_process_done jmp Set_edge_wait; No reply needed, done; Exit routines for comm

Parity_error setb status_LSB.Parity_err_flag; Indicate parity error Set_edge_wait τηον Comm_state, # Edge_wait; Go to edge wait State mov Comm_bit_count, # Nuin_start_bits; Init number of bits jmp Comm_ret

Set_send_reply mov Comm_state, # Send_edge; Go to send edge State mov Comm_bit_count, # Num_start_bits jmp Comm_ret

Rcv_next_word

<td>mov</td><td>Comm_state, # Rcv_jbits</td>

<td>mov</td><td>Comm_bit_count, # 6</td>

<td>jmp</td><td>Comm_ret</td>

<td colspan="2">Send next word</td>

<td>and</td><td>W # 01fh</td>

<td>xor</td><td>Tpar, The</td>

<td>inches</td><td>parity_lookup</td>

<td>mov</td><td>Comm_buffer, The</td>

<td>rl</td><td>Commbuffer</td>

<td>rl</td><td>Comm_buffer</td>

<td>mov</td><td>Com m_state, # Send_bits</td>

<td>mov</td><td>Comm_bit_count, # 6</td>

<td>jmp</td><td>Comm_ret</td>

<td>Set_rcv_stop</td><td></td>

; set up to receive 6-bit word; only 5 bits; update parity calculation; Save word with parity (6 bits); move to MSbs; set up to send 6-bit word

EP 1 960 932 B1

Semo

<td>mov</td><td>Comm_state, # Rcv_stop</td>

<td>jmp</td><td>Comm_ret</td>

<td>ORG</td><td>200h</td>

<td>retw</td><td>05ah, 092h, 05fh, 000h</td>

<td>retw</td><td>Offham, Offham, Offham, Offham</td>

<td>for</td><td> 4</td>

<td>ret</td><td></td>

; point to next routine

Retums 6-bit value corresponding to passed 5-bit value with odd parity parity_lookup; Save index; Set up high; get index jmp pc + in: table

<td>mov</td><td>Temp, The</td>

<td>mov</td><td>PCLATH, #: table &lt;</td>

<td>mov</td><td>In, Temp</td>

<td>jmp</td><td>+ pc in</td>

<td>retw</td><td></td>

1,2,4,7,8,11,13,14,16,19,21,22,25,26,28,31,32,35,37,38,41,42,44,47,49,50,52,55,56,5

9,61,62

Sets output bits according to received data

Comm_buf = Pulse duration in milliseconds

0: Continuous output (infinite duration)

1-255: Set output State for specified duration

After duration is over, tum all outputs off

Comm_buf + 1 [3] = Bit map of output States - MSB first bits 23-18: Unused bits 17-0: Outputs 18-1

Update_outputs

<td>mov</td><td>W, Comm buf + 3</td><td>•; get lsbs</td>

<td>and</td><td>W, # 03h</td><td>; only need 2 bits</td>

<td>mov</td><td>Temp, The</td><td></td>

<td>add</td><td>Temp, The</td><td>; Shift into bits 1 and 2 (XI and X2)</td>

<td>mov</td><td>The PORTA</td><td>; Get present status of port A pins</td>

<td>and</td><td>W # 0f9h</td><td>; elear output control bits</td>

<td>or</td><td>In, Temp</td><td>; Set desired output State</td>

<td>mov</td><td>PORTA, W</td><td>; output new value</td>

<td>rr</td><td>comm_buf + l</td><td></td>

<td>rr</td><td>comm_buf + 2</td><td></td>

<td>rr</td><td>comm_buf + 3</td><td></td>

<td>rr</td><td>comm_bufH</td><td></td>

<td>rr</td><td>comm_buf + 2</td><td></td>

<td>rr</td><td>comm_buf + 3</td><td>; shift buffer left 2 bits</td>

<td>mov</td><td>PORTB, comm_buf + 2</td><td></td>

<td>mov</td><td>PORTC, comm buf + 3</td><td></td>

<td>mov</td><td>• PORTA, # init_TRISA</td><td></td>

EP 1 960 932 B1 mov mov mov jz ms_loop mov mov: loop djnz djnz djnz and clr Ćlr done_output_ ret .'PORTB, # init_TRISB • PORTC, # init_TRISC MillisecSjCom m_buf done_output_set; first byte is pulse duration

Timeout_ctr, # ms_preset &lt;Timeout_ctr + 1, # ms_preset&gt;

Timeout_ctr + 1loop

Timeout_ctr,: loop

Millisecs, ms_loop

PORTA, # 0f9h

PORTB

PORTC; delay for pulse duration; tum off XI and X2; tum off other outputs set

Main Program start

Main_loop mov mov mov mov clr

c.lrb

C1kwait_loop djnz clr djnz djnz • jb flag cleared setb jmp

Clkcont jb jb mov setb jmp jnb djnz djnz setb t

mov mov jmp _ret jmp • PORTA, # Init_TRlSA • PORTB, # Init_TRISB! PORTC, # Init_TRISC C lk_timeout_ctr, # 12 Clk_timeout_ctr + 1 Flags.Clk_wait_flag

Initialize port A direction Initialize port B direction Init port C direction preset ...

... clock timeout counter Indicate waiting for clock Iow: low: high: cont

Comm scratch, Clk_cont WDT

Clk_timeout_ctr + · 1, Clk_cont

Clk_timeout_ctr, Clk_cont

Status_MSB.POR_flag, got_POR; Ignore clock timeout unti! POR

Status_MSB.Clk_timeout_flag; Indicate timeout on comm clock do_initialize

Comm_port.clock_in,: high; clock high

Flags.Clk_wait_flag, Clkwait_loop

Input_hold₅Comm_port; Save Data port value

Flags.Clk_wait_flag; Indicate waiting for clock high

Clkwait_loop

Flags.Clk_wait_flag, Clkwait_Ioop

NPR_timer + l,: cont; Dec LSB of need parm timer

NPR_timer,: cont; Dec MSB

Status_LSB.Need_param_refresh_flag; set flag every 64k clocks; Watchdog reset

PCLATH, # 0

W Comm_state

IN..

Main_loop; Set up high-order bits for routines in page 0; get vector; Execute comm state machine

EP 1 960 932 B1

PIC.DEF ί * include file for serial communication with PIC chips * / #pragma switch (ALL, FREQ) switch (PIC_serial_status) {

case sending bits: case sending st5 bits:

#ifdefVATEST out_bit_value = (PICxmitBuf.bits.bufLong [0] and 0x80000000)! = 0; / * out bit value =

MSB * /

PICxmitBuf.bits.bufLong [0] = P! CxmitBuf.bits.bufLong [0] «1; if (PICxmitBuf.bits.bufLong [l] and 0x80000000)

PICxmitBuf.bits.bufLong [i] ++;

PICxmitBuf.bits.bufLong [l] = PICxmitBuf.bits.bufLong [l) «1; if (PICxmitBuf.bits.bufLong [2] and 0x80000000)

PICxmitBuf.bits.bufLong [l] H ·;

PICxmitBuf.bits.bufLong [2] = PICxmitBuf.bits.bufLong [2] «1; / * Shift 96-bit buffer * / #else out_bit_value = 0;

shift_LSB_ptr = andPICxmitBuf.bits.bufByte [l 2]; of 96-bit register * / asm ("MOVE.L _shift_LSB_ptr, A0", "ROXL.W - (A0)", "ROXL.W - (A0)", "ROXL.W - (A0)", "ROXL .W - (AO) "," ROXL.W - (AO) "," ROXL.W - (AO) ", / * point past least significant word / * Get pointer to buffer, elear carry ♦ / / * rotate left and decrement pointer * / / * rotate left and decrement pointer * / / * rotate left and decrement pointer * / / * rotate left and decrement pointer * / / * rotate left and decrement pointer ♦ / / * 96 bits have been shifted, MSB is in carry * /);

ROXL.W out bit value "

/ * Put MSB in out bit value * / "endif break;

case do_send_cmd: bit_count = NUM_STARTJ3ITS-1; PIC_serial_status = sending start; out_bit_value = 0;

break;

case do_PIC_start:

bit_count = 3 * B1TS_PER_SEC; out_bit_value - l;

PIC_serial_status = sending PIC start; break;

case sending start: out_bit_value = 0; break;

EP 1 960 932 B1 case sending stop: case sending start 1:

out_bit_value = 1; break;

default:

out_bit_value = 1;

} if (out_bit_value) fsl004.io.pulse0ut20ff = 1;

else fsl004.io.pulse0ut20ff = 0; / * Send bit out * / in__bit_value = fsl004.io.pulselnl State; / * Getrcvd bit value * / fsl004.io.puise0utl0ff = 1; / * Send clock rising edge * / switch (PIC_serial_status) {

case waiting for start: if (in_bit_value = 0) zero_count-H-; else ..

{if (zero_count = (NUM_START_BITS-1)&gt;

{.PIC_serial_status = rcving bits; bit_count = PICrcvBuf.bitCount + 1;

else zero_count = 0;

} break;

case rcying bits:

#ifdefV ATTEST

PICrcvBuf.bits.bufLong [0] = PICrcvBuf.bits.bufLong [0] «1; if (PICrcvBuf.bits.bufLong [l) and 0x80000000)

PICrcvBuf.bits.bufLong [0] -H-; .

PlCrcvBuf.bils.bufLong [l] = PICrcvBuf.bits.bu £ Long [l] «1; if (PlCrcvBuf.bits.bufLong [2] and 0x80000000)

PiCrcvBuf.bits.bufLong [1] ++;

PICrcvBuf.bits.bufŁong [2] = (PICrcvBuf.bits.bufŁong [2] «1) + in_bit_value;

ielse shift_LSB_ptr = andPlCrcvBuf.bits.bufByte [12]; of 96-bit.register * / asm ("MOVE.L _shift_LSB_ptr, A0", "ROXLAV - (AO)", "ROXL.W - (AO)", "ROXL.W - (A0)", "ROXL. W - (AO) "," ROXL.W - (A0) "," ROXL.W - (AO) "

*/ .·.

Z * point past least significant word / * Get pointer to buffer, elear carry * / / * rotate left and decrement pointer * / / * rotate left and decrement pointer * Z / * rotate left and decrement pointer * Z / * rotate left and decrement pointer ♦ / / * rotate left and decrement pointer * / / * 96 bits have been shifted, LSb is unknown

EP 1 960 932 B1);

PICrcvBuf.bits.bufByte [ll] = (PICrcvBuf.bits.bufByte [l 1] and Oxfe) | in_bit_value; / * add in received bit * / #endif break;

default: -.

{ }

} · If (~ bit_count &lt;= 0) · · {

switch (PIC_serial_status) {

case rcving_bits:

PIC_serial_status = rcving stop; bit_count = 1;

break;

case sending bits:

PlC_serial_status = sending stop; bit_count = 1; .

break; · Case sending stop:

if (PICxmitBuf.PIC_addr = GLOBAL_PIC_ADDR)

PIC_serial_status = idle;

else {'

PIC_serial_status = waiting for start; bit_count = PIC_wait_limit; zero_count = 0;

} break;

case sending PIC start:

PIC_seriaI_status = idle; break;

case sending start:

PIC_serial_status = sending start 1; bit_count - 1;

break;

case sending start 1:

PIC_serial_status = sending bits; bit_count = PICxmitBuf.bitCount; break;

case waiting for start:

PICrcyBuf.flags | = rcv_timeout_flag | rcv_data_ready_flag;

PIC_serial_status = idle; break;

case rcving stop: if, (in_bit_value = 0)

PICrcvBuf.flags | = rcv_bad_length_flag;

PlC_serial_status = idle;

PICrcyBuf.flags | = rcv_data_ready_flag; bit_count = 1;

EP 1 960 932 B1

PULSE.C ftinclude "mtrlink.def” / * #include "flash.def '♦ / #define PSTRUJDEFINED // include" pulselink.def' #include "pulse.h"

tfinclude "ufloat.h"

tfinclude "log.h"

tfinclude "alarm.h"

#include "copymem.h"

tfinclude "plcctrl.h"

#include &lt;stdio.h&gt;

# ifdeffakeMC5.

#undef NUMPH. tfdefinc NUMPH 24 tfendif / * definc WDT flags for the PIC communication routine * / #pragma region ("ram = WDTFIags") short int WDTpulseSec;

#pragma region ("ram = ram") #pragma region ("data = secondBack") void (* pulseSecondp) (void) = pulseSecond; ftpragma region ("data = data") #ifndef IS_MC5 #pragma region ("data = everySubsecond") // ifdef 1S_RSM void (* pulseSubsecp) (void) = pulseSubsecond; # ełse void (* pulseSubsecp) (void) = pulseService; #endif #pragma region ("data = date") #endif.

break; #pragma region ("data = powerUp") default: void (* pulseStartupp) (void) = pulseStartup;

PlC_serial_status = idle; tfpragnta region ("data = date")&gt;

} ί / pragma region ("data = dayBack") void (* pulseDayp) (void) = pulseDay;

#pragma switch (ALL, NOFREQ) #pragma region ("data = data")

EP 1 960 932 B1 / * elear out PIC * / void pulseColdstartO.

t λ

int i;

for (i = 0; i &lt;num_PICs; iH-) if (PIC_status [i] .software_type = 3) {

PIC_status [i] .clear_puIse_regs = TRUE; PIC_status [i] .get_status = TRUE;

}. elear State = SEND_GLOBAL_CLR;

} "·· void pulseStartup (void)

and int i;

// ifndef IS_RSM int work_PIC_addr;

#endif # ifdefIS_MC5 'int work_num_pulses;

#endif #ifdefV ATEST / * test !!! '! * / tempcommand = SYSTEM_CONTROL; temp reg ID = 0; .

temp_command_data = READ_ENCODER_ED; tempflags = rcv_data_ready_flag;

#endif for (i = 0; (! dont_clear_PIC_stats) andand (i &lt;(2 * NUMPH)); i ++) {

pu! seData [i] .error_cnt = 0; pulseData [i] .ID_field [0] = 0; pulscData [i] .reading · = 0;

} for (i = 0; i &lt;MAX_PICS; i ++)

- PIC_status [i]. PIC__addr = 0;

hold__num_pulse_ctrs = releaseCodep-&gt; option.numPu! seCounters; if (hold__num_pulse_ctrs&gt; NUMPH) num_pulse_ctrs = NUMPH;

• else num_pulse_ctrs = hold_num_pulse_ctrs; num_PlCs = 1;

# ifdefIS_MC5. PlC_status [O'J.PIC_addr = MC5_MUX_PIC_ADDR; / * If MC5, add PDM PIC (s) to PIC table * /

EP 1 960 932 B1 if (int_configltmessg.configLTM [PULSE 1] .accum) {

work_num_pulses = num_pulse_ctrs; work_PIC_addr = 0; .

while (work_num_pulses&gt; 0) {

PIC_status [num_PICs ++]. PIC_addr = work_PIC_addr ++; / * Pulse counters for Q13 * /.

work_num_pulses - = 4;

} · ·. if (int_configItmessg.configLTM [PULSE2] .accum) {· · ·. · · Work_num_pulses = num_pulse_ctrs; work_PIC_addr = 6;

while (work_num_pulses&gt; 0) (

».

PlC_status [num_PICs ++]. PIC_addr = work_PIC_addiH- +; / * Pułse counters for Q14 "/ work_num_pulses - = 4;

} }

num_LCMs = releaseCodep-&gt; option.LCM_flags and 0x03; work_PIC_addr = LCM_BASE_ADDR; for (i = 0; i &lt;num_LCMs; iH-) {

PIC_status [num_PICs ++]. PIC_addr = work_PIC_addr ++; / * LCM's * /}

#else #ifdefIS_STS

PIC_status [0] .PIC_addr = ST5_MUX_PIC_ADDR; / * If ST5, add mux to PIC table * / ATM_work releaseCodep-&gt; option.couplers_mask; work_PIC_addr = ATM_BASE_ADDR; for (i = 0; i &lt;4; i ++) {

if ((ATM_work and 0x08)! = 0) {/ * Bit is set in mask, add ATM PIC to table * /

PJC_status [num_PICs-ł-ł -]. PIC_addr = work_PIC_addr;

} work_PlC_addr ++;

ATM_work = ĄTMwork «1;

} #else if (num_pulse_ctrs = 0) numPICs = 0;

#endif #endif, for (i = 0; i &lt;MAX_PICS; i ++) {/ * Build PIC table * / • PIC_status [i] .get_semo = TRUE;

PIC_status [i] .get_version = TRUE;

PIC_status [i] .get_status = FALSE; .

PIC, _status [i] .reset_status = FALSE;

PIC_status [:]. Update_parameter = FALSE;

EP 1 960 932 B1 if (łdont_clear_PIC_statsj {'

PIC_status [i] .PIC_reset_count = 0;

PIC_status [i] .comm_error_count = 0;

PlC_status [i] .PIC_data_err_count = Ó; ·

PIC_status [i] .software_type - 0;

PJC_status [i] .software_version = 0;

PIC_status [i] .serial_number = 0;

}

PIC_status [i] .curr_puIse_reg = O;

# ifdefIS_MC5.

if (PlC_status [i] .PIC_addr&gt; = ST5_MUX_PIC_ADDR) PIC_status [i] .repIy_wait_Iimit = DIRECTPICWAITLIMIT;

eise

PIC_status [i] .reply_wait_limit = BUFFERED_PIC_WAIT_LIMIT;

else //

PlC_status [i] .reply_wait_limit = DIRECTPICWAITLIMIT;

#endif if (PIC_slatus [i] .PIC_addr &lt;= MAX_PULSE_PIC_ADDR) PlC_status [i] .num_pulse_regs = PULSES_PER_PIC;

elsePIC_status [i] .num_pulse_regs = 0;

} current_PIC_index = 0; rcv_PJC_index = 0; if (dont_clear_PIC_stats). dont_clear_PIC_stats = FALSE; / * Clear flag ♦ / else {

PIC_bad_addr_count = 0;

PICrcvBuf.flags = 0;

PlC ^ serialstatus - do_PIC_start; ·. PIC_clk_state = clk_low; 'Z * Initialize serial comtn variables · /}

clear_state = NOGLOB ALSEND;

pulseOutMode = releaseCode.option.picMode; / * for compatibility with old codę * / if (startup.coldStart) {

pulseColdstartO;

}

EP 1 960 932 B1 const unsigned char parity6 [32] = {1,2,4,7,8,11,13,14,16,19,21,22,25,26,28,31,32,35, 37.38.41.42.44.47.49.50.52.55.56.59.61.62};

void pulseDayO.

{dont_clear_PIC_stats = TRUE; / * Tell pulseStartup not to elear error counts * / rebuild_timer = REBUILD_DELAY; / * Set up for delayed table rebuild * /}

void pulseSecondO {

#ifndef 1S_ST5 pulseService ();

#endif if (Comm_background_flags.do_rebuild) {

pulseStartupO;

Comm_background_flags.do_rebuild = FALSE;

}. if (Comtn_background_flags.do_alarm) putAlarm (andPIC_alarm, 4);

Commbackgroundflags.doalarm = FALSE;

/ * set_PLC_relays function * / / * Called from PLC routines to request update of * / / * PLC port multiplexer PIC chip on ST5 power board * / £ ifdefIS_ST5 void setjPLC_relays (int xmitRelay, int rcvRelay) f

k

- while (MUX_control.active_flag MUX_control.request_flag) {

ccwait ();

}

MUX_control.xmit_mask = xmitRelay;

MUX_control.rcv_mask = rcvRelay;

MUX_control.done_flag = FALSE;

MUX_control.request_flag = TRUE;

if ((MUX_control.xmit_mask! = MUX_control.last_xmit_mask) || (MUX_control.rcv_mask! = MUX_control.last_rcv_mask)) {'while (! MUX_control.done_flag andand! (MUX_control.active_flag andcying) = = {

ccwaitO;

} )

EP 1 960 932 B1 #endif void pulseService (void)

n

V

BOOLEAN need__pulse_read, copy_rcvd_data, rcv_buf_err;

# ifdefIS_MC5

BOOLEAN got_ver_3, got_ver__3_3;

int j;

unsigned char * work_char_ptr; unsigned long work_bit_mask;

#endif, int \ vork_pulse_index; phaccum accumXfer;

• int i;

if (numJPICs = 0)

PIC_serial_status = idle;

if (PIC_seriaI_status = idle) {

if (iWDTpulseSec) \ VDTpulseSec = l; / * Tell WDT controller that we are OK * /}

if (hold_num_pulse_ctrs! = releaseCodep-&gt; option.numPulseCounters) {/ * hdwr -n has changed * / dont_clear_PIC_stats = FALSE;

rebuild_timer = 1; / * Force immediate table rebuild * /}

. if ((PIC_serial_status = idle) andand (rebuildjtimer! = 0) andand (—rebui'd_timer = 0)) {

Comm_background_flags.do_rebuild = TRUE;

} else if ((PIC_seriaJstatus = idle) andand (num_PICs! = 0) andand (pulseOutMode! = PIC_MC_SERIAL) andand (! Comm_backgroiind_fłags.do_rebuild)) / * Serial processing enabled? * / {

if (PICrcvBuf.flags and rcv_data_ready_flag) {· / ♦ Process received message * /

PlCrcvBuf.fIags and = ~ rcv_data_ready_flag;

EP 1 960 932 B1 rcv_buf_err =! Decode_rcv_buffer ();

if ((PIC ^ comm_mon.control_flags and RCV_DATA_RDY) = 0) {

PIC_comm_mon.rcv_buf = PICrcvBuf;

PIC_comm_mon.control_flags [= RCV_DATA_RDY;

} if ((ext_comm.control_flags and CPY_RCV_DATA)! = 0) r

t ext_comm.rcv_buf = PICrcvBuf; · Ext_comm.control_flags and = ~ CP.Y_RCV_DATA; ext_comm.control_flags | = RCV_DATA_RDY;

} # ifdefIS_ST5 if (ATM_control.active_flag) {

ATM_control.result_flags = PICrcyBuf.flags; if (rcv__buf_err) if (ATMcontrol.State! = WAJT_ALIGN) {

ATM_controI.error_flag = TRUE;

ATM_control.active_flag - FALSE;

• ATM_control.done_flag = TRUE;

}} else {·. · Switch (ATM control.State) {"case DO_PRESET:

ATM_control.xmit_ievel - PlCrcvBuf.command_data »24; ATM_control.coupler_level = (PICrcvBuf.command_data »16) and OxOff; ATM_control.active_flag = FALSE;

} break;

case SET_AL1GN:

ATM_controLstate = WAIT ALIGN;

} · “Break:

case \ VAIT_ALIGN:

{

ATM_control.optimum_cap_code = PICrcvBuf.command_data and ATMRCCAPMASK;

ATM_control.optimum_reading = PICrcvBuf.command_data »16; ATM_control.result_flags | = (PICrcvBuf.command_data and 0xe000);

/ * Copy flags from reply * /, if ((ATM_control.result_flags and 0xc000)! = 0) {/ * Analog levels out of rank * /

ATM_control.error_flag = TRUE;

EP 1 960 932 B1 if (ATM_control.optimum_reading &lt;ATM MIN_READING) {"

ATM_control.result_flags | = 0x1000; / * Indicate reading too Iow * / ATM_control.error_flag = TRUE;

}

ATM_control.active_flag = FALSE; break;

case DO_PLC_SET:

case DO_ATM_DISCONNECT:

{

ATM_controI.active_flag = FALSE;

} break;

default:

{

ATM_control.active_flag = FALSE;

ATM_control.error_flag = TRUE;

} break;

}} if (! ATM_control.active_flag)

ATMcontrol.doneflag = TRUE;

if (MUX_control.active_flag) {

MUX_controI.resuIt_fIags = PICrcvBuf.flags; if (rcv_buf_err) {

MUX_control.error_flag = TRUE;

MUX_control.last_xmit_mask = 0;

MUX_control.last_rcv_mask = 0;

} clse {

MUX_controI.last_xmit_mask = PICrcvBuf.command_data and Oxff; MUX_control.last_rcv_mask = (PICrcvBuf.command_data »8) and Oxff; }

MUX_control.active__flag = FALSE;

MUX control.done_flag = TRUE;

} "

#endif if (rcv_buf err) {'· tfifdef IS_ST5 if (! ATM_control.active_flag || (ATM_control.state! = WAIT_ALIGN)) #endif {

last_comm_err_flag = PICrcyBuf.flags;

copymem (sizeof (PICbitBuf), (char *) (andHoldrcvBuf), (char *) (andPICrcvBuf));

if ((PICrcyBuf.flags and rcv_bad_addr_flag)! = 0)

EP 1 960 932 B1 {/ * past end of valid PICs, address error * /

PIC_bad_addr_count-H;

set_PIC_alarm (PIC_adderr_O, PICrcvBuf.PłC_addr, (PICxmitBuf.PIC_addr «8) + PICxmitBuf.command);

} else {/ * PIC address was valid, but comm failed * /

PIC_status [rcv_PIC_index] .comm_error_count-H; if (PIC_status [rcv_PIC_index] .comm_error_count&gt; 2) {

. set_PIC_alarm (PIC_comerr_0, PIC_status [rcv_PIC_index] .PIC_addr,. PICrcvBuf.flags);

} '/ * Lost contact with PIC, read serial number and software version * /. PIC_status [rcv_PIC_index] .get_semo = TRUE;

PIC_status [rcv_PlC_index] .get_version = TRUE;

} }

else {/ * Valid message received * / if ((PICrcvBuf.command = READ_REGISTER) andand (PICrcvBuf.reg_ID =

STATUS_REG)) {

process_status_bits ();

•} else if (PICrcvBuf.command = SYSTEM_CONTROL) {. if (PICrcvBuf.reg_ID = STATUS_REG) {/ * Response frome reset status bits cmd * /

PIC_status [rcv_PIC_index] .reset_status = FALSE; process_status_b its ();

} / 'ifdef 1S_MC5 else if ((PIC_status | rcv_PIC_index] .software_type = 4) andand ((Pię_status [rcv_PIC_jndex) .last_cmd data and OxfffR) OOO) =

READ_ENCODER_1D)) ~ "{/ * response from encoder read ID comd * / work_pulse_index = (PlCrcvBuf.PIC_addr * PULSES_PER_PIC) +? LCrcvBuf.reg_JD;

i = (PlC_status [rcv_PIC_index] .last_cmd_data and OxOOOOffOO) »8; work_char_ptr = (unsigned char *) andPICrcvBuf.command_data; for (j = 0; j &lt;4; j ++) ·. · {

if ((* work_char_ptr = 0) || (i&gt; = ID_FIELD_LENGTH)&gt;

{ .

j = 10; / * indicate end of message found * /} · · else {pulseData [work_pulse_index] .ID_buffer [i] = * work_char__ptr; iH-;

work_char_ptr ++;

}

EP 1 960 932 B1 if (j&gt; 5) {/ * found end of ED field from remote encoder * / for (i = 0; i &lt;ID_FIELD_LENGTH; iH-) {

pulseData [work_pulse_index] .ID_field [i] - pulseData [work_j) Ulse_index] .ID_buffer [i]; . .

puIseData [work_puIse_index] .ID_buffer [i] = 0;

} · »And

} else if ((PICrcyBuf.command = READ_REGISTER) andand (PICrcvBuf.reg_ID - ERROR_REG)) {

if (PIC_status [rcv_PIC_index] .software_type = 4) {/ * Remote encoder interface module * / work_pulse_index = (PICrcvBuf.PIC_addr * PULSES_PER_PIC) + (PICrcvBuf.command_data »24);

if (work_pulse_index &lt;(2 * NUMPH)) {

pulseData [work__pulse_index] .error_cnt-H; for (i = 0; i &lt;ID_FIELD_LENGTH;

oulseData [work_pulse_index] .ID_buffer [iH-] = 0); .

' } }

#endif&gt;}.

else if ((PICrcyBuf.command. WRITE_REG1STER) andand (PICrcyBuf.reg ID - = PARMREG)) •

PIC_status [rcv_PIC_index] .update_parameter = FALSE;

} else if ((PlCrcvBuf.command = READREGISTER) andand (PICrcvBuf.reg_ID = VERS_REG)) {

PIC_status [rcv_PIC_index] .get_version = FALSE; PIC_status [rcv_PiC_mdex) .software_type = (PlCrcvBuf.command_data and OxffDOOOOO) »24;

: PIC_status [rcv_PIC_index] .software_version = (PlCrcvBuf.command_data and ΟχΟΟΕΕΟΟΟΟ) »16; PIC_status [rcv_PIC_index] .loop_rate = (PICrcvBuf.command_data and ΟχΟΟΟΟΕΕΟΟ) »8;

&gt;

else if ((PICrcyBuf.command - READ_REGISTER) andand (PlCrcvBuf.reg_ID == SERNO_REG)) '{

PICjstatus [rcv_PIC_index] .get_semo = FALSE;

PIC_status [rcv_PIC_index) .serial_number = PICrcvBuf.coinmand_data;

} ... · . - . · -.

else if (((PłCrcvBuf.command = READ REGISTER) | 1 (PICrcyBuf.command &lt;= MAX_FAST_READ)) 'andand (PICrcyBuf.reg ^ ID &lt;= MAX_PULSE_REG)) {/ * Pulse reading * / work_pulse_index «· (PlCrcvdr *. PULSES_PER_P1C) + · PICrcvBuf: reg ID: '

EP 1 960 932 B1 if (work_pulse__index &lt;(NUMPH * 2)) {· pulseData [work_pulse_index] .reading = PlCrcvBuf.command_data; copy_rcvd_data = FALSE; . '' ·· · if (PIC_status [rcv_PIC_index] .get_version) {

} 'else if (PIC_status [rcv_PIC_index] .software_type = 4) {/ * Remote encoder interface module * / • copy_rcvd_data - TRUE; · ·. '· • accumXfer.low = pulseData [work_pulse_index] .reading;

} · Else if (PIC_status [rcv_PIC_index] .software_type - 3) {/ * Remote pulse counter module * /.

copy_rcvd_data = TRUE;

if (! PIC_status [rcv_PlC_index] .get_semo) {

sprintf ((char *) pulseData [work_pulse_index] .ID_field, "S% 081dP% d ''₅PIC_status [rcv_PlC_index] .serial_number.

PICrcvBuf.reg_ID);

if (releaseCode.option.countEveryEdge) {. accumXfer.low = pulseData [work_pulse_index] .reading;

} else {·. accumXfer.low = pulseData [work_pulse_indcx) .reading »1;

}} ·. accumXfer.high = OL;

#ifndefV ATTEST.

if (copy_rcvd_data) {

J / ifhdef 1S_MC5.

/ * It is an RSM or ST5, so mapping for pulse 1 thru 4 is M1Q13, MIQ14, M2Q13, M2Q14 * /. ph [0] [work_pulse_index / 2] [(work_pulse_indexand0x0l)? PULSE2: PULSEl] .accum = ph [1] [work_pulse_index / 2] [(work_pulse_indexandOxO 1)? PULSE2: PULSE 1] .acfer;

./else .. · / * It is an MC5, so mapping for pulse 1 thru 48 is M1Q13..M24Q13,

M1Q14..M24Q14 · / ph [0] [work_pulse_index% NUMPH] [(work_pulse_index / NUMPH)? PULSE2: PULSEl] .accu m =

EP 1 960 932 B1 ph (l] [work_puIse_index% NUMPH] [(work__pulse_index / NUMPH)? PULSE2: PULSEl] .accu m =.

accumXfer;

ftendif.

'} tfendif} ·)

. if ((PICrcvBuf.flags and (PIC_error_flag | PIC_invalid_data_flag))! = 0). PIC_status [rcv_PIC_index] .get_status = TRUE; . , -.

if ((PICrcvBuf.flags and PIC_need_refresh_flag)! = 0)

PIC_status [rcv_PIC__index] .update_parameter = TRUE;

/ * cbeck status tus flags * / f $

/ * Decide what command to send * /

PlCxmitBuf.flags = 0; tfifndef IS_ST5. · / * MC5 or RSM, cbeck for cold-start processing to elear pulse registers * / if (c! ear_state == SEND_GLOBAL_CLR). {/ * Cold start, send global clr * /

PICxmitBuf.PIC_addr = GLOBAL_PIC_ADDR;

PICxmitBuf.command = CLEAR_PULSE_REGISTERS; format_xmit__bufferQ;

clearstate = SENDINGGLOBALCLR;

PIC_serial_status = do_send_cmd; / * Start UART * /. } · 'Else if (clear_state = SENDING_GLOBAL_CLR).

{clear_state = GLOBAL_CLR_SENT;

} #else / * ST5, check for ATM (Automatic Tuning Module) operations * / if (ATM_control.request_flag) {

ATM_control.request_flag = FALSE;

ATM_control.error_flag = FALSE;

ATM_control.aciive_flag = TRUE;

ATM_control.State = ATM_DONE;

PlCxmitBuf.PlC_addr = ATM_control.ATM_number + ATM_BASE_ADDR;

switch (ATM_control.operation) {

case. SET_PRE_ALIGN :.

EP 1 960 932 B1

PlCxmitBuf.command = WRJTEREGISTER;

PICxmitBuf.reg_ID = OUTPUT_REG;

PICxmitBuf.command_data = ATM_control.start_cap_code and ATM_RC_CAP_MASK; '' ''

PICxmitBuf.command_data | = ATM_PRESET_CODE;

"ATM_control.state = DO_PRESET;

break;

case DO_AL1GN:

. PICxmitBuf.command = WRITE_REGISTER;

PICxmitBuf.regJD = CONTROL_REG; .

if (ATM_control.start_cap_code&gt; ATM_control.end_cap_code) '

ATM_control.end_cap_code = ATM_control.start_cap_code;

PICxmitBnf.command_data = ATM_control.start_cap_code and ATM_RC_CAP_MASK; .

PICxmitBuf.command_data = (PICxmitBuf.command_data «12) | (ATM_control.end_cap_code and ATM_RC_CAP_MASK) I (ATM_MEAS_TIME «24);

ATM_control.state = SET_ALIGN;

ATM_control.align_timer - ATM_control.end_cap_code ATM_control.start_cap_code;

ATM_control.align_tiiner * = ((ATM_DISC_T1ME + ATM_MEAS_TIME + 4) * (1.25 / 62.5));

ATM_controI.align_timer + = 13; / * Time in 1/64 sec to wait before checking result * / / * Number of steps * time per step + 25% + .2 second * / break;

case SET_NORMAL_PLC:

PICxmiiBuf.command = WRlTE_REGiSTER;

PlCxmitBuf.reg_ID = OUTPUTREG;

PICxmrtBuf.command_data = ATM_co.ntrol.optimum_cap_code and ATM_RĆ_CAP_MASK;

PICxmitBuf.command_data | = ATM_PLC_CODE;

ATM_control .State = DO_PLC_SET; break;

case DISCONNECT_COUPLER:

PICxmitBuf.coinmand = WRITE_REG1STER;

PlCxmitBuf.reg_TD = OUTPUTREG;

PICxmitBuf.command__data = ATM_control / optimum_cap_code and ATM_RC_CAP_MASK;

PICxmitBuf.command_data | = ATM_DISC_CODE; .

ATM_control .State = DO_ATM_DISCONNECT; break;

default:

case READ_XMIT_LEVEL:

. ATM_control.error_flag = TRUE; ATM_control.done_flag = TRUE; ATM_control.active_flag = FALSE; break;

}

EP 1 960 932 B1 if (ATM_control.active_f] ag) {. format_xmit ^ buffer ();

PIC_wait_limit = DIRECT_PIC_WAIT_LIMIT;

PIC_serial_status = do_send_cmd; / * Start UART * /&gt;

f}.

else if (ATM_control.active_flag). · '{

if ((ATM_control.state! = WAIT__ALIGN) || (--ATMcontrol.aligntimer &lt;= 0)) {

ATM_control.error_flag = TRUE;

ATM_control.done_flag = TRUE;

ATM_control.active_flag = FALSE;

} else {/ * poll ATM for auto-tune end * /

PlCxmitBuf.command = 0;

format_xmit_buffer ();

PIC_waitJimit = DIRECT_PIC_WA1T_LIM1T;

PIC_serial_status = do_send_cmd; / * Start UART * /}

} else if (MUX_control.request_flag) {

MUX_control.request_flag = FALSE;

MUX__control.error_flag - FALSE; if ((pulseOutMode = P1C_ST_SERIAL)) {

PICxmitBuf.bils.bu £ Byte [O] = ((MUX_controI.rcv_mask and 0x03) «5) | ((MUX_control.xmit_mask and 0x7f) »2);

PICxmitBuf.bits.bufByte [l] = ((MUX_control.xmit_mask and 0x03) «6); bit_count = 11;

PIC_serial_status = sending stS bits; / * Start UART ♦ / MUX_control.last_xmit_mask = MUX_control.xmit_mask; MUX_control.last_rcv_mask = MUX_control.rcv_mask; MUX_control.done_flag = TRUE;

.} 'else

MUX__control.active_flag = TRUE;

PICxmitBuf.PIC_addr = ST5_MUX_PIC_ADDR;

PICxmitBuf.command = WRITEREGISTER;

PlCxmitBuf.reg_ID = OUTPUTREG;

PICxmitBuf.command_data = (MUX_controI.rcv__mask «8) + MUX_control.xmit_mask;

format_xmit_buffer ();

PlC_waitJimit = DIRECT_PIC_WA1T_LIMIT;

PIC_seriaLstatus = do_condition_cmd; Λ Start UART * /.

EP 1 960 932 B1 #endif else if ((ext_comm.control_flags and (XMIT_DATA_RDY | XMIT_REQUEST)) =. (XM1T_DATA_RDY | XMIT_REQUEST)) {, / * Send command for extemal routine ♦ /

PICxmitBuf = ext_comm.xmit_buf;

ext_comm, control_flags and = ~ XMIT_REQUEST; ext_comm.control_flags | = CPY_RCV_DATA;

• / * Look up correct PIC_status index for reuested PIC * / for (i = 0; ((i &lt;MAX_PICS) andand (PIC_status [i] .PIC_addr! = PICxmitBuf.PlC_addr));

i ++);

if (i &lt;num_P! Cs) {

PIC_status [i] .last_cmd_data = PICxmitBuf.command_data;

PlC_status [i] .last_command = PICxmitBuf.command;

} # ifdeflS_MC5 if (ext_comm.xmit_buf.PIC_addr &lt;ST5_MUX_PIC_ADDR)

PIC_wait__limit = BUFFERED_PIC_WAIT_L1MIT; else / iendif

PIC waitlimit = DIRECT_PIC_WAIT_LLMIT; format_xńiit_buiTerO;

PlC_; serial_status = do_send_cmd; / * Start UART * /} · else if ((((ext_comm.control_flags and SUPPRESS_NORMAL_COMM) = 0) # ifdefIS_ST5 andand (~ ST5_PIC_delay_ctr &lt;= 0)) {

ST5_PlC_delay_ctr = ST5_PIC_DELAY; / * Slow down routine Communications in ihe ST5 * / #else •) {

// endif

PlCxmitBuf.PlC_addr = PIC_status [current_PIC_index] .PIC_addr; need_pulse_read = TRUE; / * Set defaults * / # ifdefIS_ST5 if ((pulseOutMode = PIC_ST_SERIAL) andand (PlCxmitBuf.PIC_addr = ST5_MUX_PIC_ADDR)) {·}

else

EP 1 960 932 B1 #endif if (PIC_status [current_PlC_index] .force_pulse_read andand (! PIC_status [current_PIC_index] .get_version) andand (PIC_status [current_PIC_index] .PIC_addr &lt;ST5 MUX_PIC_ADDR)) {~ PIC_pace_ex

} · Else. · · {

PIC_status [current_PIC_index] .force_pulse_read = TRUE;

#ifndef IS_ST5 if (PIC_status [current_PIC_index] .clear_pulse_regs andand (clear_state = GLOBAL_CLR_SENT)) {/ * Global elear sent, get status * / need_pulse_read = FALSE;

PICxmitBuf.command = READ_REGISTER;

PICxmitBuf.reg_ID = STATUS_REG; format_xmit_buffer ();

} else // endif if (PlC_status [current_PIC_index] .get_version) {. need_pulse_read = FALSE;

PICxmitBuf.command - READ_REGISTER;

PlCxmitBuf.reg_ID = VERS_REG; format_xmit_buffer ();

} else if (PIC_status [current_PlC_index] .get_semo) {

need_pulse_read = FALSE;

PICxmitBuf.command = READ_REG1STER;

PICxmitBuf.reg_ID. = SERNO_REG; format_xm it_bufferO;

} else if (PlC_status [current_PIC_index] .update_parameter) {

PICxmitBuf.command = WR1TEREGISTER; if (PIC_status [current_PIC_index] .software_type = 3) {/ * Pulse ctr * / / * Pulse ctr parameters: * / / * Power-On sample installment:, 42 / sec * / / * Power-off sample installment: 1 / sec ♦ / / * Days to count if rcving pulses: * / / *. RSM: 5 days * / / * PDM: 35 days * / / * Days to count if no pulses rcvd: * / / * RSM: 1 day * / / * PDM: 3 days. * /. / * on RSM, the 2 lsbs of * /

EP 1 960 932 B1 i * load_shedjmask [0] are sent to * / / * the PIC output bits * / #ifdefIS_RSM

PICxmitBuf.command_data = 0x01150507 and · (load_shed_state [0] | Oxfffffffc);

else //

PICxmitBuf.command_data = 0x0115230d;

// endif}.

// ifdef IS_MC5 else if (PIC_status [current_PIC_index] .software_type = 4) {/ * Remote encoder reader * /

PICxmitBuf.conimand_data = READJENCODERJPARM; if ((releaseCodep-&gt; option.couplers_mask and 0x01) = 0) • {/ * If mask bit 0 is 0, no touch-pad compatibility * /

PICxmitBuf.command_data and = OxffOOfHF;

} else if (PIC_status [currentJPIC_index) .software_typc = 5) {/ * MC5 mux * / got_ver_3 = got_verJ3_3 = FALSE;

for (i = 0; i &lt;num_PICs; i ++) {

if (PIC_status [i) .get_version) {. got_ver_3 = TRUE; got_ver_3_3 = TRUE;

} else if (PIC_status [i] .software_type = 3)

- {got_ver_3 = TRUE; .

if (PIC_status [i] .software_version = 3) got_ver_3_3 = TRUE;

}} · If (got_ver_3) ·· f

&lt;.

if (got_ver_3_3 andand ((releaseCodep-&gt; option.coupIers_mask and 0x02)! = 0))

PlCxmitBuf.command_data = 0x0c007000; / * 32 bps, periodic wake-up * / ·}

else {

PICxmitBuf.command_data = 0x0c007080; / * 32 bps, no wake-up * / ł

And '}

else

PlCxmitBuf.command_data = 0x02030080; / * 205 bps, no wake-up * /}

#endif // ifdcf IS_ST5

EP 1 960 932 B1 else if. (PIC_status [current_PIC_index) .software_type = 8) {/ * Auto tune module * /

PICxmitBuf.command data = 0x02030000 | (ATM_DISC_TIME «8) | · (ATM_RC_XMIT_ON» 8) | ATM_NUM_CAP_BITS;

/ ♦ xmit offset = 2, cplr offset = 3, * / / * relay delay = ATM_DISC_TIME, Xmit mask = ATM_RC_XMIT_ON, * / / * number of capacitor relays = ATM_NUM_CAP_BITS * /}

else if (PIC_status [current_PIC_index] .software_type = 6) {/ * ST5 mux * /

PICxmitBuf.command_data = 0x00000000;

} · // endif else if (PIC_status [current_PIC_index] .software_type - 7) {/ * Load Control Module * / '· PICxmitBuf.command_data = 0x00000000;

} else {'

PIC_status [current_PIC_index] .update__parameter = FALSE;

/ * unknown software type, cancel command * /}.

if (PIC_status [current_PIC_index] .updatejparameter) · {

need_pulse_read = FALSE;

PICxmitBuf.regJED = PARM_REG; format_xmit_buffer ();

}} · Else if (PIC_status [current_PIC_index] .reset_status) {· need_pulse_read = FALSE;

PICxmitBuf.command = SYSTEM_CONTROL;

PICxmitBuf.command_data =.

(PIC_status [current_PTC_index] .status_reg_value and Oxffbf); PICxmitBuf.command_data = PICxmitBuf.command_data «16; / * Move status bits to MSb's * /

PICxmilBuf.rcg_ID = STATUSJREG; fbrmat_xmit_buffer ();

} · · Else if (PIC_status [current_PlC_index] .get status) {"need_pulse_read = FALSE;

PlCxmitBuf.conimand = READ_RJEGTSTER;

PICxmitBuf.reg_lD = STATUS_REG; format_xinit_buffer ();

} // ifdef IS_MC5 if (need_pulse_read andand (PIC_status [current_PIC_index] .soflware_type = 4)) {. need_pulse_read = FALSE;

PICxmitBuf.command = SYSTEM_CONTROL;

EP 1 960 932 B1 if (-H-piC_status [current_PIC_index] .curr_ID_reg ^&gt;= PULSES_PER_PIC) PlC_status [current_PIC_index] .curr_ID_reg = 0;

if (((((PIC_status [current_PlC_index] .PIC_addr * PULSES_PER_PIC) +

PIC_status [current_PIC_index] .curr_ID_reg)% 24)&gt; = num_pulse_ctrs)

PIC_status [current_PIC_index] .curr_ID_reg ~ 0;

PICxmitBuf.reg_ID = PIC_status [current_PIC_index] .curr_ID_reg; work_pulse_index = (PIC_status [current_PIC_index] .PIC_addr *

PULSES_PER_PIC) + PICxmitBuf.reg_lD;

for (i = 0; i &lt;lD_FIELD_LENGTH; i ++) {· · if (pulseData [work_pulse_index]. ID_buffer [i] = 0) i

j = ii; · I = ID_FIELD_LENGTH;

} }

if0 &lt;0) {

j = 0; . .

} else if (j&gt; (ED_FIELD_LENGTH-4)) {

j = TDJFIELD ^ LENGTH-4;

}

PICxmitBuf.command_data = READENCODERED | (j «8) ;; format_xmit_buffer ();

-} #endif if (need_pulse_read) {

# ifdefIS_MC5 if fPIC_status [current_PIC_index] .sofhvare_type = 7) i = PIC_status [current_PIC_index]. PIC_addr - LCM_BASE_ADDR; / * get

LCM # * / workbitmask = (load_shed_state [0] »(9 * i)) and 0x000001ff; PICxmitBuf.command_data = 0; for (i = 0; i &lt;9; i ++). .

{if ((work_bit_mask and 0x100)! = 0)

PlĆxmitBuf.command_data = (PICxmitBuf.command_data «2) + 1; / * lsb tums relay on * / else.

PICxmitBuf.command_data = (PICxmitBuf.command_data «2) + 2; / * msb tums relay on * / work_bit_mask = work_bit_mask «1;

. )

PICxmitBuf.command_data | = 0x32000000; / * Set pulse time = 50 mS * /

EP 1 960 932 B1

PICxmitBuf.command = WRITEREGISTER;

PlCxmitBuf.regJD = OUTPUT_REG; forrnat_xmit_buffer ();

need_pulse_read = FALSE;

} else and ^ endif if (PIC_status [current_PIC_index). nujn_pulse_regs = 0). {'#ifhdef ISST5

PICxmitB trust command = READREGISTER;

. . PICxmitBuf.reg_ED = VERS_REG;

format_xmit_bufferO; need_pulse_read = FALSE;

#endif}

else {

/ iifdef ISMC5 if (((((PIC_status [current_PIC_index] .PIC_addr * PULSES_PER_PIC) + PIC_status [current_PIC_index] .curr_pulse_reg)% 24)&gt; = num_pulse_ctrs)

PIC_status [current_PIC_index] .curr_pulse_reg = 0;

i / endif if (PIC_status [current_PIC_index] .curr_pulse_reg &lt;= MAX_FAST_READ) PICxmitBuf.command = PIC_status [current_PIC_index] .curr_pulse_reg;

else

- PICxmitBuf.command = READREGISTER;

PICxmitBuf.reg_ID = PIC_status [current_PIC_index] .curT._pu] se_reg;

- format_xmit_buffer (); need_pulse_read = FALSE;

. if (++ PIC_status [current_PIC_index] .curr_pulse_reg&gt; = PIC_status [current_PIC_index] .num_pulse_regs) {

. PIC_status [current_PIC_index] .curr_pulse_reg = 0; i / ifdef IS__RSM

PIC_status [current_PIC_index] .update_parameter = TRUE;

E / endif)

}

PIC_status [current_PIC_index] .last_cmd_data = PICxinilBuf.command_data; PIC_status [current_PIC_index] .last_command = PICxmitBuf.command; PIC_wait_limit = PIC_status [current_PIC_index] .repIy_wait_limit; rev_PIC_index = current_PIC_index;

if (++ current_PIC_index = num_PICs) current_PIC_index = 0;

if (! need_pulse_read)

PlC_seriaI_status- = to ^ send ^ cmd; / * Start U ART * /

EP 1 960 932 B1}

}}, #ifdef IS_RSM 7 * In RSM, generate series! stream from subseconds * / void pulseSubsecond (void) {

if (numJPICs! = 0) {·. if (PIC_cIk_state - clk_high) {'/ * Falling edge, just set clock Iow * / fsl004.io.pulse0utl0ff = 0;

PlC_clk_state = clk_low;

} else {

PIC_clk_state = clk_high;

r / include "pic.def / * Do PIC serial comm on clock rising edge * /}

} }

#endif void process_status_bits (void) from

and unsigned int work_pulse_index, work_status_bits; PIC_status [rcv_PIC_index] .get_status = FALSE;

PIC_status [rcv_PIC_index] .status_reg_value = PICrcvBuf.command_data »16;

PIC statusfrcy PIC indexl.time sińce global = (PICrcvBuf.command_data »8) and

OxFF;

if (PIC statusfrcy PIC index ~ | .status reg value! = 0) {·

PIC_status [rcv_PIC_index] .reset_status = TRUE; .

if ((PIC statusfrcy PIC indexl .status reg value and 0x8fl0)! = 0) {

PIC_status [rcv_PIC_index] .PIC_data_en_count ++; / ♦ PIC detected bad data * / set_PIC_alarm (PIC_flags_O, PIC__status [rcv_PIC_index]. PIC_addr,

PIC statusfrcy PIC index ~ | .status reg yalue); work_status_bits = (PIC statusfrcy PIC index1.status reg yalue »8) and 0x0f; work_pulse_index = PIC_status [rcv_PIC_index]. PIC_addr * PULSES_PER_P1C; while (work_status_bits&gt; 0) {. if (work_status_bits and 0x01) pulseData [work__pulse_index] .erTor_cnt ++;

EP 1 960 932 B1 \ vork_status_bits = work_status_bits »1; workjpulse_index-L +;

}} ·. · '· · If ((((PIC statuslrcy PIC index1.status reg value and 0x20)! = 0) andand! PIC_status [rcv_PIC__index], clear_pulse_regs) {'.

PlC_status [rcv_PIC_index] .comm_error_count ++; / * PIC detected comm parity err.

if (PIC_status [rcv_PTC_index] .comm_error_count&gt; 2) {

set_PIC_aIarm (PIC_comerr_0, PIC_status [rcv_PIC_index]. PIC_addr, PICrcvBuf.flags | 0x0800);

} . · }

if ((PIC statusfrcy PIC indexl.status reg yalue and 0x3080)! = 0) {

PlC_status [rcv_PIC_indexJ.PIC_reset_count-W-; / ♦ PIC was reset * / if (PIC_status [rcv_PIC_index] .PIC_reset_count&gt; 1) f {'set_PIC_alarm (PIC_reset_O, PIC_status [rcv_Pię_index] .PIC_addr,

PIC status PIC index1.status reg yalue);

}

- } } .

if (PIC_statusfrc v_PIC_index] .clear_pulse_regs andand (clear_state = GLOBAL_CLR_SENT)) {. .

• PIC_status [rcv_PIC_index] .cIear_pulse_regs = FALSE;

if ((((PIC statusfrcy PIC indexl .status reg yalue and OxOf)! = 0x0f) andand (PlC_status [rcv_PIC_index] .software_type = 3)) {

Pię_status [rcv_PIC__index] .PIC_data_err_count ++; / * Clear cmd failed * / set_PIC_alarm (PIC_flags_O, PIC_status [rcv_PIC_index]. PIC_addr,

PIC statusfrcy PIC index1.status reg yalue);

} ·· · · }

else if ((((PIC statuslrcy PIC.index ~ l.status reg yalue and OxOf)! = 0) andand ((PIC statuslrcy PIC indexl.status reg yalue and OxflO) = 0)) {

PIC_status [rcv_PIC Jndex] .PIC_data_err_count + = 1000; / * Spurious clr cmd * / set_PIC_alarm (PIC_flags_O, PIC_status [rcv_PIC_index] .PIC_addr,

PIC statusfrcy PIC indexl.status reg yalue);

} }

void set_PIC_alarm (alarmcodes pass_alarm_codes, int pass_PIC_addr, unsigned int pass_alarm_data) f

if (! Comm_background_flags.do_alarm) {

PIC_alarm.alarm_codes = pass_alann_codes + pass_PIC_addr;

EP 1 960 932 B1

PIC_alarm.ack = pass_alarm_data;

Comm_background_flags.do_alarm - TRUE;

} ' }

unsigned char workTpar;

BOOLEAN decode_rcv_buffer (void) {

int i;

unsigned int worklnt; workTpar = 0xlf; 'if (PICrcvBuf.flags = 0) {

work_PIC_addr = Get5 (); if (PJCrcvBuf.flags - 0)

PICrcvBuf.PIC_addr = work_PIC_addr; / * Valid address received * / PICrcvBuf.command = Get5 (); if (PICrcvBuf.command&gt; 0x0f)

PJCrcyBuf.regUD = Get50; else.

PlCrcvBuf.reg_ID = PICrcvBuf.eommand;

PICrcvBuf.command_data = 0; for (i = 0; i. &lt;6; and W).

PlCrcvBuf.command_data = (PICrcvBuf.command_data «5) + Get5 (); worklnt = Get5 ();

. PlCrcvBuf.command_data = (PICrcvBuf.command_data «2) + (worklnt» 3);

.. PICrcvBuf.flags | = worklnt and 0x07;

worklnt = Get5O; if (workTpar! = 0)

PICrcvBuf.flags | = rcv_tpar_error_flag;

} · / * Look up correct PIC_status index for data in rcv buffer * / for (i = 0; ((i &lt;MAX_PICS) andand (PIC_status [i] .PIC_addr! = PICrcvBuf.PIC_addr)); iw); if (i&gt; = num_PICs)

PICrcvBuf.flags | = rcv_bad addr_flag; / * past end of valid PICs, address error * / if (i =? MAX_PICS). rcv_P! C_index = 0;

else.

rcv_PlC_index = i;

3ifdefVATEST ł / ifVATĘST = l.

PlCrcYBuf.commaud = temp_command;

PICrcvBuf.reg_JD = temp ID ID;

PICrcvBuf.command_data = temp ^ commanddata;

PICrcvBuf.flags = temp_flags;

flendif tfendif

Retum ((P'CrcvB uf.flags and ~ (PIC_error_flag | PlC_need_refresh_flag | PIC_invalid_data_flag)) = O);

void format_xmit_buffer (void) f

4.

int ij, ShiftCount;

unsigned int Worklnt; unsigned long WorkData;

PICxmitBuf.bitCount = 0; '

PICxmitBuf.bits.bufLong [0] = 0;

PlCxmitBuf.bits.bufLo'ng [1] - 0; .

PICxrriitBuf.bits.bufLong [2] = 0; / * Clear xmit bit buffer ♦ / workTpar = 0x lf; / * Tpar ​​Inilialysis * /

StufT6 (PlCxmitBuf.PIC_addr);

StufF6 (PICxmitBuf.comraand); if (PICnmitBuf.command&gt; 0x0f) {

Sftłff6 (PlCxmitBuf.reg_ID); if (PiCxmitBuf.command&gt;; 0x17) {

WorkData ~ PICxmitBuf.command_data;

ShiftCount - 32; for (i - 0, i &lt;7; i ++) i

Worklnt = 0;

-for 0 = 0y &lt;5y ++) {

Worklnt = Worklnt «1; if (WorkData and 0x80000000) • Worklnt + =. 1;

WorkData = WorkData «1; if (—ShiftCount = 0) (.

Worklnt = (Worklnt «3) + (PICxmitBuf.flags and 0x07);

- j = 5 ;. · •} · '\.

Stuff6 (Worklnt);

• ··} } . }

Stuff6 (workTpar); . ·.,. / * Buffer set, set up UART control * /

PlCrcvBuf.bitCount = 66;

if ((P'C_comrn_mon.control_flags and XMIT_DATA_RDY) == · 0) {·

PIC comm_mon.xmit_buf = PICxmitBuf;

PIC comm_mon.control_flags) = XMTT_DATA RDY;

EP 1 960 932 B1

PICrcyBuff.flags = 0;

PICrcvBuf.PIC_addr = PICxmitBuf.PIC_addr; / * preset address of remote PIC * /}

unsigned int Get5 (void) {

int byte_index, bit_index;

unsigned int work_result;

work_result = 0; if ((PICrcyBuf.flags and ~ (PIC_error_flag | PIC_need_refresh_flag | PIC_invalid_data_flag)) == 0) {byte_index = 96 - PlCrcvBuf.bitCount; bit_index = byte_index and 0x07; byte_index = byte_index »3;

work_result = (PICrcvBuf.bits.bufByte [byte_index] «8) + PICrcvBuf.bits.bufByte [byte_index + 1];

work_result = work_result »(10 - bit_index); work_result and = 0x3f, if (parity6 [work_result »1]! = work_result) {

. work_result = 0;

PICrcyBuf.flags | - rcv_parity_err_flag;

else {· • work_result = work_result »1; workTpar^Λ= work__result;

PICrcvBuf.bitCount - = 6; if (PICrcvBuf.bitCount &lt;0)

PICrcyBuf.flags) = rcv_bad_length_flag;

} }

return (work_result);

} void StufF6 (int pass_data) {

int byte_index, bit_index;

workTpar pass_data;

byte_index = PICxmitBuf.bitCount »3;

bit_index = PICxmitBuf.bitCount and 0x07;

pass_data - parity6 [pass_data] "(10 - bit_index);

PICxmitBuf.bits.bufByte [byte_index] | = pass_data &gt;&gt; 8;

PICxmitBuf.bits.bufByte [byte_index + l] | = pass_data and Oxff;

PICxmitBuf.bitCount + = 6;

}

EP 1 960 932 B1

PULSE.H / * * / #ifndef BOOLEANJDEFINED #define BOOLEAN_DEFINED typedef int BOOLEAN;

#endif / * subsecond processing for pulse counters * / void pulseSubsecond (void);

/ * Daily PIC table rebuild * / void pulseDay (void);

/ * Main PIC communication routine * / void pulseService (void);

/ · PIC comm routine - once-per-second codę * / \ 'oid pulseSecond (void);

/ * Subroutines for PIC communication * / void Stuff6 (int pass_data); void format_xmit_buffer (void);

BOOLEAN decode_rcv_buffer (void); void process_status_bits (void); unsigned int Get5 (void);

void set_PIC_alarm (alarmcodes pass_alarm_type, int pass_PIC_addr,.

unsigned int pass_alarm_data);

/ * Startup codę for PIC communication * / void pulseStartup (void);

/ * Routine to elear pulse registers after cold start * / void pulseColdstart (void);

/ * defined in pt.c ♦ / #defme RELAY_A 0 #define RELAY_B 1 void pulseOut (int picNbr, int relayNbr, int ONoff); void ptEveryMinute (void); void ptEverySecond (void); void set_PLC_relays (int xmitRelay, int rcvRelay);

EP 1 960 932 B1

PICEND.DEF / * include file at end of mtrsamp to control MC and ST pic chips from mtrsamp interrupt * / # ifdefIS_MC5 if (pulseOutMode = PIC_MC_SERIAL) {

asm ("MOVE.L # Ox80400E, AO");

asm ("AND.W # 0xFCFF, (A0)"); / * Clear clock and data ports * /}

#endif # ifdefIS_ST5 asm ("MOVE.L # 0x804O0E, A0");

asm ("AND.W #OxFEFF, (AO)"); / * Insert clock falling edge * / if (PIC_serial_status = sending st5 bits) {

asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP"); asm ("NOP");

asm ("NOP");

asm ("MOVE.L # 0x804O0E, A0");

asm ("OR.W # 0x0100, (AO)"); / * If sending bits, activate clock * /}

#endif

PICVARS.DEF / * local variables to control MC and ST pic chips from mtrsamp interrupt meter / c / lib / picvars.def * / unsigned long bitOneFlag;

EP 1 960 932 B1

PULSELINK.DEF / * determine if variables are extemal or defined here ♦ / #undef ref

Wifdef PSTRU_DEFINED #define ref #else #define ref extem #endif #if (NUMPH&gt; 6) #defme IS_MC5 #else #ifdefMAX_SCAN_METERS #define IS_ST5 #else fldefine IS_RSM ł / endif // endif / * Values ​​for hdwrode () * / tfdefine STANDARD_PIC_COMM 0 #if 0 / * remove these equates from mtrlink.def * / #define PICPULSESERIAL 1 // define PIC_MC_SERIAL 2 // define PIC_ST_SERIAL 3 #endif / * then uncomment them here * / / * #define VATEST 1 * / #ifdefV ATEST // undef IS_MC5 #undefIS_RSM // undef IS_ST5 // define IS_RSM // undefNUMPH // define NUMPH 3 // undef MAX_SCAN_METERS #endif / * Uncomment for water meters (Oakville Hydro) * / // define READ_ENCODER_ID 0x49ff0000 // define READ_ENCODER_PARM 0x0312500c / * Uncomment for gas meters (Sonix) // define READJENCODER9

EP 1 960 932 B1, 7define READ_ENCODER_PARM 0x0300500c * / #define IDFEELDLENGTH 13 #define PULSES_PER_PIC 4 # ifdefIS_MC5 #define BITS_PER_SEC 822 #define MAX_Pics_ #_sese_SEC_SE_SEC_SE_ICS_TS_ICS 1 #endif tfendif #define DIRECTPICWAITLIMIT 24 tfdefine BUFFERED_PIC_WAIT_LIMIT 10 * BITS_PER_SEC #define NUM_START_BITS 12 #ifdef IS_ST5 #define REBUILDJDELAY 30000 // else // define REBUILD_Def unsigned long serial_number; unsigned long last_cmd_data;

unsigned char unsigned char unsigned char unsigned char unsigned int unsigned char unsigned char unsigned char unsigned char curr_ID_reg;

unsigned char lastcommand;

PIC_addr;

software_type;

software_version;

loop_rate; status reg val ue; time sińce global; num_pulse_regs; curr_pulse_reg;

unsigned int unsigned int unsigned int unsigned int unsigned unsigned unsigned unsigned unsigned reply_wait_l imit; PIC_data_err_count; PIC_reset_count; commerrorcount; force_pulse_read: 1;

get_semo get_version get_status reset status i;

and;

and;

and;

EP 1 960 932 B1 unsigned npdate_parameter: 1;

unsigned clear_pulse_regs; 1;

}

PICstatust;

typedef enum {sending bits, sending st5 bits, rcving_bits, do_PIC_start, sending_PIC_starŁ, do_send_cmd, sending_start, sending start 1, sending stop. waiting_for_start, rcving_stop, idle}

PIC_s_stat_t;

typedef enum {

SET_PRE_ALIGN,

DO_ALIGN,

SET_NORMAL_PLC,

DISCONNECT_COUPLER,

READ_XMIT_LEVEL

ATM_op_t;

typedef enum {

DO_PRESET,

DO_PLC_SET,

SET_ALIGN,

WAIT_ALIGN,

DO_ATM_DISCONNECT,

ATMDONE}

ATMstatet;

typedef struct {unsigned char unsigned char unsigned char unsigned long

PIC_addr; command; reg_JD; command_data;

unsigned int flags;

int bitCount;

union {unsigned long bufLong [3]; unsigned char bufByte [12];

EP 1 960 932 B1; bits;

}

PICbitBuf; 'tfifndef BOOLEANJDEFINED #define BOOLEAN_DEFINED typedef int BOOLEAN;

#endif / * Definition of bits in Flags field of PIC comm buffers * / / * ΝΟΤΕ- Top 4 bits (0x1000) reserved for use by ATM codę * / #defin e rcv_bad_addr_flag 0x0100 #define rcv_tpar_error_flag 0x0080 #define rcvagine r00_f 0x0020 // define rcv_timeout_flag 0x0010 #define rcv_parity_err_flag 0x0008 #define PlC_error_flag 0x0004 #define PIC_need_refTesh_flag 0x0002 #define PICJnvaIid_data_flag 0x0001 / * / Command codes for Pefine communication MAX_FAST_READ 0x07 #define CLEAR_PULSE_REGISTERS 0x08 r / define READ_REGISTER 0x 10 #define WRITE_REGISTER 0x18 tfdefine SYSTEM_CONTROL 0x19 / * Register ED codes for PIC communication * / tfdefine MAXJPULSEJREG 15 #define 28EGERefine CONTROUND VERS_REG 29 #define SERNOREG 30 #define STATUSJREG 31 / * Special-purpose PIC addresses * / tfdefine GLOBAL_PIC_ADDR 31 tfdefme MC5JMUX_PIC_ADDR 30 '#define ST5_MUX_PIC_ADDR 29 #define LCMJBASE_ADDR 16 / ♦ First LCM is at address 16 * / tfdefine ATM_BASE_ADDR 20 / * First ATM is at address 20 * / #define MAX_PULSE_PIC_ADDR 15 / * pulse couters are from 0 to 15 * / i * Bit usage in the ATM relay control word * /

EP 1 960 932 B1 #define ATM_RC_XMIT_ON 0x00008000 #define ATM_RC_MEAS_XMIT 0x00004000 #define ATM_RC_MEAS_CPLR 0x00002000 #defme ATM_RC_RES_SHORTED 0x00001000 #define ATM_MSCCC0000 ATM_RC_MEAS_XMIT | ATM_RC_MEAS_CPLR tfdefine ATM_PLC_CODE ATM_RC_XMIT_ON | ATM_RC_RES_SHORTED #define ATM_DISC_CODE O / * Other ATM control equates * / #define ATM_MEAS_T1ME 20L / * mSec to wait between cap change and ADC reading * / #define ATM_DISC_TIME 20L / * mSec to wait before switching cap relays * / #defme ATM_MIN_READING 0x0038 / ♦ If reading at end of autotune less than this, fail * / / * * Equates for ST5 comm * / #defme ST5_P1C_DELAY 66 #pragma region ( "ram = ram") ref unsigned short current_PIC_index, rcv_PIC_index;

ref PIC_status_t PIC_status [MAX_PICS];

struct {unsigned long reading; int error_cnt;

unsigned char ID_field [ID_FIELD_LENGTH];

unsigned char ID_buffer [ID_FIELD_LENGTH];

} ref pulseData [2 * NŁJMPH];

struct {

PICbitBuf xmit_buf;

PICbitBuf rcv_buf; int control_flags;

} ref ext_comm, PICcommmon;

struct {

ATM_op_t operation; unsigned int ATM_number;

ATM_state_t State; unsigned request_flag: 1;

unsigned done_flag: 1;

unsigned error_flag: 1;

unsigned active_flag: 1;

unsigned int start_cap_code; unsigned int end_cap_code; unsigned int optimum_cap_code;

EP 1 960 932 B1 unsigned int optimumjreading; unsigned int xmit_level; unsigned int coupler_level; unsigned int result_flags; long int align_timer;

} ref ATM_control;

struct {unsigned unsigned unsigned unsigned unsigned int unsigned int unsigned int unsigned int unsigned int request_flag: 1; donejflag: 1; error_flag: 1; active_flag: 1; xmit_mask; rcyjmask; result_flags; last_xmit_mask; last_rcv_mask;

} ref MUX_control;

struct {unsigned do_rebuild: 1; unsigned to alarm: 1;

} ref Comm_background_flags;

/ * Bit definitions in ext_buf.control_flags * / #define SUPPRESS_NORMAL_COMM 0x0001 ffdefine XMIT_REQUEST tfdefine CPY_RCV_DATA rcv_buf * / #define RCV_DATA_RDY rcv_buf * / #define

0x0002 / * Extemal routine requests send of xmit_buf * / 0x0004 / * Extemal cmd was sent, copy rcvd buffer to 0x0008 / * Got reply from extemal cmd, reply is in 0x0010 / * xmit_buf has copy of last cmd sent * /

PICxmitBuf, PICrcvBuf, HoIdrcvBuf; PIC_serial_status; numJPICs; num_LCMs; rebuild_timer;

ATMJwork; work_PIC_addr; num__pulse_ctrs; hold_num_pulse_ctrs; bit_count;

out_bit_value;

* Shift_LSB_ptr; in_bit_value;

PIC_waitJimit; zerojcount;

Iast_comm_err_flag; dontclearJPIC_stats;

ST5_PIC_delay_ctr;

PIC_bad_addr_count;

PIC_alarm;

refPICbitBuf ref PIC_s_stat_t ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned int ref unsigned char ref unsigned char ref unsigned int lef unsigned int ref unsigned int refBOOLEAN ref int ref unsigned int ref alarmstr #ifd_efVATEST

EP 1 960 932 B1 / * test !!!! * / ref int tef int reflong ref int / * test !! l! * / // endif temp_command;

tempregED;

temp_command_data;

temp_flags;

refenum {clk_high.

clk_low}

PIC_clk_state;

ref enum {

NOGLOBALSEND,

SENDGLOBALCLR,

SENDINGGLOBALCLR,

GLOBAL_CLR_SENT clear_state;

/ * Old equates maintained for compatibility * / #if 0 // define RELAY_A_BIT 1 // define RELAYJB JBIT 2 // define IDLE 0 // define TX l // define RX 2 // define DATA_READY 3 // define WAKE 4 // defme PIC_RESET 5 // define WAKECOUNTRELOAD (64 * 4) / * Four Seconds * / // define RESET_COUNT_RELOAD 10 / * 1/4 Seconds * / // define RELAY_A_OFF_CMD 5 / * active Iow trigger * / // define RELAY_A_ON_CMD 4 // define RELAYJB_OFF_CMD 7 #define RELAY_B_ON_CMD 6 // define CLEAR_ACC_CMD 8 // define SUBACC_CMD 12 // define ECHO_CMD 14 // define SLEEP_CMD 15 // define PULSE_SERIAL_COM_MAX 15 // defme WAKECMD 16 // define RESETJCMD 17 // define PULSECOMNUM 18 // define NO_PULSE_BIT_DATA 0xFFFFFFFF // define RELAY_CMD_MTN 4 // define RELAY_CMD_MA

EP 1 960 932 B1