Invalidating storage, clearing buffer entries

[0001] The invention relates generally to processing in a computational environment, and in particular to one or more memory invalidations, deletion of buffer entries, and instructions for these operations.

[0002] Existing computing environments use virtual memory, which is usually maintained in auxiliary memory, to increase the amount of available memory. When a reference to a virtual memory page is made, the virtual address used to refer to this page is translated by dynamic address translation to the actual memory address. If the translation is successful, then virtual memory is valid; otherwise it is not important. The virtual memory page is indicated as valid or invalid by the invalid bit in the page table entry, where the entry contains the actual memory address if the page is valid.

[0003] Memory pages may be invalidated one side at a time. For example, in a computing environment based on the z / Architecture architecture offered by International Business Machines Corporation, an instruction called the Revoke Page Table Entry (IPTE) instruction is used to invalidate memory pages. The annulment contains the setting of an invalid indicator in the control structure associated with virtual memory and located in physical main memory to indicate that the virtual address of the location in virtual memory cannot be translated by dynamic address translation to the physical main memory address, also called the address real. In addition, the instruction is used to delete internal buffer entries associated with the page, which entries can be used during

Dynamic real corresponding dynamic address translation in order to avoid being able to access control structures in physical main memory. For example, in z / Architecture architecture, Translation Lookaside Buffers are used when translating virtual addresses to addresses. When a memory page is unset, the buffers are also cleared of entries associated with that page.

[0004] There are also instructions that allow holistic cleaning of the Page Table Address Translation Buffers. For example, in a z / Architecture architecture, a statement, called the Compare and Replace and Delete (CSP) instructions, deletes all entries of the Page Table Address Translation Buffers.

[0005] Therefore, although there are instructions for invalidating memory pages and clearing buffers from entries associated with the page, and instructions for completely clearing buffers, there is still a need for instructions that can selectively invalidate different sizes of memory units and / or clear buffers from their associated entries. On instruction request, invalidation of the selected unit of memory specification greater than page and / or causes associated buffer entries to be deleted. In addition, there is a need for an instruction that allows deleting buffer entries for selected memory units without affecting buffer entries for other memory units.

[0006] From the document "Enterprise System Architecture / 390 Principles of Operation" [Online] July 31, 2001,

XP002294122, downloaded from the website, URL:

<a href="http://publibz.boulder.ibm.com/%20epubs/pdf/dz9ar007.pdf">http: //publibz.boulder.ibm.com/_epubs/pdf/dz9ar007 .pdf</a>&gt;, example, exists which enables

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- 4 we learn about the selective deletion of entries in the buffer based on the starting address of the page table.

[0007] From US 2003/074541 A1 we learn that there are other forms of translation tables start addresses containing the start addresses of the segment tables and the start addresses of the area tables.

[0008] The present invention provides a method of invalidating the computing environment memory as claimed in claim 1.

[0009] Preferably, the present invention provides a method of invalidating computing environment memory. The method includes, for example, specifying a memory unit to be invalidated, the memory unit comprising a plurality of pages of memory, wherein specifying a memory unit includes providing a descriptor of the memory unit; and invalidating the memory unit.

[0010] Preferably, the present invention provides a method that facilitates cleaning of computing environment buffers. The method includes, for example, identifying a memory unit for which to delete one or more entries in one or more buffers, wherein the memory unit comprises a plurality of pages of memory; and deleting one or more entries in one or more buffers associated with the identified memory unit, wherein one or more entries associated with the next storage unit are not deleted.

[0011] Preferably, an instruction is provided to be executed in a computing environment. This instruction includes, for example, an operation code to identify the instruction to be executed;

designating invalidation to specify information related to the memory unit to be invalidated, the memory unit comprising a plurality of

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- 5 pages of memory; subsequent designation to specify additional information used by the instruction;

and determining deletion to specify information related to one memory unit and another memory unit for which one or more entries in one or more buffers are to be deleted, wherein one or more components of one or more cancellation designations, subsequent designation and deletion designation are configurable as blank commands.

[0012] Preferably, an instruction is provided to be executed in a computing environment. The instruction includes, for example, an operation code to identify the instruction to be executed and at least one element of the following:

a first cancellation designation to specify information related to the memory unit to be invalidated, the memory unit comprising a plurality of pages of memory; a second revocation designation to specify additional information related to the memory unit to be revoked; and designating deletion to specify information related to one of the memory units and the next memory unit for which one or more entries in one or more buffers are to be deleted, the information specified by deleting designation not associated with at least one another memory unit for which one or more entries are not to be deleted.

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[0013] A computer program system and products corresponding to the above method summary is also described and claimed herein.

[0014] Additional features and advantages are obtained by the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered to be part of the claimed invention.

[0015] The subject matter of the invention is particularly emphasized and expressly claimed in the claims at the end of the description. The above and other objects, features and advantages of the invention will be apparent from the following detailed description, together with the accompanying drawings, in which:

Fig. 1 shows one computing environment using one or more of the invention;

Fig. 2 shows an embodiment and aspects of the present embodiment one additional detail related to the controller of Fig. 1, according to an aspect of the present invention;

Fig. 3 shows one embodiment of a host computer that can emulate another computer, according to an aspect of the present invention;

Fig. 4 shows one embodiment of a logic circuit associated with invalidating memory according to an aspect of the present invention;

Fig. 5 illustrates one embodiment of the logic associated with clearing buffer entries, according to an aspect of the present invention;

Fig. 6a shows one embodiment of the format of the Invalid Entry in the Dynamic Table instruction

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- Address Translation (IDTE) according to an aspect of the present invention;

Fig. 6b illustrates one embodiment of the fields associated with the general purpose register R1 of the IDTE instruction in Fig. 6a, according to an aspect of the present invention;

Fig. 6c illustrates one embodiment of the fields associated with general register R2 of the IDTE instruction in Fig. 6a, according to an aspect of the present invention;

Fig. 6d illustrates one embodiment of the fields associated with the general purpose register R3 of the IDTE instruction in Fig. 6a, according to an aspect of the present invention;

Figures 7a-7b illustrate one embodiment of the logic associated with an IDTE instruction according to an aspect of the present invention;

Fig. 8a illustrates one embodiment of the general purpose register fields R1 used in the alternative operation of the IDTE instruction according to an aspect of the present invention;

Fig. 8b illustrates one embodiment of the general purpose registry fields R2 used in the alternative operation of the IDTE instruction according to an aspect of the present invention;

Fig. 8c illustrates one embodiment of the R3 general purpose registry fields used in the alternative operation of the IDTE instruction according to an aspect of the present invention; and

Fig. 9 illustrates one embodiment of the logic associated with the alternative operation of the IDTE instruction according to an aspect of the present invention.

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[0016] According to an aspect of the present invention, the specified portion of the memory (e.g. virtual memory) is invalidated. As examples for invalidation, a memory segment that contains multiple memory pages or a memory area that contains multiple memory segments is selected. Revocation is facilitated by setting revocation indicators located in the data structure entries corresponding to the memory units to be revoked. In a further aspect of the present invention, buffer entries (e.g., Table Table Address Translation Buffer entries) associated with invalidated memory, or other memory, are removed. Furthermore, in yet another aspect of the present invention, buffer entries associated with selected address spaces are removed from the buffers without affecting the buffer entries of non-selected address spaces and without performing invalidation. In one example, the statement here referred to as the Invalid Array Dynamic Address Translation (DAT) entry from the IBM® z / Architecture is used to perform one or more of the above operations. [0017] One embodiment of the computing environment 100, incorporating and using one or more aspects of the present invention, will be described with reference to Fig. 1. Computing environment 100 is based, for example, on z / Architecture architecture offered by International Business Machines Corporation of Armonk, New York. The z / Architecture architecture is described in the IBM® publication entitled "z / Architecture Principles of Operation", IBM Publication No. SA22-7832-00, December 2000. (IBM® is a registered trademark of International Business Machines Corporation of Armonk, New York, USA. Other names used herein may be registered trademarks,

Trademarks or product names of International Business Machines Corporation or other companies). In one example, a z / Architecture computing environment includes the zSeries eServer, offered by International Business Machines Corporation of Armonk, New York.

As one example, the computing environment 100 includes a central processor assembly (CPC) 102 connected to a controller 120. The central processor assembly 102 includes, for example, one or more partitions 104 (e.g.

LP1-LPn logical partitions), one or more central processors 106 (e.g., CP1-CPm) and supervisor 108 (e.g., logical partition management), each of which is described below.

[0018] Each logical partition 104 is able to function as a separate system. That is, each logical partition can be independently reset with a pre-loaded operating system if required and run with different programs. The operating system or application program executing in the logical partition gives the impression that it has access to the entire and complete system, but in reality only part of it is available. The combination of computer hardware and Licensed Internal Code (usually called a microprogram) does not allow the program from a different logical partition to interfere with the program in the logical partition. This allows several different logical partitions to run on one or more physical processors using time sharing. In this particular example, each logical partition has a resident operating system 110, which may be different from one or more partitions. In one embodiment, operating system 110 is an z / OS operating system offered by

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- 10 relevant headquarters of the International Business Machines Corporation of Armonk, New York.

[0019] Central processors 106 are physical processor resources that are allocated to logical partitions. For example, logical partition 104 contains one or more logical processors, each of which represents all or part of the physical processor resources 106 allocated to the partition. The logical processors of a given partition 104 can either be allocated to the partition so that the basic processor resources are reserved for that partition, or shared with the next partition so that the basic processor resources are potentially available for the next partition.

Logical partitions 104 are managed by supervisor 108, implemented by the microprocessor, executing on processors 106. Logical partitions 104 and supervisor 108 are one or more programs located in parts of the central memory associated with the processors. One example of supervisor 108 is the Processor Resource / System Manager (PR / SM) offered by International Business Machines Corporation of Armonk, New York.

[0020] The controller 120, which is connected to the central processor assembly, includes a central logic responsible for granting access between different processors requesting. For example, when the controller 120 receives the request, it determines that the requester is the master processor for that request and that the other processors are slave processors; broadcasts messages; and also supports requests. One example of a controller is described in US Patent No. 6,199,219.

Further details are also described with reference to Fig.

2. Fig. 2 shows one example of the controller 200,

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- 11 connected to multiple central processors (CPUs) 201. This example shows two central processors. However, it will be understood that more than two processors can be connected to the controller 200.

[0021] The controller 200 includes various control systems including, for example, system serialization control system 202. The system serialization control is used to ensure that operations to be serialized, such as invalidation instructions, are serialized, that is, only one such instruction is executed at a time in the computing environment. It also monitors the sequence of events for this operation.

[0022] The controller 200 is connected to each central processor via various interfaces. For example, interface 204 is used by the Licensed Internal Code in a central processor to send "control" commands to the controller that specify the actions to be performed and to send "read" commands that return information from the controller. Another interface is the response bus 206, which is used to return information from the controller for "read" commands. The response bus is also used to send command status for "control" commands and can be set from many sources within the controller containing the system serialization control. The central processor can use this interface to read the status of the system serialization control in the 200 controller.

[0023] Another interface is interface 208, which is used by the controller to send commands to each CPU. It can also be controlled from a number of sources within a controller comprising the system serialization control 202. Another interface is the 210 interface,

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Which supplies signals to central processor 201 cache control circuits 212. Cache control circuit 212 processes the commands in response to the signals. In one example, cache control system 212 processes commands that affect one or more buffers, such as Page Table Translation Buffers 213 (TLBs), as described in detail below.

[0024] In addition to the cache control system 212, the central processor 201 includes various other control systems including, for example, interrupt control systems 220 and performance control systems 222. In response to individual events, interrupt control circuits 220 cause an internal interrupt pending in the CPU, which in turn causes execution control circuits 222 to suspend the processing of program instructions at the next interruptible moment. In response to an interrupt, the execution control circuits 222 call the Licensed Internal Code procedure to set the latch 224 of the allowed broadcast operation to allow the cache control circuits 212 to process the wait commands.

[0025] The central processor 201 also includes a CPU latch 226 at rest, which indicates whether the central processor is at rest or not.

[0026] The computing environment described above is just one example. For example, one or more partitions can run on different types of architecture. In addition, as another example, the environment does not have to be based on z / Architecture, and instead can be based on other architectures offered by Intel, Sun Microsystems, as well as other companies. In addition, the environment may contain an emulator (e.g., software or

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- 13 other emulating mechanisms) in which a specific architecture or its subassembly is emulated. In such an environment, one or more emulator functions may implement one or more aspects of the present invention, even though the computer performing the emulator may have a different architecture than the emulated capabilities. As one example, in emulation mode, a specific instruction or emulated operation is decoded, and a corresponding emulation function is created to implement an individual instruction or operation.

[0027] Further emulation details discussed with reference to Fig. 3. the host computer 300 has environments will be

As one example, emulate another architecture, computer and / or processing ability of another computer. For example, the host computer 300 is based on Intel architecture; RISC architecture such as PowerPC; SPARC architecture, offered by Sun Microsystems; or other architecture and has the ability to emulate IBM® z / Architecture or other IBM® or third-party architecture.

The host computer 300 includes, for example, memory 302 for storing instructions and data; instruction download unit 304 for the instruction to download from the memory 302 and optionally to provide local buffering of the downloaded instructions; instruction decoding unit 306 for receiving instructions from the instruction retrieval unit 304 and for specifying the type of instruction that has been downloaded and instruction execution unit 308 for executing the instruction. Execution may include entering data into the register from memory 302; saving data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the decoding unit.

[0028] In one example, each unit described above is implemented in software. For example, operations to be performed by entities are implemented as one or more subprograms in the emulator program. In another example, one or more operations are implemented in the firmware, computer hardware, software or some combinations thereof.

[0029] Furthermore, although Fig. 3 is described with reference to emulation, the environment of Fig. 3 does not need to be emulated In a further example, in a native environment and implemented in computer hardware, hardware, software or in some combinations thereof. [0030] The computing environment may include virtual memory as well as main memory. Virtual memory can significantly exceed the size of main memory, instructions are operations are the software available configuration is usually maintained in auxiliary memory. Virtual memory is thought to be made up of blocks of addresses, called pages. Recent references to virtual memory pages are assigned to occupy physical main memory blocks. When a user references virtual memory pages that are not in main storage, virtual pages are downloaded to replace pages in main storage that are less likely to be used. Swapping pages in memory can be done by the operating system without the user's knowledge.

[0031] The addresses used to designate locations in virtual memory are called virtual addresses. A block of sequential connection of virtual addresses, for example, up to 4 kilobytes is called a page. Similarly, a block of sequential connection of virtual pages, for example, to

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- 15 1 megabyte is called a segment; and a block of sequential connection of virtual segments, for example, up to 2 gigabytes is called an area. In addition, the sequence of virtual addresses associated with virtual memory indicated by the address space control (ASCE) is called the address space. Address spaces can be used to provide degrees of isolation between users. An address space may contain one or more areas, one or more segments, one or more pages, or some combinations thereof.

[0032] Related to different types of memory units (e.g., areas, segments, pages) are data structures used in processing associated with memory units. For example, area tables are associated with area tables; segment tables are associated with segments; and pages are associated with pages. These arrays are used, for example, during translation (e.g. Dynamic Address Translation) of a virtual address to a real address that is used to access main storage. The tables used in translation, referred to herein as the translation tables, are designated by the address space control (ASCE). This is described in more detail in the IBM® publication entitled "z / Architecture, Principles of Operation", IBM publication No. SA22-7832-00, December 2000. A unit of virtual memory that is not currently assigned to the main memory is called invalid. The invalid state of a virtual memory unit is indicated by an invalid indicator in the data structure associated with that unit.

[0033] The dynamic address translation mechanism is implemented in one embodiment such that information obtained from translation tables (e.g., area tables, segment tables, and / or page tables) during

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16 DAT processes are stored in one or more buffers located inside processors, called Page Table Address Translation Buffers, to enhance address translation efficiency. That is, during translation it is checked if the buffers contain the necessary information, and then, if there is no information in the buffers, one or more translation tables are provided.

[0034] In one embodiment, the buffer entry is treated as one of three types: TLB entry of combined area and segment tables; page table TLB entry; or a real space TLB entry, each of which will be described below.

[0035] The TLB entry of combined area and segment tables (CRSTE) contains both information obtained from the table entry or entries in real or absolute memory, and attributes used to retrieve this information from memory. In one example, the TLB entry of combined area and segment (CRSTE) tables contains the following fields:

TO - the starting address of the table in the address space control element used to create the entry;

RX - virtual address area index used to create the entry;

SX - virtual address segment index used to create the entry;

PTO - starting address of the page table, retrieved from the segment table entry in real or absolute memory;

C - common segment bit, retrieved from the segment table entry in real or absolute memory; and P - page protection bit, taken from the segment table entry in real or absolute memory.

[0036] V - The validity bit indicates whether the entry in the TLB is valid and thus, can be used to search subsequent entries.

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[0037] The TLB page table entry contains information obtained from the table entry or entries in real or absolute memory and the attributes used to retrieve this information from memory. In one example, an entry in the TLB page table contains:

TO - the start address of the table in the address space control element or TLB entry of the combined area and segment tables, used to create the entry, depending on how the entry was created;

PTO - starting address of the page table, used to create the entry;

PX - index of the virtual address page used to create the entry;

PFRA - real address of the page frame, taken from the entry for the page table in real or absolute memory; and

P - page protection bit, retrieved from the page table entry in real or absolute memory.

[0038] V - The validity bit indicates whether the entry in the TLB is valid and therefore, can be used to search subsequent entries.

[0039] Sometimes the memory unit is to be invalidated. To facilitate this invalidation, a translation table associated with this memory unit is used, as described herein. In addition, in response to memory invalidation, the corresponding buffer entries can also be deleted. For example, to invalidate a memory page, an invalid bit is set in the page table entry. Additionally, in one example, the corresponding entries in one or more TLBs are undivided. In one particular example, invalidation and deletion

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- 18 entries related to memory pages are performed by the instruction Revoke Entry in Page Table (IPTE).

[0040] In addition to invalidating memory pages in connection with an aspect of the present invention, memory segments and / or memory areas may be invalidated. As one example, segment and / or area tables are used for this invalidation. One embodiment of the logic associated with invalidating a specific memory unit is described with reference to Fig. 4.

[0041] Initially, the area or segment table in which one or more entries are to be invalidated, STEP 400 is identified. In one example, this includes providing the region table start address or segment table start address. Next, the entry within the designated area or segment table to be canceled is identified, STAGE 402 and this entry is canceled, STAGE 404. In one example, the identification is made by providing an area index or segment index (real address bits) that selects an entry within an identified table and the invalidation includes setting an invalid indicator within the entry. In response to the setting of the invalid indicator, the corresponding memory unit (e.g. area or segment) is invalidated. Then it is determined whether there are more entries to be canceled, QUESTION 406. If there are more entries to be revoked, then processing will continue from STEP 402. Otherwise, processing will end.

[0042] In addition to the invalidation of one or more entries in the area or segment table, and thus the invalidation of these memory units, the corresponding entries (or other entries) may be removed or cleaned from one or more buffers on one or more processors in the environment. One

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- the embodiment of the logic associated with this removal is further described in more detail with reference to Fig. 5.

[0043] It is initially determined whether the start address of the area or segment table, QUESTION 500 will be specified. If the start address of the area or segment table is specified, then the entries specified by the area or segment index that corresponds to the address are removed from one or more buffers. initial area or segment, STEP 502. Next, it is determined if there are more entries to be deleted, QUESTION 504. If so, then processing will continue from STEP 502. Otherwise, processing will end.

Returning to QUESTION 500, if the start address of the area or segment table is not specified, then the entries specified by the area or segment index, STEP 508, are removed from one or more buffers. Then, it is determined whether there are more entries that have be deleted, QUESTION 510. If there are more entries to delete, then processing continues at STEP 508. Otherwise, processing is terminated.

[0045] In one example, invalidation and deletion are performed by one instruction. The instruction invalidates the selected entries in the segment or area table and indivisibly deletes at least the corresponding entries (or other entries) from the TLB in processors of the given configuration. In one example, entries are cleared of all TLBs on all processors, physical, virtual, or software emulated. If there is a multi-level TLB structure, then all levels are cleaned in one example. If it exists in the system

If there are many logical partitions, then TLB entries in this and other processors that were created for the logical partition in which the current IDTE instruction is executed are cleared.

[0046] The instruction can be implemented in many architectures and can be emulated. For example, the instruction may be executed in hardware by the processor; or by emulating an instruction set containing this instruction by software executed on a computer having various internal instruction sets. In one particular case, the instruction is implemented in a z / Architecture architecture and is called an Invalid Table Entry (IDTE) Dynamic Address Translation (DAT) instruction.

[0047] IDTE provides, for example, an invalidation and delete option in which one or more areas or memory segments are invalidated by one or more entries of the region table or from the segment table and at least the corresponding entries (or others e.g. of all buffers) are cleared. TLB) in

The manual specifies the minimum set to be cleaned. In further entries) from the configuration TLB buffers.

TLB entries, implementations, more or even all TLB entries can be cleared after executing the IDTE instruction.

[0048] One embodiment of the DAT Invalidation format of the Table entry (IDTE) is described with reference to Fig. 6a. In one example, the IDTE instruction 600 includes, for example, operation code 602 designating the DAT Invalidation instruction of the Table Entry (e.g., 'B98E'x) and multiple registers 604-608. Each of these registers is described in more detail below with reference to Figs. 6b-6d.

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[0049] Referring to Fig. 6b, register 606, which is general purpose register R1, has, for example, the format of the address space control element with the table start address (e.g. bits 0-51) and determination type control (bits 60 and 61). Bits 52-59, 62 and 63 are ignored. In particular, R1 includes, for example, the start address 610 of an area table or segment table for invalidation, which designates a translation table from which one or more entries are to be invalidated; and designation type control (DT) 612 that specifies the type of this table (e.g., area table or segment table). [0050] Register 608 (Fig. 6c), which is a general purpose register, R2 contains the first area index 614, detailing the first level area table; a second area index 616 detailing a second level area table; and a third area index 618 listing the third level area table. That is, to customize large virtual addresses, three levels of area tables are used. Register R2 also contains a segment index 620, which is an index in the segment table; mode indicator 621 that specifies the function to be performed; and an indicator 622 additional entries, which indicates how many entries are to be canceled. For example, bits 53-63 of general register R2 contain a binary integer specifying the number of additional entries in the table to be invalidated. In one example, the number of entries to be invalidated is 1-2048, corresponding to 0-2047 bits 53-63. Bits 44-51 of general register R2 are zero; otherwise the specification exception is recognized. Thus, bits 0-43 of general register R2 have the format of the area index and the virtual address segment index. Part of bits 0-43 used by DAT to select an entry in

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The 22 table type designated by the general purpose register R1 is called the Effective Cancellation Index and is described in detail below.

[0051] Register 604 (Fig. 6d), which is general register R3, has, for example, the format of the address space control element, using the table start address, bits 0-51 if it is non-zero. This table start address is used to select the TLB entries to be deleted, and the type of table it designates is independent of bits 60 and 61 of general register R1. Bits 52-63 of general register R3 are ignored. If R3 is zero, all contents of general register 0 are ignored. In one example, the entries to be deleted may be the same or different than the entries being invalidated.

[0052] One embodiment of the logic associated with the invalidation and removal operation is described with reference to Figs. 7a-7b. In one example, the invalidation and delete operation is determined when bit 52 of general register R2 is zero. In this operation, the designated entry in the area table or the entry in the segment table in memory or the range of entries starting with the designated entry is invalidated and the corresponding table entries (or other entries) are removed from the page table address translation (TLB) buffers in the CPUs in the configuration. . In one example, all buffer levels are cleared on all CPUs if they are multi-level.

[0053] Referring to Fig. 7a, the start address of the area table or segment table is initially determined, designating the area table or segment table from which one or more entries are to be invalidated, STEP 700.

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- 23 one example is established in the general purpose register R1. In addition, the table entry in the memory to be invalidated is selected, STEP 702. In one example, the table entry is determined by adding the table start address in general register R1 and the effective invalidation index in general register R2 and following different rules as described here.

[0054] Bits 60 and 61 of general register R1 specify the type of invalidation table as follows:

Bits 60 and in Reg. Type of array R1 and effective index

Effective Cancellation Index in Reg. R2

First area table Second area table Third area table

Segment table

First area index (bits 0-10) Second area index (bits 11-21) Third area index (bits 22-32) Segment index (bits 33-43) (Some bits 0-43 on the right of the effective invalidation index are ignored) [0055] With reference to the above table, when bits 60 and 61 have a binary value of 11, the first area index in Part R2 together with the start address of the first area table in R1 are used to select the entry in the first area table. The start table address is treated as a 64-bit address.

This 64-bit address of the entry in the first area table in real or absolute memory is obtained by attaching twelve zeros to the right of bits 0-51 determining the first area table and adding the first area index with three attached zeros located

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- 24 most right and fifty attached zeros most left. This addition is performed according to the rules of 64-bit address arithmetic, regardless of the current addressing mode, specified by bits 31 and 32 of the current Program State Word (PSW). When a transfer from a zero bit position occurs during the addition, it is ignored. The address created from these two components is real or absolute. All 64 bits of the address are used regardless of whether the current PSW specifies the 24-bit, 31-bit or 64-bit addressing mode.

[0056] In one example, the entire entry in the first area table is fetched concurrently from memory as used by other CPUs. Access to fetching the entry is subject to key control protection, while access to memory is subject to key control protection and low address protection. When the memory address generated for fetching an entry in the first area table designates a location that is not available in the configuration, an addressing exception is recognized and the unit of operation is removed.

[0057] When bits 60 and 61 have a binary value of 10, the second area index in R2 together with the start address of the second area table in R1 is used to select an entry from the second area table. The process of searching the second area table is similar to the process of searching the first area table. When no exceptions are recognized, the entry fetched from the second area table specifies the beginning and specifies the offset and length of the corresponding third area table.

[0058] When bits 60 and 61 have a binary value of 01, the third area index in Part R2 together with the start address of the third area table in R1 is used to select an entry from the third area table. Searching process

The third area table is similar to the process of searching the first area table. When no exceptions are recognized, the entry fetched from the third area table designates the beginning and sets the offset in the length of the corresponding segment table.

[0059] When bits 60 and 61 have a binary value of 00, the segment index in part R2 together with the starting address of the segment table in R1 is used to select an entry from the segment table. The process of searching the segment table is similar to the process of searching the first area table. When no exceptions are recognized, the entry fetched from the segment table designates the beginning of the corresponding page table.

[0060] In one example, the entire table entry is fetched concurrently from memory. Then the entry is invalidated, STEP 704. In one example, the entry is invalidated by setting bit 58 of the entry to binary value 1. By invalidating this entry, the corresponding memory unit is invalidated.

[0061] Next, it is determined whether more entries are to be annulled, QUESTION 706. In one example, it is determined by checking bits 53-63 of general register R2. If bits 53-63 of general register R2 are not all null, then more entries are to be invalidated. Thus 1 is added to the previously used effective revocation index value and processing continues at STEP 700. This is repeated so that the number of entries one greater than the number specified by bits 53-63 is invalidated. The transfer from the leftmost bit position in the effective invalidation index is ignored and in this case a circular transition occurs in the table.

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- 26 The content of the general purpose register R2 remains unchanged.

[0062] Then, after invalidating one or more entries, according to another aspect of the present invention, given from its TLBs and configuration so that the CPU deletes selected entries signals the remaining CPU in the given delete selected entries from its TLBs, STEP 708. In one example, each TLB is cleaned, at least from those combined Area and Segment Table (CRSTE) entries that meet the following conditions:

[0063] The effective invalidation index and bits to its left in general register R2 and the same part of the area index of the area and segment in the TLB entry match. (In one embodiment, if these fields contain segment index fields then CRSTE may be cleaned regardless of their area index fields or all CRSTE may be cleaned. If the fields do not contain segment index fields, all CRSTE may be cleaned). It should be noted that when many entries in the table are invalidated due to bits 53-63 in general register R2, then the effective invalidation index is increased and the position of the bit located furthest to the left of the index is lost.

[0064] Either R3 is zero or the table start address field in general register R3 corresponds to the table start address field in the TLB entry.

[0065] If the invalidated entry is an entry in the segment table, the page address of the initial page table in the invalidated entry corresponds to the field of the initial address of the page table in the TLB entry. (In one embodiment, the TLB entry can be deleted regardless of the start address of the page table in the entry.)

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[0066] Each TLB is also cleaned, at least with a related reference to Fig.

those entries in the page table in which the starting address field of the page table corresponds to the starting address field of the page table in (1) the invalidated entry in the segment table, if the entry in the segment table has been canceled, or (2) any entry of the combined area and segment table has been deleted (included in the kit to be removed) in the same TLB. (In another embodiment, the implementation may delete the entry in the page table regardless of the start address of the page table in the entry. This may therefore delete all entries in the page tables.) [0067] One embodiment of the logic removing entries from the TLB is described in As one example, this is

7b.

the continuation of processing performed by IDTE is performed relative to invalidation, as other CPUs are used indivisibly by the given CPU and system.

[0068] Referring to Fig. 7b, it is initially determined whether R3 is zero, QUESTION 720. If R3 is nonzero, then the start address of the area or segment table to be deleted is indicated in register R3, to delete the TLB entry, start address of the area table / segment designated in the R3 register, is to correspond to the start address of the area / segment table used to create the entry, STEP 722. If R3 is zero, the contents of register R3 (register 0) are ignored and the entry is deleted regardless of the start address of the area / segment table used to create the entry, STEP 724. [0069] TLB is cleared of all processors in the system from these entries specified by the area / segment index specified in the R2 register, STEP 726. In one example, the TLB is cleaned with at least

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- 28 of those entries of the combined area and segment tables, in which, for example, the effective invalidation index and bits from its left in general register R2, and the same part of the area and segment table index in the TLB entry match. As one example, to delete an entry, the V bit is disabled.

[0070] Also, if the entry in the segment table is invalidated, then the TLB buffers on all processors in the system are cleared of entries in the page table in which the start address of the page table in the entry is equal to the start address of the page table in TLB, STEP 728. In addition, if an entry in the segment table is overridden, TLB buffers are cleared, at least from those entries in the page table, in which the starting address field of the page table corresponds to the starting address field of the page table in any CRSTE that has been deleted (e.g. necessarily) in thereby TLB, STEP 730. The cleaning process is repeated for the number of entries one greater than the number specified in field 622 additional entries in Fig. 6c,

INQUIRY 734. In one is not completed in

STEP 732.

[0071] Next, it is determined whether the invalidation and cleanup operation is completed, example, IDTE instruction of the calling processor until the marked TLB entries are deleted in the given CPU and all other CPUs in the system complete any memory calls using the TLB entry specified in this manual. In one example, it is the resting state controller that signals to the calling processor whether other processors have terminated the calling processor and any processors from their calls. is considered subordinate, on the IDTE instruction indicate to the driver

That is, a given main processor that affects its states. IN

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- 29 responses to the controller receiving appropriate states from slave processors, signaling the termination of the main processor. If processing is completed, then the instruction is terminated, STEP 736. Otherwise, the processor waits for a predetermined amount of time and checks the status again or receives a signal as to completion, QUESTION 734.

[0072] In one embodiment, writing an area or segment table entry and deleting TLB entries may or may not occur if the invalid bit has already been set to one in the area or segment table entry.

[0073] Although in the embodiment described above, the removal of TLB entries is performed after invalidation of the desired entries, in other embodiments, the removal of TLB entries may occur after each cancellation, after a selected number of cancellations, etc.

[0074] In another aspect of the present invention, the IDTE instruction can alternatively be used to clear TLB entries associated with the address space (e.g., designated by the Address Space Control (ASCE)). In one example, this option is indicated by setting bit 52 in general register R2 to 1. In this option, the contents of general register R1 are ignored (see Fig. 8a), as well as bits 0-43 and 53-63 of general register R2 (see Fig. 8b). The contents of the general purpose register R3 have the format of an address space control element with the table starting address in use, bits 0-51 (Fig. 8c). Bits 52-63 of general register R3 are ignored. R3 can be zero or non-zero; it is any general purpose register containing register 0 that can be designated. This operation does not perform

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- no invalidation of the memory, but clears the TLB buffers in the CPUs in the configuration, at least from those entries of the combined area and segment table and entries in the page tables in which the table's start address field corresponds to the table's start address field in general register R3. (In another embodiment, the implementation may delete the entry in the page table, regardless of the starting address of the entry table. That is, it may delete all entries in the page table.)

[0075] One embodiment of the logic associated with cleaning by an ASCE operation is described with reference to Fig. 9. Initially, the start address of the area table or segment table is specified, designating the area table or segment table for which the corresponding TLB entries have be deleted, STEP 900. In one example, this is listed in bits 0-51 of the general register R3. Then, at least entries of the combined area and segment table and page table entries corresponding to the start address of the tables specified in R3 are deleted on all processors in the system, STEP 902.

[0076] Next, it is determined whether the execution of the IDTE instruction is completed, QUESTION 904. In one embodiment, the IDTE instruction is not completed on the calling processor until the TLB entries corresponding to the specified parameters are deleted on the calling CPU and other CPUs in the configuration are not will terminate any memory calls containing change bit and reference bits using TLB entries corresponding to the specified parameters. If entries have been deleted and memory calls have been completed, the IDTE instruction is completed, STEP 906. Otherwise, the processor waits for a predetermined amount of time.

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- 31 and checking the status again or receiving an end signal, QUESTION 904.

[0077] The processing associated with the IDTE instruction has been described in detail above. In one embodiment, operations need not necessarily affect TLB space entries. The following notes provide actual additional and / or examples of information, implementation extensions related to processing one embodiment of the IDTE instruction.

1. Selective deletion of TLB entries can be implemented in different ways, depending on the model or selected embodiment. For example, generally, more entries can be deleted than the minimum number specified. When the invalidation and delete operation is performed, all combined area and segment table (CSRTE) entries that contain a segment index equal to the effective invalidation index, which is the segment index, can be deleted or all CRSTE entries can be deleted when the effective invalidation index is not an index segment. In addition, CRSTE or a page table entry can be deleted regardless of the start address of the page table in the entry. When the ASCE delete operation is performed, the page table entry can be deleted regardless of the start address of the table in the entry. When one of these operations is performed in one embodiment, the precise minimum number of entries required can be removed.

2. The address space control may include a real space start address tag instead of the start address of the area table or segment table. Starting address of the table in

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- 32 general purpose register R3 is indistinguishable from the start address flag in the register.

3. When an invalidation and delete operation is specified, TLB entries can be removed using the page table start address in the segment table entry. Therefore, if an entry in the segment table in an attached state contains the start address of the page table that differs from the current value, copies of entries containing previous values ​​may remain in the TLB.

4. When the invalidation and deletion operation is specified, the address of the entry in the DAT table for IDTE is a 64-bit address and the arithmetic of the address is performed according to the usual rules arithmetic of 64-bit address metrics with cyclic transition for 2⁶⁴ - 1. Also, offset and length fields are not used. Accordingly, DAT tables are not to be specified for moving from the maximum memory locations to location 0, and the first designated entry and all additional entries specified by bits 63-63 of general register R3 should fit within the designated table.

5. The IDTE instruction is subject to interception under SIE. In one embodiment, the system is serialized such that the processor executing the IDTE instruction cannot start the operation until the other processors stop using the TLB entries to be specified. In addition, the processor executing the IDTE instruction does not continue until the corresponding entries are removed from the TLBs of all processors on the system.

6. The serialization function is performed before the operation begins and again after completion

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- 33 operations. Serialization refers to the CPU; other CPUs are not necessary serialized.

[0078] Above is described in detail one example of an instruction that can invalidate entries for a segment table or area and undividedly delete at least the corresponding entries (or other entries) from one or more page address translation buffers. Different operation codes, different fields, different registers can be used, or even no registers, different bits etc. can be used. For example, other instruction set architectures may define the equivalent instruction in some other way (e.g., other operation codes used, other fields in the instruction, other registers, etc.), but one or more aspects of the present invention still apply. In addition, as described above, one or more aspects of the present invention relate equally well to emulation of target architecture software, such as IBM z / Architecture. In this case, the TLB buffers described above may be an array or other data structure implemented by the software emulator to store the last virtual to real mappings. It may also be that the emulator software does not implement any structure similar to TLB. In this case, only invalidating entries in memory can be used.

[0079] Thus, an instruction is provided here that is capable of invalidating the memory, invalidating the memory and indivisibly deleting the buffer entries or deleting the buffer entries. Therefore, it is said that one or more instruction registers are configured as blank commands ("do nothing"). That is, information in these registers, if any, related to a specific operation (e.g.

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- 34 cancellations, deletions, etc.) that are not provided are ignored.

[0080] Although the instruction in or indicate that the operation is not specifically described is invalidation, above which invalidation and deletion or removal are provided, the instruction may be modified or other instructions may be implemented that simply perform one or more aspects operations implemented by IDTE. For example, the instruction may simply implement memory invalidation. As another example, an instruction can simply clean up entries from buffers that are associated with a given segment or area table. As yet another example, an instruction can be implemented that simply cleans the entries based on the address space.

[0081] In the commercial implementation of the invalidation and / or removal function in the form of a computer-based instruction format of a particular architecture, the instructions are used by programmers, such as operating system programmers writing in assembler language. The instruction formats saved in the storage medium can be executed in a native IBM server with z / Architecture architecture or alternatively in devices implementing other architectures. They can be emulated in existing or future IBM mainframe servers and in other IBM devices (e.g. pSeries Servers and xSeries Servers). They can be performed in devices running on the Linux system in various devices using equipment manufactured by IBM, Intel, AMD, Sun Microsystems and other companies. In addition to performing in hardware with z / Architecture architecture, Linux can be used, as well as devices that use emulation implemented by

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- 35 Hercules, UMX, FXI or Solutions Platform, where, as a rule, the program is executed in emulation mode.

In emulation mode, a specific emulated instruction is decoded and a subroutine is constructed to implement a single instruction, such as in a C or subroutine driver, or some other technique is used to provide a driver for a given computer hardware as known to those skilled in the art after understanding the description of the embodiment invention. Various software and hardware emulation patents including, but not limited to, US Patent No. 5,551,013, US Patent Document No. 6,009,261, US Patent Document No. 5,574,873, US Patent No. 6,308,255, US Patent Document No. 6,463,582 and US Patent Document No. 5,790,825 show various known ways of obtaining instruction format emulation with a specific architecture adapted to different devices in the target device, available to experts in the field, as well as commercial software techniques used by the persons mentioned above.

[0082] Preferably, one or more aspects of the present invention improve system performance. For example, by selectively deleting buffer entries instead of completely clearing buffers, system performance is increased by not requiring unnecessary re-creation of entries. That is, it requires 20+ to 100s cycles to create a TLB entry, and selective cleanup avoids unnecessary re-creation of entries.

[0083] Another advantage is that if full TLB cleaning is required, then the implementation allows cleaning. In addition, the TLB may be considered as an empty order if, for example, the TLB is not used. Preferably, the IDTE instruction may be implemented

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- 36 hardware, firmware, software or a combination thereof, or can be used in the emulator of the target computer instruction set.

[0084] One or more aspects of the present invention are equally applicable, for example, a virtual machine emulation in which one or more pageable units (e.g., guests) is performed on one or more processors. As one example, pageable guests are defined by the Start Interpretive Execution (SIE) architecture, one example of which is described in the IBM publication entitled "IBM System / 370 Extended Architecture", IBM Publication No. SA22-7095 (1985).

[0085] Although SIE and z / Architecture are mentioned above, one or more aspects of the present invention are equally applicable to other architectures and / or environments using pageable entities or similar constructions.

[0086] Although an environment with logical partitions is described here, this is just one example. Aspects of the invention are beneficial for many types of environments, including other environments that have multiple zones, and for non-partitioned environments. In addition, there may not be central processor assemblies, but many processors connected together. In addition, one or more aspects of the invention may be used in single processor environments.

[0087] If the environment is logically partitioned, then more or fewer logical partitions may be included in the environment. In addition, there may be multiple central processing units connected to each other. These are just some of the varieties that can be made. In addition, other variations are possible. For example, although the driver described here serializes the instructions so that

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- 37 drivers.

at rest one IDTE instruction is executed at a time, in the next embodiment many instructions can be executed simultaneously. In addition, the environment can contain many

In addition, many status requests from one or more controllers) can occur concurrently in the system. Additional variations are also possible.

[0088] The term "processing unit" as used herein includes pageable entities such as guests; processors; emulators and / or other similar components. In addition, the term 'through the processing unit' includes a reference to the processing unit. The term "buffer" includes a memory region as well as other types of data structure containing, but not limited to, arrays; and the term "array" may include data structures other than the array type. In addition, the instruction may contain structure other than registers for determining information. In addition, the page, segment and / or area may have sizes that are different from those listed here.

[0089] One or more possibilities of the present invention may be implemented in software, firmware, computer hardware, or a combination thereof. In addition, one or more possibilities can be emulated.

[0090] One or more aspects of the present invention may be included in a manufactured product (e.g., in one or more computer program products) having, for example, media useful for a computer. The carrier has embedded, e.g., computer-readable program code or logic (e.g., instructions, code, commands, etc.) to provide and facilitate the feasibility of the present invention. The product can be made

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- 38 implemented as part of a computer system or may be sold separately.

[0091] In addition, at least one program memory device readable by the executing device, at least one instruction program that can be executed by the device to achieve the possibilities of the present invention can be provided.

[0092] The diagrams presented here are just examples. There may be many variants of the schemes or steps (or operations) described herein. For example, the steps may be performed in a different order or the steps may be added, removed or modified.

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