Tdm multichannel duplex radio system

The present invention is directed to providing a number of full duplex radio communication channels each using the same portion of the frequency spectrum.

According to the invention there is provided a duplex radio system comprising a multiplicity of terminals each of which includes a direct conversion receiver having a local oscillator, compression means for time compressing information to be transmitted for each channel, expansion means for time expanding transmitted information received from each channel, and means for modulating the signal produced by the local oscillator to produce the transmitted information.

Reference will now be made to the accompanying drawings

in which:Fig. 1 shows one fend of a multichannel system in accordance with an embodiment of the invention;

v Fig. 2 shows one form of baseband receiver suitable as

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the receiver 15;

Fig. 3 shows a detail of Fig. 1;

Fig. 4 shows a form of memory 21 of Fig. 1;

Fig. 5 shows one form of memory 22 of Fig. 1;

Fig. 6 shows an alternative form of memory 21 or 22 of Fig. 1 and

Fig. 7 shows one form of the control 23, 24, of Fig. 1.

Referring to Fig. 1 the analogue output of microphone 1 is passed via analogue to digital converter 2 for storage in digital memory 21. When a time slot is available, the stored information is read out as a burst of data and passes via

oscillator 5 and receiver 15 for transmission.

On the receive side, an incoming information burst passes via direct conversion (zero IF) receiver 15 to memory 22 and is read out from the store and passes via digital to analogue

converter 13 to transducer 14.

Control blocks 23, 24 determine when data can be transmitted in dependence on information on other channels received either directly or off-air.

Further end of the link assumes "master" status depending upon the originating direction of the call. The oscillator 5 is nominally in the centre of the operating band and for the

receive mode is unmodulated. For the transmit burst the oscillator is modulated and either transmitted directly or

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switching to the antenna. Any form of modulation may be

used. The control blocks monitor the state of the wideband

channel such as to decide which time slot is most appropriate for communicating. Dynamic channelling (trunking) is thus obtained without the need for a frequency synthesiser. In a typical application digitised voice would be sent over the duplex channel and the control function would include facilities for signalling and supervision of the line, e.g. call set up and clear down. The control function also continuously monitors the state of the transmission such as to

move the time slot being used and maintain the required

quality of transmission. This is necessary in the system as described since other users have asynchronous clocks and

thus drift relative to the time slots of the link considered

The local oscillator 5 may contain a surface acoustic wave

device.

Thus the system provides a number of full duplex radio communication channels each using the same portion of frequency spectrum. Each duplex channel operates independently

of the others and there is no fixed master control of the

system. By using a direct conversion (zero IF) radio

receiver in each equipment its local oscillator can be used

as the transmitter as well. The information to be transmitted

is broken down into blocks of data which are compressed in

time and sent as bursts of data in each direction so as to

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occupy a fraction of their original block length. In the

intervals between the bursts other transmitter/receiver combinations communicate which are operating nearby.

The use of a direct conversion receiver together with time duplex and time multiplex gives a simple single channel/ multichannel availability duplex radio link without the need for a separate transmitter and R.F. duplexing arrangements.

The control comprises two sections. Control section 23 performs the mechanical function of clocking data into and

out of the memories 21 and 22 at the correct rate and time.

If the terminal is acting as a slave, then control section 23 will also monitor incoming "raw" data from the receiver

15 in order that it can ensure that the transmitted data is

synchronised.

The multiplex facility is provided by the more intelligent channel selection control section 24. Depending on whether FDM or TDM is being used, control section 24 either controls the local oscillator frequency or assigns the time slots to be used by control section 23 through connection a or b respectively.

Control section 24 receives and decodes "off-air"

information about the status of the channels in the system and uses this to assign its present one.

In Ithe case of a "central" system e.g. a central transmit /receive unit in a cellular mobile radio system where many

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channels may be in use at the same location then control 24

would be arranged to receive channel information direct (connection c). Thus the central transmit/receive unit is adapted to provide communication with a number of remote units. In this case the central unit will assign the channels as required to the individual duplex equipment.

The receiver utilised in the present system does not process signals that consist simultaneously of components

of both transmitted and received waveform since the receive

and transmit functions are time-multiplexed. For this reason the zero IF receiver need not necessarity be one that demodulates F.M., although preferably it is.

An embodiment of a receiver 15 is shown in Fig. 2 of the drawings. Referring to Fig. 2 the baseband receiver shown includes the mixer/splitter/combiner circuit 6 which receives the signals from the antenna An and the local oscillator 5 to mix the signals down to baseband and provides four channels spaced at 45 degrees intervals. This is because the modulation index used would probably be 0.707.

The circuit 6 also has a switch to load all the local oscillator power to the antenna for transmission and prevent this leakage during reception.

The signals in the four channels are fed via respective

low pass filters LP1, LP2, LP3, LP4 to respective limiting

amplifiers LAI, LA2, LA3, LA4. The four channels are then

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combined back into two channels A and B in quadrature using two OR gates Ga and Gb.

The outputs of channels A and B are applied to an exclusive OR gate 36 which receives the channel waveforms and provides a square wave output at twice the deviation frequency. Blocks 31 and 34 will, in response to every edge in channel A or B respectively, produce a short pulse which sets or resets a flip-flop 32. A longer pulse (of the length required for output) is produced by block 33 which closes an analogue switch 38 for the duration of the pulse. Blocks 31, 33, 34 could be realised by an exclusive OR and a resistor and a capacitor, for example, but the man skilled in the art will realise alternative arrangements depending on the application. In general terms blocks 31, 33, 34 can be described as monostables triggerable by either positive or negative-going pulses. The output pulse of block 33 has a polarity determined by the exclusive OR 36 and exclusive OR 35 through flip-flop 32. This output pulse is applied to junction g between two resistors of equal value R^ and R₂ so that the voltage of the pulse at g is either 0 Volts when signal e is zero and the switch 38 is

closed or V when signal e is a "1" and the switch 38 is cc _

closed. Thus the waveform shows whether the incoming r.f. signal is above or below the local oscillator frequency, and this is multiplied by the series of pulses of waveform since

waveform c

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changes its polarity at each edge (both positive and negative)

of the deviation frequency. When the analogue gate 38 is

open, point g is at 1/2 V_cc·

Low-pass or band-pass filter 37 produces an approximation of an analogue output.

The analogue output is fed to a slicing circuit 39 which slices the output so that above a threshold voltage the circuit produces a logic 1 and anything below it produces a logic 0.

The output of the slicing circuit 39 is the output 15a of the baseband receiver 15 shown in Fig. 1 of the drawings.

One form of item 6. in Fig. 1 is shown in Fig. 3. Switch SW switches between receive and transmit modes to feed a premixer R.F. amplifier . AMP for reception and to transmit the oscillator modulation signal via a power amplifier PA for

transmission. As an alternative to the direct modulation of

the oscillator, the modulation can be applied to an electrically controllable phase shift network PSN interposed between

the local oscillator 5 and the antenna An.

The function of memory 21 in Fig. 1 is to continuously clock in data at the lower bit rate from A/D converter 2, and at times specified by control 23 to clock out the same data in blocks at a higher data-rate.

Memory 22 performs the reverse function by continuously clocking data out at a low bit rate into D/A converter 13 that

N.Z. PATENT OF:- IGii

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has been clocked into it in bursts at a higher bit rate.

Provision can be made in memory 21 for adding a syncword to the data blocks before they are released, and in memory 22 for extracting a syncword from the fast input data so that it does not get clocked into the D/A converter 13. Fig. 4 shows one form of such a memory. Data is continuously clocked into shift registers SRl and SR2, but they are clocked at different rates. Thus if SW1 is in the "UP" position then SRl is clocked at the fast (Output) rate and ST2 is clocking in data at the slow rate from A/D converter 2. As soon as it is full SWl is moved to the "DOWN" position, and the stored data is clocked fast, at the correct time, through SR3 which is preloaded with the syncword (should this be required). Meanwhile SRl has been carrying on loading the data at the slow rate. (NB: while the previous data is being clocked out fast, new, meaningless data is being clocked in from the A/D converter 2.

This does not matter, however, since as soon as the valid data bits have been output, a shift register SR3 is switched over to the other shift register ready to accept some new and

valid data.

The total length of the transmitted burst is "n + m" bits (m = syncword length) and the time that it must be transmitted in is 9Γ where "r" is the A/D bit rate and "p" is the number of TDM channels in a TDM system.

The transmitted bit rate is therefore:202041

2pr (η + m)

η

It should also be noted that the fast clock is in general not continuous but consists of bursts of (n + m) pulses.

Fig. 5 shows a similar format for the receive memory 22 5 where n bits are clocked into a shift register SR4 (at the

correct time). The n bits are then clocked slowly into the D/A converter 13 while the other shift register SR5 stands by

to receive its burst from the receiver 15. Switch SW2 is

controlled in a way similar to SW1 in Fig. 4.

10 Fig. 6 shows another method of realising the memories

which is conservative of storage, but requires a parallel loading facility.

Shift register SR6 and SR7 are continuously clocked synchronously with the A/D and D/A converters 2 and 13, res15 pectively, shift register SR8 is the clocked at the correct

times a) to load data from the receiver, and b) to pass data to the transmitter. After a) has occurred, SR7 is parallel loaded from SR8, maintaining a continuous valid stream of data to the D/A converter 13. SR8 is the ready to parallel

20 load from SR6 before sending its block of data through SR9

to the transmitter. SR9 is pre-loaded with syncword at the

same time as SR7 is loaded.

Fig. 7 shows the main circuit blocks for the CONTROLS

23 and 24. This is for a slave terminal. A master would not

25 have bit sync or sync recogniser, but would generate pulses

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to load sync words into the transmitter memory.

The pulses and clock directing circuitry is a set of logic switches arranged to control the memories in the correct fashion operating from the information gained from

5 the sync detector and microprocessor bus.

A bit synchronism BS feeds a control pulse generator CPG which provides control pulses to a sync word recogniser SWR and sync detector SD. A clock frequency generator CFG provides fast and slow clock frequencies to a pulse and closk

10 cirecting circuit PD. Circuit PD comprises a set of logic

switches arranged to control the memories 21 and 22 in the correct fashion and operating from the information gained from the sync detector SD and a microprocessor bus forming part of control 24.

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