Radio transmission system

Agent (s): Jean Pothet

Radio transmission system.

(57) The invention relates to a radio transmission system comprising numerous transceiver terminals.

Each receiver, of the direct conversion type, comprises a local oscillator 5, a device 21 for the compression over time of the information to be transmitted, a device 22 for the expansion in time of the information received, as well as means a for modulating the frequency of the signal generated by the local oscillator in order to produce the transmission signal.

The invention applies in particular to radiotelephony.

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FR 2,538,642

D

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The present invention relates to a multi-channel duplex radio-electric transmission system, particularly a system which is in the form of portable radio-electric transceiver equipment, such as radio telephones.

From British Patent No. 1,556,087, a single channel duplex transmission system is known.

In such a system, the receiving party uses the method of demodulation known as zero Intermediate Frequency (IF) or direct conversion. Such a method is described in British Patent N °

530 602 and in another French application filed today by the applicant for a direct conversion radio receiver for frequency modulated signals. In short, signals from a local oscillator phase shifted in quadrature at the carrier wave frequency are individually mi xed with the modulated audio input signal. The resulting signals have a zero intermediate frequency and the two side bands overlap in baseband and extend from the frequency of a continuous signal to the single side bandwidth of the original signal. The mixer outputs include low-pass filters and amplifiers that reduce the signals to a normal level. The two signals are then differentiated separately. Each differentiated signal is then multiplied by the input signal from the other differentiator and the output from one of the multipliers is subtracted from the other.

According to British Patent Application No. 8027566, a duplexed single-channel radio transmitter and receiver system is known. The null IF or direct conversion demodulation method is again used, but the radio signals are transmitted in digital form.

The transmission is effected by means of digital signals modulated by frequency displacement, the transmitter comprising a source of digital signals and a local oscillator whose frequency can be modulated by digital signals in order to generate signals modulated by frequency displacement. The signals modulated by frequency displacement of the local oscillator are coupled to a transmission medium, and mixed at the receiving end of this medium with the output signals of the local oscillator in order to provide signals of s

quadrature output, these being applied to a null Fl demodulator which generates a delayed digital output signal and addressed to a digital circuit in which cancellation is carried out with respect to the corresponding digital signals generated by a distribution and combination.

The object of the present invention is to provide a number of duplex radio communication channels, each channel using the same portion of the frequency spectrum.

According to the invention, this objective is achieved by the fact that there is a duplex radio system comprising a large number of terminals each equipped with a direct conversion receiver consisting of, a local oscillator, a means of compression for · 'compression over time of .1'.information? to be transmitted on each channel, an expansion means for the expansion over time of the information which is received on each channel, · and of a signal modulation device generated by the local oscillator. to produce the information transmitted.

The invention will be better understood on reading the detailed description which follows, given by way of nonlimiting example, with reference to the appended figures among which:

Fig. 1 shows one end of a multi-channel system according to an embodiment of the invention.

Fig. 2 shows a form of baseband receiver suitable for receiver 15;

Fig. 3 shows a detail of FIG. 1;

Fig. 4 shows a form of memory 21 in FIG. 1;

Fig. 5 shows a form of memory 22 in FIG. 1;

Fig. 6 shows another possible form of memory 21 or 22 in FIG. 1, and. "Fig. 7 shows a form of control module 23, 24 in FIG. 1. /

According to FIG. 1 the analog output signals of the microphone 1 are converted into digital signals by the analog / digital converter 2, then stored in the digital memory 21. When a time interval is free, the stored information -are read in the form of a group of data and pass through the oscillator 5 and the receiver 15 for the purpose of transmission.

On the receiver side, a group of input data passes through the direct conversion receiver (zero IF) to the memory 22; then the memory is emptied and the data is applied to the digital / analog converter 13, then to the transducer 14.

The control blocks 23, 24 determine the instant of data transmission as a function of the information present on the other channels and received either directly or by antenna.

Each end of the link assumes a master state according to the point of origin of the call. The main position of oscillator 5 is in the center of the operating band, and it is not modulated in reception. On a group of transmitting data, the frequency of the oscillator is modulated and transmitted either directly (according to British Patent Application No. 44368/78 for example) or by antenna. Any form of modulation can be used. The control blocks monitor the state of the broadband channel so as to detect the time interval that will be most conducive to transmission. This gives a dynamic distribution of channels (establishment of links) without the need to use a frequency synthesizer. A typical application would consist in transmitting a digitized phonic message on the duplex channel, a link for which the control functions would include possibilities for signaling and supervision of the line, for example for setting up and ending the call. In addition, the control function continuously monitors the state of the transmission so as to shift the time interval in service and preserve the required transmission quality. This is made necessary in the system as described because the other users have asynchronous timers which cause a drift with respect to the time intervals of the link considered. The local oscillator 5 can contain a surface acoustic wave device.

Thus we have in this way several duplex radio transmission channels each using the same portion of the frequency spectrum. Each duplex channel operates independently of the others and the system has no fixed main controls. The incorporation of a direct conversion radio receiver (zero IF) into each piece of equipment also makes it possible to use its local oscillator as a transmitter. The information to be transmitted is broken down into blocks of data processed by time compression and sent in the form of groups of data in each direction so as to occupy a fraction of the length of their original block. Other combinations of neighboring transmitters / receivers may communicate in the intervals between the data groups.

The use of a direct conversion receiver in conjunction with a duplex and a time sharing multiplex results in a duplex radio link in single or multiple channels for which there is no need to resort to the use of '' a separate HF transmitter and duplexer.

The orders are divided into two sections.

The control block 23 performs the mechanical function of transmitting and receiving synchronization data from and to the memories 21 and 22 at the desired rate and at the desired times. If the terminal operates as a slave, the control block 23 will then also monitor the raw input data coming from the receiver 15 so as to ensure the synchronization of the transmitted data.

Multiplexing depends on the control block 24 responsible for selecting the channels and whose capacity is greater. Depending on whether one uses frequency division multiplexing or time sharing multiplexing, block 24 is responsible either for controlling the frequency of the local oscillator or for determining the time intervals which will be used by the block of command 23, on the links (a) or (b) respectively.

The control block 24 receives and decodes the information entering by antenna so as to know the states of the channels of the system and uses the result for the allocation of its own channel at this precise moment.

In the case of a centralized system, for example a central transceiver incorporated in a cellular mobile radio system in which a large number of channels can be in service at the same location., The control unit 24 would then be arranged to receive channel information directly (link c). Thus the central transceiver would make it possible to establish communications with a certain number of remote devices. In this case, the central unit would allocate the channels on demand to the various devices working in duplex.

The receiver used in the system which is the subject of the present invention does not process the signals consisting simultaneously of components of the transmitted and received waveforms, since the reception and transmission functions are multiplexed by time sharing. For this reason, it is not necessary for the null IF receiver to be able to demodulate the EiM. although this is desirable.

An embodiment of the receiver 15 is illustrated in FIG. 2 provided in annex. According to FIG. 2, the baseband receiver shown comprises the mixer / distributor / combination circuit 6 which receives the

Signals from the An antenna, the local oscillator 5 allowing the mixing of the signals on the baseband and four channels spaced at 45 ° intervals. This is because the modulation index is likely to be 0.707. Circuit 6 is also provided with a switch making it possible to switch all of the power of the local oscillator on the antenna for the purpose of transmission and to avoid the leakage of this power on reception.

The signals conveyed by the four channels pass respectively through the low-pass filters, LP1, LP2, LP3, LP4, and respectively arrive at the clipping amplifiers LAI, LA2, LA3, LA4. The four channels are then recombined into two channels A and B arranged in quadrature by means of two OR circuits Ga and Gb ·

The output signals from channels A and B are applied to points a and b. An exclusive OR circuit 36 ​​receives the waveforms present on the channels and delivers a square output signal at a frequency twice the deflection frequency. Blocks 31 and 34, in response to each pulse edge appearing on channels A and B respectively, will deliver a short pulse which will control flip-flop 32 to 1 or O.

A pulse of longer duration (of the required length at output) is generated by block 33 which closes an analog switch 38 for the duration of the pulse. The blocks 31, 33, 34 can be produced by means of an exclusive OR, a resistor and a capacitor for example, but the specialist will be free to carry out other assemblies according to the particular applications. In general, the blocks 31, 33, 34 can be described in the form of monostables triggered by positive or negative pulses. The polarity of the output pulse of the block 33 taken at f is determined by the exclusive OR circuits 36 and 35 via the flip-flop 32. This output pulse is applied to the junction g between two resistors RI and R2 of equal value so that the polarity of the pulse in gr is equal to OV when the signal e is at 0 and the switch 38 closed, or equal to V when the signal e is at 1 and the switch 38 closed. The waveform therefore indicates whether the input HF signal is higher or lower than the frequency of. the local oscillator, and this indication is multiplied by the series of pulses of the waveform c, because it will be noted that the polarity of the latter changes with each pulse edge (both positive and negative) by the frequency of deviation. When the analog door 3.8 is open, the potential at point 2 is 1/2 V_CC,

The low-pass or band-pass filter 37 generates an approximation of analog output signal h.

Signal h is then applied to a limiting circuit 39 which limits the output signal so as to generate a logic state 1 above a threshold voltage, and a logic state O below.

The output signal of the limiter circuit 39 appears at 15a from the baseband receiver 15 shown in FIG. 1 provided in annex.

A form of the module 6 of FIG. 1 is shown in FIG. 3. The selector SW switches between the reception and transmission modes in order to supply an AMP pre-mixer amplifier AMP in reception and to transmit the signal modulated by the oscillator through a power amplifier PA in transmission . With regard to the direct modulation of the oscillator, it is also possible to apply this modulation to a phase shifter PSN electrically controlled and inserted between the local oscillator 5 and the antenna An.

The function of memory 21 represented by the

Fig. 1 is to continuously rhythmize the input data according to the lowest bit rate coming from the A / D converter 2, and at the instants stipulated by the control block 23, to rhythm the same output data in blocks at a faster rate Student.

- The memory 22 is responsible for the inverse function by continuously rhythmizing the output data at a low ⁸ bit rate before entering the D / A converter 13 which has been internally synchronized according to higher bit rate data groups.

It is possible to provide the memory 21 with a device for adding a synchronization word to the data blocks before they are transmitted, and for the memory 22 with a device for extracting the synchronization word high rate input data so that no synchronization occurs in the D / A converter 19. FIG. 4 shows such a form of memory. Data is continuously paced in the shift registers SRI and SR2, but at different rates. Thus when the selector SW1 is in the HIGH position, the register SRI is paced at a fast (output) rate and SR2 paces at a slow rate the input data coming from the converter-A / D 2. As soon as the register is full, SW1 goes to the DOWN position, and the memorized data are paced at a fast rate, at the desired moment, via SR3 which has been loaded beforehand by the synchronization word (if necessary) . In the meantime SRI has continued to change the data at slow rate (Note while the previous data is paced at output at a fast rate, new non-significant data is paced at input from the A / D converter 2). However, this does not matter because as soon as the correct data bits are output, the shift register SR3 switches to the first register ready to receive new correct data.

The total length of the transmitted data group is equal to n + m bits (m = length of the synchronization word) and the insertion time is ^_rf where r is the bit rate of the A / D converter and p is the number of time-sharing multiplex channels making up the system.

The transmission bit rate is therefore equal to

2pr (n + m) n

It will be noted that the fast clock pulses are generally not continuous, but that they are made up of groups of (n + m) pulses.

Fig. 5 shows a similar format for the memory 22 in which n bits are synchronized in a shift register SR4 (at the desired time). The n bits are then synchronized at a slow rate in the D / A converter 13 while the other shift register SR5 is awaiting reception of the data groups coming from the receiver 15 „The selector SW2 operates in a similar manner to the selector SW1 of Fig. 4.

Fig. 6 shows another method of producing memories in which the stored data is preserved, but which requires a parallel loading device.

The shift registers SR6 and SR7 are continuously paced and synchronously with the converters A / D 2 and D / A 13, then the shift register SR8 is paced at the desired times a) to load the data coming from the receiver, b) to transfer the data to the transmitter. When event (a) has taken place, SR7 is loaded in parallel from SR8 and permanently sends a correct data rate to the D / A converter 13. Then SR8 is ready to receive a parallel loading from SR6 before sending its own data blocks M to the transmitter via SR9 '. The register SR9 is preloaded by the synchronization word simultaneously with the loading of SR7.

Fig. 7 shows in the form of a block diagram the main modules of the control blocks 23 and 24. This corresponds to a slave terminal. A master terminal would not have bit synchronization or a synchronization word identifier, but it would deliver pulses intended to load the synchronization words into the memory of the transmitter.

The pulse and clock control circuit is a set of logic gates arranged so as to properly control the memories from information coming from the synchronization detector and from the microprocessor bus.

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A bit synchronizer BS feeds a generator of control pulses CPG which addresses these pulses to a word identifier of. SWR synchronization and an SD synchronization detector. A base frequency generator CFG provides fast and slow base frequencies to a PD pulse and clock director circuit. The PD circuit is composed of a set of logic gates arranged so as to properly control the memories 21 and 22 and activated by the information coming from the synchronization detector SD and from a microprocessor bus forming an integral part of the control block 24. It remains obvious that the above description has been given only by way of nonlimiting example and that other variants can be envisaged without departing from the scope of the invention.