An arithmetic unit for structure arithmetic.

The invention relates to a very fast memory bit cell for Implementation in VLSI technology. Many blt cells can be packed very tightly. The blt cells include: a cell circuit (T1, T2, L1, L2, D1, D2; T1, T2, II, 12, D1, D2) in which a bit value can be stored, which value is either 'true' or 'false'; a first connection (Vcc) which is constantly supplied with a supply voltage, a second, a third and a fourth connection (acc, d, d) each of which is adjustable in different control states; which cell circuit is such that each combination of control states for the second, third and fourth connections sets the memory bit cell to a single one among a set of function states.