Method and circuit arrangement for transcoding code words

CLAIMING THE PRIORITY OF THE PATENT / QVhi. - Sign up

IN: THE FEDERAL REPUBLIC OF GERMANY

Dated: September 1, 1982

PATENT APPLICATION in

Luxembourg

Applicant: Siemens Aktiengesellschaft Berlin and Munich

Re: method and circuit arrangement for recoding of

Codewords.

SIEMENS AKTIENGESELLSCHAFT

Berlin and Munich

Our sign

VP_A. 82 P m 5 DE • Method and circuit arrangement for recoding code words

The invention relates to a recoding of 5 code words of a code with m-digit code words into the corresponding code words of another code with likewise m-digit code words.

In digital communication technology and also in data processing technology, information for the purpose of forwarding or processing is represented by a digital signal composed of sequences of so-called code words, with the code words possibly obtained from an underlying analog signal by continuously repeated sampling, quantization and coding can be and thus correspond to the respective analog signal sample value.

For the relationship between the analog signal values ​​of a telephone analog signal and the code words 20 of a corresponding telephone digital signal, there are two CCITT recommendations, which are commonly referred to as A-law and / i-law and which both have a logarithmic quantization interval / analog signal value

Approximate the companding curve by means of a segment25 linear kink curve. Although the buckling curve following the so-called A-law is in one

Digital / analog converter in circuitry particularly favorable way with the help of a constant current

Spr 1 Kel / 31.8.82

- 2 - vpa 82 P 1 7 h 5 DE supplied so-called R-2R network can be implemented, in some countries preference is given to the / i characteristic curve, which is less easy to implement. This has the consequence that if necessary For communication devices that are basically the same but that are used in different countries, different encoders / decoders have to be provided, which results in an undesirable reduction in the number of pieces required for large-scale integration, or, starting from a uniform codec, an additional one Recoding of the output or input bits must effect, for example, by means of an arithmetic unit.

The invention is based on the object of avoiding such increases in expenditure and instead showing another way of recoding the type outlined at the beginning.

The invention relates to a method for recoding 20 code words of a code with m-digit code words into the corresponding code words of another code with likewise m-digit code words; According to the invention, this method is characterized in that the individual bits of the code word to be recoded during this.

serial input into an m-digit shift register or during the serial output therefrom from register stage to register stage in each case via a relay circuit in accordance with the agreement or non-agreement of the individual bits of the transcoding 30 Cbdewort of the one code and the corresponding code word of the other code in the manner not negated or . are passed on negated, that the passing bits in each case before and after one with their position within the shift register of the position does not match

Bits within the two code words corresponding register stage experience a negation.

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The invention, which is not tied to the recoding of A-law code words into / j-law code words and vice versa, but also to another with the same

Bit rate recoding in progress, for example the inversion of every second bit required in the course of A-law encoding or also in what is known as S'Crambling, enables recoding that takes place at the same bit rate with very little circuitry effort, in particular also insofar as, in a further development of the invention, at the beginning or end of a transmission path, for example for buffering and / or for parallel / serial or Serial / parallel conversion already existing shift registers only need to be supplemented with appropriate transfer circuits and can then be used for the recoding according to the invention} here, in messages | serially sending and receiving G_edevices that use the same shift register for sending and receiving that use the

Shift register stages associated transfer circuits are also used twice.

I.

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The invention will be explained in more detail with the aid of the drawing. It shows

1 schematically shows an embodiment of a

Circuit arrangement for recoding according to the invention;

FIG. 2 shows further circuit details of such a circuit arrangement.

In FIG. 1, an embodiment of a circuit arrangement for recoding code words of one code with m-digit code words into the corresponding code words of another code with likewise m-digit code words according to the invention is shown schematically to the extent necessary to understand the invention. In this circuit arrangement, an m-digit shift register is provided, each with a set input D and a reset input D and, in addition to an output Q, a complementary output Q having register stages RmS, ..., RjS, RiS, ..., R1S. Forwarding circuits eWm, mWm-1, ..., jWi, ..., 2W1, 1Wa are in front of and behind the register stages. Depending on a control bit applied to the control input eum of the forwarding circuit eWm, the input e of the shift register is connected to the set input D or the reset input D of the register stage RmS and the complementary input e of the shift register is connected to the reset input D or the set input D of the register stage RmS. In accordance with the following transfer circuits ..., jWi, ... pending control bits is the output of a preceding register stage with the set input or the reset input of the following register stage and the complementary output of the preceding register stage with the _ 5 - vpa P 1 7 b DE

Reset input or the set input of the respective subsequent register stage; for example, according to the control bit applied to the control input jui of the relay circuit jWi, the output 5 Q of the preceding register stage RjS is connected to the set input D or the reset input D of the subsequent register stage RiS and the complementary output Q of the register stage RjS is connected to the reset input D or the set input D. the register level RiS. Finally, in accordance with the control bit present at the control input 1ua of the relay circuit 1Wa, the output Q of the register stage R1S is connected to the output a or the complementary output â of the shift register and the complementary output Q of the register stage R1S is connected to the complementary output ä or the output a of the shift register.

The negation of bits of an m-bit code word to be re-encoded and thus its re-encoding now takes place in the manner that when the code word to be re-encoded is entered serially before and after that register stage whose position in the shift register corresponds to the position of the relevant bit in the code word, by switching the relevant, for this purpose, the respective passing bits of the code word are negated at their control inputs to which the corresponding control bits are applied. Each bit actually to be negated experiences just one negation (or an odd number of negations), while each bit not to be negated experiences zero or two negations 30 (or an even number of negations) and thus remains unchanged in the result. As soon as the last bit of the code word to be re-encoded has been entered into the shift register RmS, ..., RjS, RiS, ..., R1S, the re-encoded code word is already in the shift register instead of the code word to be re-encoded,

- 6 - VPA 82 P 1 7 4 5 OE then for example in parallel or also - but now with no line crossing and therefore none

Negation causing transfer switching - can be output serially.

As an alternative to this, it is also possible to enter the code word to be recoded in parallel or, in the case of line-crossing-free and thus no negation-causing transfer circuits, in series in the shift register RmS, ..., RjS, RiS, ..., R1S and to do the recoding only when the serial code word is output by switching the forwarding circuit accordingly during the code word output, dai3 again depending on the agreement or Inconsistency of the individual bits of the code word to be recoded of the one code and the corresponding code word of the other code are passed on in a non-negated or negated manner in such a way that the bits passing through are passed before and after a register stage whose position within the shift register corresponds to the position of 20 bits which do not correspond within the corresponds to both code words, one

Experience negation.

The relay circuits can, as can be seen in further details from FIG The transistor switches connected to the X circuit can be acted upon with the respective control bit and the respective other transistor switches with the negated control bit at 50. In Figure 2 it is indicated that the control electrodes of the two so to speak uncrossed through-switching transistor switches 1 and 2 directly to the

- 7 - VPA 82 P 1 7 4 5 QE the respective control line carrying the relevant control bit is connected, while the control electrodes of the two transistor switches 3 and U, which are each so to speak crossed through, are connected via a NOT element

NOT are connected to the respective control line carrying the relevant control bit.

In the circuit arrangement according to FIG. 2, the control information controlling the recoding is in the form of a

Control bytes applied in parallel to the control lines, the individual control bits being output by the individual cells of a control information register Um, ..., Uj, Ui ..., U1. By entering a corresponding control byte, any recoding of m-digit code words of one code into the corresponding m-digit code words of another code can be effected.

Alternatively - and without this being shown in the drawing - it is also possible to connect a tiny control bit line directly or via an inverter to the control electrodes of the transistor switches of the individual transfer circuits in such a way that the desired recoding when shifting the contents of the shift register RmS, ..., RjS,

RiS, ..., R1S takes place.

If, as can be seen from FIG. 2, the control information is provided in the form of a control byte in parallel representation, it is also possible, as can also be seen from FIG Transfer circuit lying between two register levels, for example the register levels RjS and RiS, in the example the transfer circuit jWi,

- 8 - VPA 82 P 1 7 4 5 OE leading control line jui is the output line of an EXCLUSIVE-OR element EXOR, whose two inputs are supplied with those two control bits whose positions within the control byte correspond to the positions of the 5 two register levels (RjS and RiS ) within the shift register.

If, for example, all bits of each code word are to be negated with the exception of the first bit in each case, as would be the case, for example, with an A-lawZ / j-law recoding, the serial input or output of the code word that is recoded in the process is converted into or . from the shift register RmS, ..., RjS, RiS, ..., R1S from all control information cells Um, ..., Uj, Ui ... - with the exception of 15 of the control information cell U1 providing a control bit 0 - a control bit “1 provided. The control bits are linked in pairs in the EXCLUSIVE-OR elements EXOR, so that in the 20 transfer circuits mWm-1, ..., jWi, ..., 2W1 connected to the EXCLUSIVE-OR elements EXOR with their control lines, the one crossed Through-switching causing transistor switches 3 and 4 only the relay circuit 2W1 are controlled in the conductive state, while in the other relay circuits mWm-1, ..., jWi. the transistor 25 switches 3 and 4 remain in the blocking state and the

Transistor switches 1 and 2 each cause uncrossed through-connection there. In addition, the control bit “1” output by the control information cell Um in the relay circuit eWm controls the transistor switches 3 and 4, which cause a crossed circuit, to the conductive state; the control bit 0 ”output by the control information cell U1 finally holds the transistor switches 1 and 2 im causing uncrossed connection in the relay circuit 1Wa

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Leading state. This means that of all the bits of a code word entered serially into the shift register RmS, ..., RjS, RiS, ..., R1S via the input terminals e and ë, only that up to the shift register stage

The first bit passing through R1S is negated twice, namely in the forwarding circuits eWm and 2W1, while the following bits each experience only one negation, namely in the forwarding circuit eWm. This then stands for the complete serial

Input of the code word to be recoded into the shift register in this precisely the recoded code word, which can then be read out of the shift register in parallel or - without further negations - also serially.

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